CN116075927A - 前段工艺互连结构以及相关联系统和方法 - Google Patents

前段工艺互连结构以及相关联系统和方法 Download PDF

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CN116075927A
CN116075927A CN202180052883.9A CN202180052883A CN116075927A CN 116075927 A CN116075927 A CN 116075927A CN 202180052883 A CN202180052883 A CN 202180052883A CN 116075927 A CN116075927 A CN 116075927A
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semiconductor device
dielectric material
front side
trench
conformal dielectric
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K·K·柯比
K·R·帕雷克
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Micron Technology Inc
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Abstract

用于半导体装置的系统和方法，所述半导体装置包括：前侧处具有沟槽的衬底材料；位于所述衬底材料的所述前侧的至少一部分上方且位于所述沟槽中的保形电介质材料；位于所述沟槽中的所述保形电介质材料之上的填充电介质材料；以及在前段工艺(FEOL)处理期间形成的导电部分。所述导电部分可包含FEOL互连通孔，其延伸穿过所述填充电介质材料和所述保形电介质材料的至少一部分，具有限定延伸超出所述半导体衬底材料的所述前侧的前侧电连接件的前侧部分和限定有源接触表面的背侧部分。所述导电部分可延伸横过所述保形电介质材料的至少一部分和所述填充电介质材料，并且具有限定有源接触表面的背侧表面。

Description

前段工艺互连结构以及相关联系统和方法
相关申请案的交叉引用
本申请要求于2020年8月28日提交的第63/071,983号美国临时专利申请案以及于2021年5月19日提交的第17/325,090号美国专利申请案的权益和优先权，所述申请案以全文引用的方式并入本文中。
技术领域
本公开大体上涉及半导体装置，并且在若干实施例中，更具体地涉及形成用于背侧电连接件的预定位的前段工艺互连结构的系统和方法。
背景技术
微电子装置，例如存储器装置、微处理器和发光二极管，通常包含安装到衬底且包覆在保护性覆盖物中的一或多个半导体裸片。半导体裸片包含功能特征，例如存储器单元、处理器电路、互连电路系统等。为减少半导体裸片所占的体积、同时增大所得经包封组件的容量和/或速度，半导体裸片制造商承受着越来越大的压力。为满足这些和其它需求，半导体裸片制造商通常以竖直叠加方式堆叠多个半导体裸片，以增大半导体裸片所安装到的电路板或其它元件上的有限容积内的微电子装置的容量或性能。在竖直半导体裸片堆叠组件中，穿硅通孔(TSV)通常用于形成穿过裸片的电连接。
半导体装置最初使用前段工艺(FEOL)处理制造，其中在半导体衬底的有源侧形成个别装置(晶体管、电容器、电阻器等)。在常规半导体装置组件中，衬底的后段工艺(BEOL)处理用于形成用于背侧电连接件的各种互连件，例如穿硅通孔、金属化层、接合衬垫等。用于形成互连件的常规BEOL处理方法需要大量处理时间和复杂的制造操作，并且还具有用于布设配置的受限设计选择。BEOL处理通常紧接在探测阶段之前发生，其中从半导体装置的内部节点物理地获取信号以用于故障分析和缺陷检测。
附图说明
图1A-1E是示出根据本发明技术的实施例的制造具有前段工艺互连结构的半导体装置的各个阶段的放大横截面视图。
图2A和2B是示出图1A-1E的半导体装置的组件配置的实施例的放大横截面视图。
图3A-3F是根据本发明技术的实施例的制造具有前段工艺互连结构的半导体装置的各个阶段的放大横截面视图。
图4是根据本发明技术的实施例的包含半导体装置的系统的示意图。
具体实施方式
本文中所公开的技术涉及半导体装置、具有半导体装置的系统，以及用于制造半导体装置的相关方法。术语“半导体装置”一般指包含一或多种半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置和二极管等。此外，术语“半导体装置”可指成品装置或成为成品装置之前的各个处理阶段时的组件或其它结构。
取决于其使用的上下文，术语“衬底”可指支撑电子部件(例如，裸片)的结构，例如晶片级衬底，或经单分裸片级衬底，或用于裸片堆叠应用的另一裸片。可在晶片级或在裸片级执行本文中所描述的方法的适当步骤。此外，除非上下文另有指示，否则可使用常规的半导体制造技术来形成本文中所公开的结构。例如，材料可使用化学气相沉积、物理气相沉积、原子层沉积、旋涂、电镀和/或其它合适的技术沉积。类似地，例如，可使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它合适的技术来去除材料。
本发明技术包含一种半导体装置，其具有用于在前段工艺(FEOL)处理期间嵌入(例如，“预定位”)的背侧电连接件的互连结构。FEOL处理为其中在半导体材料的有源侧形成个别装置(晶体管、电容器、电阻器等)的集成电路制造阶段。与本发明技术相比，FEOL过程发生于在背侧制造金属互连结构之前。常规半导体装置封装使用后段工艺(BEOL)处理以形成接触衬垫、穿硅通孔、互连线和/或电介质结构，还包括其它过程。在BEOL处理期间，金属和/或电介质材料沉积在晶片上以产生用于晶片与晶片和晶片与封装连接的接触件、绝缘材料、金属层级和/或接合位点。在BEOL处理之后，执行探测阶段以物理地从半导体装置的内部节点获取信号以用于故障分析和缺陷检测。在探测阶段之后，执行后探测处理，包含前侧和/或背侧上的过程，包含例如三维集成(3DI)处理以及其它处理。
本发明技术一般涉及在FEOL处理(例如，栅极级处理)期间在裸片的有源侧处或附近形成互连结构，以及在BEOL或具有超薄硅处理、全硅去除和/或图案化的后探测处理期间暴露或以其它方式接近预定位的互连结构。在一些实施例中，与常规过程相比，本发明技术消除了形成BEOL互连件的需要，允许直接到装置布设，允许在制造的早期阶段进行探测测试，并且实现了超薄裸片堆叠以及其它优点。在一些实施例中，浅互连区域邻近浅沟槽隔离(STI)结构定位，并且在FEOL处理期间在衬底之中或之上形成。经FEOL处理的互连件或互连区域具有有源接触表面或3Dx接触件，其在FEOL处理期间在装置背侧上掩埋在硅和/或电介质材料内。随后显露FEOL互连件的有源表面以用于在BEOL或后探测处理期间从背侧接近。
各种FEOL互连配置在本发明技术的范围内，例如阵列、牺牲氧化物等，或其任何组合。预期使用本发明技术处理三维集成(3DI)降低成本且提供用于布设和其它结构的高度设计灵活性。例如，背侧布设部件可在FEOL处理期间形成，并在BEOL或后探测处理期间接近以便通过衬底进行电连接，如下文将描述。相比之下，常规处理需要在BEOL处理期间通过图案化、蚀刻和填充来形成背侧布设部件以形成穿硅通孔，这带来了各种挑战，例如蚀刻和填充相对较深的孔、在不损坏薄层的情况下进行处理等。在这些方面，本发明技术的装置连接件比常规的装置连接件更直接地集成。一些实施例可应用于例如NAND电路等接合微电子装置。在这些配置中，单独的互补金属氧化物半导体(CMOS)和阵列芯片可以面对面、面对背或背对背方式接合在一起。在FEOL处理期间，FEOL互连件预定位在阵列芯片的衬底材料或绝缘材料中，并接近以便通过阵列芯片的背侧进行电连接。在一些实施例中，CMOS组件包含支持阵列的外围电路装置，但通常不包含存储器单元和存取装置；阵列组件包含字线、位线、存取装置和存储器单元，但一般不包含驱动器、锁存器、控制器、稳压器等外围电路装置。
图1A-1E示出根据本发明技术的实施例的制造包括阵列芯片组件100(“阵列组件100”)的半导体装置的各个阶段的放大横截面视图。阵列组件100包含多层硅衬底，其具有块状硅区域108、第一植入区域109和第二植入区域110，其中区域108、109和110经配置以接收阵列组件100的各种材料和部件。阵列组件100还具有由延伸穿过至少第一植入区域109和第二植入区域110的侧壁111a限定的沟槽区域，且在一些实施例中，侧壁111a延伸到至少部分地进入块状硅区域108中的深度以形成底部表面111b。阵列组件进一步包含电介质材料112、填充材料116和孔113中的FEOL导电互连通孔114。电介质材料112可为保形结构，例如STI材料，其在第二植入区域110上方、沿着侧壁111a且在底部表面111b上方延伸。填充材料116可为填充沟槽区域的电介质材料。
在所说明的实施例中，互连通孔114延伸穿过填充电介质材料116且至少部分地穿过STI 112。互连通孔114通过穿过填充材料116和电介质材料112蚀刻孔113接着在孔113中沉积合适的导电材料(例如，钨)而形成。互连通孔114具有延伸超出第二植入区域110的前侧的前部部分115a以及至少部分地突出穿过STI 112且定位在块状硅区域108处或之中的背部部分115b。在其它实施例中，背部部分115b部分地掩埋在STI 112中，并且在FEOL处理期间并不接触块状硅区域108。例如3Dx接触件等经FEOL预定位的接触件150(“FEOL接触件150”)位于互连件114的背部部分115b的端部之上并且限定有源接触表面。
阵列组件100还可包含阵列结构120，例如存储器阵列或其它有源特征。阵列结构120可通过在FEOL处理期间嵌入于阵列组件100的材料中的一或多个电路(未示出)电耦合到互连通孔114。尽管图1A-1E中描绘阵列结构120的一种示例性配置，但阵列结构120或其它装置结构的任何合适配置也在本发明技术的范围内。
图1B示出在已去除块状硅区域108的一部分之后与图1A相比处于颠倒定向的阵列组件100。去除块状硅区域108可暴露阵列组件100的背侧处的嵌入式FEOL接触件150；然而，FEOL接触件150可在图1D中所示的步骤之前保持嵌入在硅或电介质材料下。图1C示出在已在变薄的块状硅区域108、STI电介质材料112和FEOL接触件150(如果暴露)的部分上形成额外的绝缘材料130之后的阵列组件100。图1D示出在绝缘材料130、STI电介质材料112和填充电介质材料116的一部分已经图案化和蚀刻以在沟槽区域中形成开口117之后的阵列组件，所述开口暴露FEOL接触件150和背部部分115b处的互连通孔114的一部分，使得可以进行电连接。
图1E示出导电接触特征140已在开口117(图1D)中形成于FEOL接触件150上方之后的阵列组件。可通过横过背侧沉积导电材料接着图案化且蚀刻导电材料以在开口117中形成接触特征140来形成接触特征140。接触特征140具有凹形区域141，其经配置以在其中接收可提供用于阵列组件100的背侧电连接位置的焊料材料。接触特征140可进一步通过金属接合形成电连接。尽管示出FEOL接触件的一种配置，但其它配置也在本发明技术的范围内。
图2A和2B示出图1E的阵列组件100的组件配置的实施例的放大横截面视图。图2A示出以背对背配置布置的多个阵列组件100，其中个别阵列组件100的接触特征140电连接。阵列组件100可在此配置中通过在由接触特征140的凹形区域141限定的体积内的接合线142和/或焊料连接件144处接合接触特征140而电耦合。
图2B示出其中阵列组件100以背面对面布置电耦合到3D存储器阵列200的另一配置。3D存储器阵列200具有通过互连件204电耦合到一或多个接合衬垫210的多个堆叠式存储器阵列层202。接触特征140在接合线242和/或由接触特征140的凹形区域141限定的体积中的焊料连接件244处电连接到堆叠式存储器阵列组件200的接合衬垫210。
图3A-3F示出根据本发明技术的实施例的制造包括阵列芯片组件300(“阵列组件300”)的半导体装置的各个阶段的放大横截面视图。阵列组件300与图1A-1E的阵列组件100的总体结构和配置类似，并且类似附图标记指代图3A-3F中的类似特征，但属于300系列，并且所述特征可具有变化和/或具有不同的形状和大小。
阵列组件300包含多区域硅衬底，其具有块状硅区域308、第一植入区域309和第二植入区域310，其中区域308、309和310经配置以接收阵列组件300的各种材料和部件。阵列组件300还包含由侧壁311a和底部表面311b限定的沟槽区域。侧壁311a至少延伸穿过第一植入区域309和第二植入区域310，并且在一些实施例中，侧壁311a延伸到块状硅区域308的一部分中，使得沟槽区域的底部表面311b位于块状电介质区域308内。阵列组件300进一步包含贴合侧壁311a和底部表面311b的电介质材料312，例如STI电介质312，以及沟槽区域的体积中的沟槽绝缘材料316。阵列组件300进一步包含延伸横过沟槽绝缘材料316且横过STI电介质312的至少一部分的导电互连材料314，以及FEOL阵列结构320(例如，存储器阵列)。经FEOL预定位的有源接触表面350(例如，3Dx接触表面)可定位在互连材料314的面向沟槽绝缘材料316的表面上。互连材料314可通过在FEOL过程期间形成的一或多个电路(未示出)电耦合到FEOL阵列结构320。尽管图3A-3D中描绘阵列结构320的一种示例性配置，但阵列结构或其它装置结构的任何合适配置也在本发明技术的范围内。
图3B示出与图3A相比处于颠倒定向和已去除块状硅区域308的一部分以暴露阵列组件300的背侧上的STI电介质312的至少一部分之后的阵列组件300。图3C示出在使用背侧钝化或其它合适的方法在其余的块状硅区域308和STI电介质312之上形成额外的绝缘材料330之后的阵列组件300，图3D示出在抗蚀剂材料342已施加到绝缘材料330上方并且开口343已形成于抗蚀剂材料342中之后的阵列组件300。图3E示出在穿过绝缘材料330、STI电介质312和沟槽绝缘材料316形成孔360之后的阵列组件300。孔360延伸到导电互连材料314以暴露互连材料314背侧上与抗蚀剂材料342中的开口343对准的FEOL接触表面350(图3D)。
图3F示出在已施加导电材料370来在开口360中形成互连通孔372并在互连通孔372的一个端部形成接触特征340之后的阵列组件300。互连通孔372电耦合接触特征340与FEOL接触表面350以提供用于阵列组件300的背侧电连接位置。尽管示出FEOL接触表面的一种配置，但其它配置也在本发明技术的范围内。与图2A和2B中所示的组件配置类似的组件配置以及其它面对面、背对背和背对面配置对于阵列组件300是可能的。
本文中所描述的互连件可由例如铜(Cu)的合适导电材料形成，并且可具有焊料盖以形成电连接(例如，锡-银(SnAg)焊料盖)。在组装期间，可使用联合回焊、声波回焊，或其它技术回焊所述焊料盖。接合衬垫可为铜衬底且可使用铜与铜接合或其它合适的技术来接合。
图4是说明根据本发明技术的实施例的并入有半导体装置的系统的框图。具有上文参考图1A-3F所描述的特征的半导体装置中的任一者可并入到大量更大和/或更复杂的系统中的任一者中，所述系统的代表性实例是在图4中示意性地示出的系统400。系统400可包含处理器402、存储器404(例如，SRAM、DRAM、快闪和/或其它存储器装置)、输入/输出装置406，和/或其它子系统或部件408。上文参考图1A-3F所描述的半导体组件、装置和装置封装可包含于图4中所示的元件中的任一者中。所得系统400可经配置以执行广泛多种合适的计算、处理、存储、感测、成像和/或其它功能中的任一者。因此，系统400的代表性实例包含但不限于，计算机和/或其它数据处理器，例如台式计算机、膝上型计算机、网络家电、手持式装置(例如，掌上型计算机、可穿戴式计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器的或可编程的消费型电子装置、网络计算机和微型计算机。系统400的额外代表性实例包含灯、相机、车辆等。在这些和其它实例中，系统400可容纳在单个单元中或例如通过通信网络分布在多个互连单元上。因此，系统400的部件可包含本地和/或远程存储器存储装置和广泛多种合适的计算机可读媒体中的任一者。
如在前文描述中所使用，鉴于图中所展示的定向，术语“竖直”、“横向”、“上部”和“下部”可指半导体装置中的特征的相对方向或位置。例如，“上部”或“最上”可指定位成比另一特征更接近页面顶部的特征。然而，这些术语应在广义上予以解释以包含具有例如颠倒或倾斜定向的其它定向的半导体装置，其中顶部/底部、上方/下方、高于/低于、向上/向下、左/右以及远侧/近侧可取决于定向而互换。此外，为了易于参考，贯穿本公开，相同附图标记用于标识类似或相似部件或特征，但使用相同附图标记并不暗示特征应理解为相同的。实际上，在本文中所描述的许多实例中，相同编号的特征具有在结构和/或功能上彼此不同的多个实施例。此外，除非本文中具体地标注，否则相同着色可用以指示横截面中的可在成分上类似的材料，但使用相同着色并不暗示材料应理解为相同的。
前述公开内容还可参考数量和数目。除非特别说明，否则不应将这些数量及数目视为限制性的，而应作为与新技术相关的可能数量或数目的示例。而且，就此而言，本公开可使用术语“多个”指代数量或数目。就此而言，术语“多个”表示大于一，例如，二、三、四、五等的任何数目。出于本公开的目的，短语“A、B和C中的至少一个”例如意指(A)、(B)、(C)、(A及B)、(A及C)、(B及C)，或(A、B及C)，包含列出多于三个元素时的所有进一步可能的排列。
从前文应了解，本文中已出于说明的目的描述了新技术的具体实施例，但可在不偏离本公开的情况下进行各种修改。因此，本发明不受所附权利要求书之外的限制。此外，在特定实施例的上下文中描述的新技术的某些方面还可在其它实施例中组合或去除。此外，尽管已经在那些实施例的上下文中描述了与新技术的某些实施例相关联的优点，但其它实施例也可显示此类优点，且并非所有的实施例都要显示此类优点以落入本公开的范围内。因此，本公开和相关联的技术可涵盖未明确地在本文中示出或描述的其它实施例。

Claims (20)

1.一种半导体装置，其包括：
包括硅的衬底材料，所述衬底材料具有前侧、背侧和所述前侧处的沟槽；
所述衬底材料的所述前侧处的位于所述沟槽的任一侧之上的有源电部件；
位于所述衬底材料的所述前侧的至少一部分上方且位于所述沟槽中的保形电介质材料；
位于所述沟槽中的所述保形电介质材料之上的填充电介质材料；
延伸穿过所述填充电介质材料和所述保形电介质材料的至少一部分的导电FEOL互连通孔，所述互连通孔具有限定延伸超出所述衬底材料的所述前侧的前侧电连接件的前侧部分和限定有源接触表面的背侧部分。
2.根据权利要求1所述的半导体装置，其进一步包括电耦合到所述有源接触表面以用于在所述半导体装置的所述背侧处进行电连接的接触特征。
3.根据权利要求2所述的半导体装置，其中所述接触特征具有经配置以在其中接收焊料材料的凹形区域。
4.根据权利要求2所述的半导体装置，其进一步包括限定存储器阵列的阵列层，其中所述存储器阵列通过所述互连通孔电耦合到所述接触特征。
5.根据权利要求2所述的半导体装置，其中：
所述半导体装置为通过所述接触特征电耦合到第二半导体装置的第一半导体装置；并且
所述第二半导体装置为阵列芯片组件或CMOS芯片组件。
6.一种半导体装置，其包括：
包括硅的衬底材料，所述衬底材料具有前侧、背侧和所述前侧处的沟槽；
所述衬底材料的所述前侧处的位于所述沟槽的任一侧之上的有源电部件；
位于所述衬底材料的所述前侧的至少一部分上方且位于所述沟槽中的保形电介质材料；
位于所述沟槽中的所述保形电介质材料之上的填充电介质材料；以及
延伸横过所述保形电介质材料的至少一部分和所述填充电介质材料的导电材料，所述导电材料具有限定有源接触表面的背侧表面。
7.根据权利要求6所述的半导体装置，其进一步包括：
穿过所述保形电介质材料和所述填充电介质材料的孔；以及
延伸穿过所述孔且电耦合到所述有源接触表面的导电互连通孔。
8.根据权利要求7所述的半导体装置，其进一步包括电耦合到所述互连通孔和所述有源接触表面以用于在所述半导体装置的所述背侧处进行电连接的接触特征。
9.根据权利要求8所述的半导体装置，其进一步包括限定存储器阵列的阵列层，其中所述存储器阵列通过所述互连通孔和所述导电材料电耦合到所述接触特征。
10.根据权利要求8所述的半导体装置，其中：
所述半导体装置为通过所述接触特征电耦合到第二半导体装置的第一半导体装置；并且
所述第二半导体装置为阵列芯片组件或CMOS芯片组件。
11.一种用于在半导体装置的背侧上形成电连接件的方法，所述方法包括：
在所述半导体装置的前段工艺处理期间形成一
衬底材料的所述前侧处的沟槽；
所述衬底材料的所述前侧处的位于所述沟槽的任一侧之上的有源电部件；
位于所述衬底材料的所述前侧的至少一部分上方且位于所述沟槽中的保形电介质材料；
位于所述沟槽中的所述保形电介质材料之上的填充电介质材料；以及
延伸横过所述保形电介质材料的至少一部分和所述填充电介质材料的导电材料。
12.根据权利要求11所述的方法，其中所述导电材料进一步包括延伸穿过所述填充电介质材料和所述保形电介质材料的至少一部分的互连通孔，所述互连通孔在所述互连通孔的背侧部分处具有有源接触表面。
13.根据权利要求12所述的方法，其进一步包括在前段工艺处理之后：
去除所述衬底材料的至少一部分；以及
形成电耦合到所述互连通孔的所述有源接触表面的接触特征，以用于在所述半导体装置的所述背侧处形成所述电连接件。
14.根据权利要求13所述的方法，其中在形成所述接触特征之前去除所述保形电介质材料的一部分。
15.根据权利要求13所述的方法，其进一步包括形成穿过所述接触特征到达阵列芯片组件或CMOS芯片组件的电连接件。
16.根据权利要求11所述的方法，其进一步包括在前段工艺处理之后：
去除所述衬底材料的至少一部分；以及
形成穿过所述保形电介质材料和所述填充电介质材料的孔以从所述半导体装置的所述背侧暴露所述导电材料的有源接触表面。
17.根据权利要求16所述的方法，其进一步包括用导电材料填充所述孔以形成电耦合到所述有源接触表面的互连通孔。
18.根据权利要求17所述的方法，其进一步包括形成电耦合到所述互连通孔的接触特征，以用于在所述半导体装置的所述背侧处形成所述电连接件。
19.根据权利要求18所述的方法，其进一步包括形成穿过所述接触特征到达阵列芯片组件或CMOS芯片组件的电连接件。
20.根据权利要求16所述的方法，其进一步包括在去除所述衬底材料的至少一部分之后在所述保形电介质材料上形成无源绝缘材料。
CN202180052883.9A 2020-08-28 2021-08-18 前段工艺互连结构以及相关联系统和方法 Pending CN116075927A (zh)

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