CN101714532B - 封装件及其制造方法 - Google Patents
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Abstract
一种封装件及其制造方法。封装件包括一导电层、一芯片、数个第一焊垫、数条焊线及一封胶。导电层具有一芯片承座且包括数条走线。每一走线的路径实质上平行于芯片承座的一承座面,每一走线具有一走线上表面及一走线下表面。芯片设置于承座面上且具有数个接垫。第一焊垫对应地形成于走线上表面。焊线电性连接接垫与第一焊垫。封胶包覆导电层、第一焊垫、芯片及焊线,并裸露导电层的下表面,而导电层突出于封胶的底面。
Description
技术领域
本发明是有关于一种封装件及其制造方法,且特别是有关于一种裸露出芯片承座的封装件及其制造方法。
背景技术
现今的电子产品功能愈来愈强大,相对的用电量也增加。用电量一增加,电子产品内的电子组件的负荷也就愈重,也因此造成更多热量的产生。因此,电子组件的散热性也愈来愈受重视。
电子组件,例如是封装件,多是把芯片完全地包覆在封胶内。这样的封装方式不用质疑地对散热是一大障碍。虽然,有些封装件以加装散热片的方式来增加散热量,但是封装件的散热能力是永远不会被满足的。因此,如何提升封装件的散热性是产业发展的重点之一。
发明内容
本发明是有关于一种封装件及其制造方法,经由芯片承座突出于封胶的底面的方式,增加芯片承座与封装件的外部的接触面积。因此,提升了封装件的散热性。
根据本发明的一方面,提出一种封装件。封装件包括一导电层、一芯片、数个第一焊垫、数条焊线及一封胶。导电层具有一芯片承座(Die Pad)且包括数条走线。每一走线的路径实质上平行于芯片承座的一承座面,每一走线具有一走线上表面及一走线下表面。芯片设置于承座面上,芯片具有数个接垫。第一焊垫对应地形成于走线上表面。焊线电性连接接垫与第一焊垫。封胶包覆导电层、第一焊垫、芯片及焊线,并裸露导电层的下表面。其中,导电层突出于封胶的底面。
根据本发明的另一方面,提出一种封装件的制造方法。制造方法包括以下步骤。提供一载体(carrier)。形成一线路图案层于载体的一载体上表面。形成一导电层于载体上表面,导电层与线路图案层互补,导电层具有一芯片承座且包括数条走线,每一走线的路径实质上平行于芯片承座的一承座面,每一走线具有一走线上表面及一走线下表面。对应地形成数个第一焊垫于走线上表面。设置一芯片于承座面上,芯片具有数个接垫。以数条焊线电性连接接垫与第一焊垫。以一封胶包覆导电层、第一焊垫、芯片及焊线。移除载体与线路图案层,以裸露出导电层的下表面,而导电层突出于封胶的底面。
为让本发明的上述内容能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下:
附图说明
图1绘示依照本发明第一实施例的封装件的制造方法的流程图。
图2绘示第一实施例的载体的剖切图。
图3A绘示第一实施例形成有线路图案层的载体的剖切图。
图3B绘示图3A的形成有线路图案层的载体的俯视图。
图4A至4C绘示图3A的线路图案层的形成示意图。
图5绘示第一实施例形成有有机薄膜的载体的剖切图。
图6绘示第一实施例形成有第二焊垫的载体的剖切图。
图7绘示第一实施例形成有导电层的载体的剖切图。
图8绘示第一实施例形成有第一焊垫的载体的剖切图。
图9绘示第一实施例形成有第一绝缘层的载体的剖切图。
图10绘示第一实施例形成有芯片的载体的剖切图。
图11绘示第一实施例形成有焊线的载体的剖切图。
图12绘示第一实施例形成有封胶的载体的剖切图。
图13绘示图12的载体及线路图案层被移除后的剖切图。
图14绘示第一实施例形成有第二绝缘层的载体的剖切图。
图15绘示图14的封装件252的底视图。
图16绘示依照本发明第二实施例的封装件的制造方法的流程图。
图17A至17I绘示图16的各步骤示意图。
主要组件符号说明
202:载体
204:线路图案层
206:载体上表面
208、308:导电层
210、310:芯片承座
212、312:走线
214、314:承座面
216、316:走线上表面
218、318:走线下表面
220、320:第一焊垫
222、322:芯片
224、324:接垫
226、326:焊线
228、328:封胶
230、330:导电层的下表面
232、332:封胶的底面
234:有机薄膜
236、244、336、344:镍层
238、242、338、342:金层
240、340:第二焊垫
246:光阻层
248、348:第一绝缘层
250、350:第二绝缘层
252、352:封装件
254:封装件的四边
256:空间
具体实施方式
以下是提出较佳实施例作为本发明的说明,然而实施例所提出的内容,仅为举例说明之用,而绘制的图式为配合说明,并非作为限缩本发明保护范围之用。再者,实施例的图标亦省略不必要的组件,以利清楚显示本发明的技术特点。
第一实施例
请参照图1,其绘示依照本发明第一实施例的封装件的制造方法的流程图。制造方法包括以下步骤。
于步骤S102中,请同时参照图2,其绘示第一实施例的载体的剖切图。提供一载体(carrier)202。载体202的材质为一金属,例如是铜金属。
接着,于步骤S104中,请同时参照图3A及图3B,图3A绘示第一实施例形成有线路图案层的载体的剖切图,图3B绘示图3A的形成有线路图案层的载体的俯视图。如图3A及图3B所示,形成一线路图案层204于载体202的一载体上表面206。其中,线路图案层204露出数个空间256。线路图案层204的材质为金属,例如是铜金属。
此外,请同时参照图4A至4C,其绘示图3A的线路图案层的形成示意图。线路图案层204的形成步骤如下。如图4A所示,于步骤S104后,形成一光阻层246于载体上表面206。
然后,如图4B所示,图案化光阻层246。
然后,如图4C所示,形成线路图案层204于载体上表面206。在移除光阻层246后就完成如图3A所示的线路图案层204。
此外,于步骤S104之后,请同时参照图5,其绘示第一实施例形成有有机薄膜的载体的剖切图。制造方法可更包括形成一有机薄膜(organic film)234于载体202上及线路图案层204上的步骤。有机薄膜234具有黏合性,可以黏住载体202及线路图案层204。有机薄膜234的形成方式可应用化学处理的方式完成。
然后,于步骤S106中,请同时参照图6,其绘示第一实施例形成有第二焊垫的载体的剖切图。对应地形成数个第二焊垫240于载体202上,第二焊垫240包括一金层242及一镍层244。进一步地说,形成第二焊垫240的步骤为两步骤所完成,即于步骤S104之后,形成金层242于载体202上。然后,再形成镍层244于金层242上。
然后,于步骤S108中,请同时参照图7,其绘示第一实施例形成有导电层的载体的剖切图。形成一导电层208于载体上表面206上的有机薄膜234。导电层208与线路图案层204互补,也就是说,导电层208将图3A的该些空间256填满。此外,导电层208具有一芯片承座210且包括数条走线212,每一走线212具有一走线上表面216及一走线下表面218。
然后,于步骤S110中,请同时参照图8,其绘示第一实施例形成有第一焊垫的载体的剖切图。对应地形成数个第一焊垫220于走线上表面216。第一焊垫220包括一镍层236及一金层238。也就是说,第一焊垫220的形成步骤为两步骤所完成,即,于步骤S108之后,形成镍层236于走线212上。然后,再形成金层238于镍层236上。
然后,于步骤S112中,请同时参照图9,其绘示第一实施例形成有第一绝缘层的载体的剖切图。形成一第一绝缘层248于走线上表面216(走线上表面216绘示于图7),第一绝缘层248裸露出第一焊垫220。第一绝缘层248的形成方法例如是以化学浸泡(dipping)的方式完成。
然后,于步骤S114中,请同时参照图10,其绘示第一实施例形成有芯片的载体的剖切图。设置一芯片222于承座面214上。芯片222具有数个接垫224。
然后,于步骤S116中,请同时参照图11,其绘示第一实施例形成有焊线的载体的剖切图。以数条焊线226电性连接接垫224与第一焊垫220。
然后,于步骤S118中,请同时参照图12,其绘示第一实施例形成有封胶的载体的示意图。以一封胶228包覆导电层208、第一焊垫220、芯片222及焊线226。
然后,于步骤S120中,请同时参照图13,其绘示图12的载体及线路图案层被移除后的剖切图。移除载体202、线路图案层204及有机薄膜234,以裸露出导电层208的下表面230。也就是说,当载体202与线路图案层204移除后,芯片承座210的下表面及走线212的下表面被裸露出来。而移除载体202与线路图案层204的方式例如是采用一剥离(peel off)方式完成。由于有机薄膜234黏住载体202及线路图案层204,所以只需要轻微的力量就能以剥离的方式,例如是用手撕除有机薄膜234的方式,同时移除有机薄膜234、载体202及线路图案层204。
由于导电层208与线路图案层204呈互补(如图7所示),所以在移除线路图案层204后,芯片承座210的下表面及走线212的下表面除了被裸露出来外,更突出于封胶228的底面232,如图13所示。由于导电层208(即芯片承座210及走线212)突出于封胶228的底面232,故增加了导电层208与封装件252的外部的接触面积。如此,芯片222所产生的热量可以经由芯片承座210快速地传导至外部,以提升封装件252的散热性。
此外,于步骤S122中,请参照图14,其绘示第一实施例形成有第二绝缘层的载体的剖切图。形成一第二绝缘层250于走线下表面218,第二绝缘层250裸露出第二焊垫240。同样地,第二绝缘层250的形成方法例如是以化学浸泡完成。至此,完成依照本发明第一实施例的封装件252。
此外,请参照图15,其绘示图14的封装件252的底视图。走线212的路径实质上平行于芯片承座210的承座面214(承座面214绘示于图7)。也就是说,第一实施例的第二焊垫240位于走线212的一端,该端沿着承座面214延伸至邻近于封装件252的四边254。封装件252可经由延伸至四边254的第二焊垫240与外部组件,例如是电路板(未绘示)进行电性连接。
第二实施例
请参照图16及图17A至17I,图16绘示依照本发明第二实施例的封装件的制造方法的流程图,图17A至17I绘示图16的各步骤示意图。第二实施例中与第一实施例相同之处沿用相同标号,在此不再赘述。第二实施例与第一实施例不同之处在第二绝缘层的形成步骤S402可接续于步骤S104之后。
进一步地说,于步骤S102、步骤S104及形成有机薄膜234的动作完成之后,进入步骤S402,请同时参照图17A,其绘示第二实施例形成有第二绝缘层的载体剖切图。形成第二绝缘层350于载体202的载体202上。
然后,于步骤S106,请同时参照图17B,其绘示第二实施例形成有第二焊垫的载体的示意图。对应地形成数个第二焊垫340于载体202上。同样地,第二焊垫340也包括一金层342及一镍层344。也就是说,第二焊垫340的形成步骤为两步骤所完成,于步骤S402之后,形成金层342于载体202上。然后,再形成镍层344于金层342上。
然后,于步骤S108,请同时参照图17C,其绘示第二实施例形成有导电层的载体的示意图。形成导电层308于载体202上。导电层308与线路图案层204互补。导电层308具有一芯片承座310且包括数条走线312,每一走线312具有一走线上表面316及一走线下表面318。
然后,于步骤S110中,请同时参照图17D,其绘示第二实施例形成有第一焊垫的载体的示意图。对应地形成数个第一焊垫320于走线上表面316。第一焊垫320包括一镍层336及一金层338。也就是说,第一焊垫320的形成步骤为两步骤所完成,于步骤S108之后,形成镍层336于走线312上。然后,再形成金层338于镍层336上。
然后,于步骤S112中,请同时参照图17E,其绘示第二实施例形成有第一绝缘层的载体的示意图。形成一第一绝缘层348于走线上表面316,第一绝缘层348裸露出第一焊垫320。
然后,于步骤S114中,请同时参照图17F,其绘示第二实施例形成有芯片的载体的示意图。设置芯片322于承座面314上。
然后,于步骤S 116中,请同时参照图17G,其绘示第二实施例形成有焊线的载体的示意图。以焊线326电性连接接垫324与第一焊垫320。
然后,于步骤S118中,请同时参照图17H,其绘示第一实施例形成有封胶的载体的示意图。以一封胶328包覆导电层308、第一焊垫320、芯片322及焊线326。
然后,于步骤S120中,请同时参照图17I,其绘示图17H的载体及线路图案层被移除后的示意图。移除载体202与线路图案层204,以裸露出导电层308的下表面330。至此,完成依照本发明第二实施例的封装件352。
如图17I所示,导电层308突出于封胶328的底面332,使得导电层308与封装件352的外部的接触面积增加。所以,芯片322所产生的热量可以快速地传导至外部,提升了封装件352的散热性。
本发明上述实施例所揭露的封装件及其制造方法,导电层突出于封胶的底面,增加了导电层与封装件的外部的接触面积。因此,芯片所产生的热量可以经由芯片承座快速地传导至外部,提升封装件的散热性。
综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视后附的权利要求书所界定者为准。
Claims (13)
1.一种封装件,包括:
一导电层,具有一芯片承座且包括数条走线,所述走线的路径平行于该芯片承座的上表面,所述走线具有一走线上表面及一走线下表面;
一芯片,设置于该承座的上表面上,该芯片具有数个接垫;
数个第一焊垫,对应地形成于该些走线上表面;
数条焊线,电性连接该些接垫与该些第一焊垫;以及
一封胶,包覆该导电层、该些第一焊垫、该芯片及该些焊线,并裸露该导电层的下表面;
其中,该导电层突出于该封胶的底面。
2.如权利要求1所述的封装件,更包括:
一第一绝缘层,形成于该些走线上表面,该第一绝缘层裸露出该些第一焊垫。
3.如权利要求1所述的封装件,更包括:
数个第二焊垫,对应地形成于该些走线下表面。
4.如权利要求3所述的封装件,更包括:
一第二绝缘层,形成于该些走线下表面,该第二绝缘层裸露出该些第二焊垫。
5.一种封装件的制造方法,包括:
提供一载体;
形成一线路图案层于该载体的一载体上表面;
形成一导电层于该载体上,该导电层与该线路图案层互补,该导电层具有一芯片承座且包括数条走线,所述走线的路径平行于该芯片承座的一承座的上表面,所述走线具有一走线上表面及一走线下表面;
对应地形成数个第一焊垫于该些走线上表面;
设置一芯片于该承座的上表面上,该芯片具有数个接垫;
以数条焊线电性连接该些接垫与该些第一焊垫;
以一封胶包覆该导电层、该些第一焊垫、该芯片及该些焊线;以及
移除该载体与该线路图案层,以裸露出导电层的下表面,该导电层突出于该封胶的底面。
6.如权利要求5所述的制造方法,其中于形成该线路图案层的该步骤与形成该导电层的该步骤之间,该制造方法更包括:
形成一有机薄膜于该载体上及该线路图案层上。
7.如权利要求5所述的制造方法,其中形成该些第一焊垫的该步骤包括:
形成一镍层于该些走线上;以及
形成一金层于该镍层上。
8.如权利要求5所述的制造方法,更包括:
对应地形成数个第二焊垫于该载体上。
9.如权利要求8所述的制造方法,其中形成该些第二焊垫的该步骤包括:
形成一金层于该载体上;以及
形成一镍层于该金层上。
10.如权利要求8所述的制造方法,其中于移除该载体的该步骤后,该制造方法更包括:
形成一第二绝缘层于该些走线下表面,该第二绝缘层裸露出该些第二焊垫。
11.如权利要求5所述的制造方法,其中于形成该线路图案层的该步骤及形成该导电层的该步骤之间,该制造方法更包括:
形成一第二绝缘层于该载体上。
12.如权利要求5所述的制造方法,其中于形成该导电层的该步骤后,该制造方法更包括:
形成一第一绝缘层于该些走线上表面,该第一绝缘层裸露出该些第一焊垫。
13.如权利要求5所述的制造方法,其中于移除该载体与该线路图案层的该步骤采用一剥离方式完成。
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