CN1319138C - 封装的半导体器件的形成方法 - Google Patents
封装的半导体器件的形成方法 Download PDFInfo
- Publication number
- CN1319138C CN1319138C CNB031023126A CN03102312A CN1319138C CN 1319138 C CN1319138 C CN 1319138C CN B031023126 A CNB031023126 A CN B031023126A CN 03102312 A CN03102312 A CN 03102312A CN 1319138 C CN1319138 C CN 1319138C
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- radiator
- circuit
- circuit wafer
- semiconductor device
- wafer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/072,167 | 2002-02-07 | ||
US10/072,167 US6858932B2 (en) | 2002-02-07 | 2002-02-07 | Packaged semiconductor device and method of formation |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006101075528A Division CN101150098B (zh) | 2002-02-07 | 2003-01-30 | 半导体器件 |
Publications (2)
Publication Number | Publication Date |
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CN1437233A CN1437233A (zh) | 2003-08-20 |
CN1319138C true CN1319138C (zh) | 2007-05-30 |
Family
ID=27610553
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031023126A Expired - Lifetime CN1319138C (zh) | 2002-02-07 | 2003-01-30 | 封装的半导体器件的形成方法 |
CN2006101075528A Expired - Lifetime CN101150098B (zh) | 2002-02-07 | 2003-01-30 | 半导体器件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006101075528A Expired - Lifetime CN101150098B (zh) | 2002-02-07 | 2003-01-30 | 半导体器件 |
Country Status (5)
Country | Link |
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US (1) | US6858932B2 (zh) |
EP (1) | EP1335426A3 (zh) |
JP (1) | JP4653383B2 (zh) |
KR (1) | KR100995478B1 (zh) |
CN (2) | CN1319138C (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6853070B2 (en) * | 2001-02-15 | 2005-02-08 | Broadcom Corporation | Die-down ball grid array package with die-attached heat spreader and method for making the same |
US6794748B1 (en) * | 2003-04-22 | 2004-09-21 | Intel Corporation | Substrate-less microelectronic package |
US7190068B2 (en) * | 2004-06-25 | 2007-03-13 | Intel Corporation | Bottom heat spreader |
US7071556B2 (en) * | 2004-09-10 | 2006-07-04 | Jinghui Mu | Tape ball grid array package with electromagnetic interference protection and method for fabricating the package |
US7786591B2 (en) * | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
KR100700936B1 (ko) * | 2006-01-25 | 2007-03-28 | 삼성전자주식회사 | 냉각 장치 및 이를 갖는 메모리 모듈 |
US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
US20090039524A1 (en) * | 2007-08-08 | 2009-02-12 | Texas Instruments Incorporated | Methods and apparatus to support an overhanging region of a stacked die |
US8472190B2 (en) * | 2010-09-24 | 2013-06-25 | Ati Technologies Ulc | Stacked semiconductor chip device with thermal management |
TWI446495B (zh) * | 2011-01-19 | 2014-07-21 | Subtron Technology Co Ltd | 封裝載板及其製作方法 |
US9070657B2 (en) | 2013-10-08 | 2015-06-30 | Freescale Semiconductor, Inc. | Heat conductive substrate for integrated circuit package |
KR20170001238A (ko) * | 2015-06-26 | 2017-01-04 | 에스케이하이닉스 주식회사 | 계단형 기판을 포함하는 반도체 패키지 |
US10741534B2 (en) * | 2018-09-28 | 2020-08-11 | Intel Corporation | Multi-die microelectronic device with integral heat spreader |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1187037A (zh) * | 1996-12-30 | 1998-07-08 | Lg半导体株式会社 | 半导体封装及其制造方法 |
CN1202983A (zh) * | 1995-11-28 | 1998-12-23 | 株式会社日立制作所 | 半导体器件及其制造方法以及装配基板 |
TW429494B (en) * | 1999-11-08 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Quad flat non-leaded package |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61232651A (ja) * | 1985-04-09 | 1986-10-16 | Seiko Epson Corp | 半導体実装方法 |
JP2660732B2 (ja) * | 1989-01-09 | 1997-10-08 | 株式会社日立製作所 | 半導体装置 |
JPH0458539A (ja) * | 1990-06-27 | 1992-02-25 | Mitsubishi Electric Corp | 混成集積回路装置 |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5468994A (en) | 1992-12-10 | 1995-11-21 | Hewlett-Packard Company | High pin count package for semiconductor device |
JP2591499B2 (ja) * | 1994-10-21 | 1997-03-19 | 日本電気株式会社 | 半導体装置 |
JP2636777B2 (ja) | 1995-02-14 | 1997-07-30 | 日本電気株式会社 | マイクロプロセッサ用半導体モジュール |
TW373308B (en) * | 1995-02-24 | 1999-11-01 | Agere Systems Inc | Thin packaging of multi-chip modules with enhanced thermal/power management |
JPH0917919A (ja) | 1995-06-29 | 1997-01-17 | Fujitsu Ltd | 半導体装置 |
US5844168A (en) | 1995-08-01 | 1998-12-01 | Minnesota Mining And Manufacturing Company | Multi-layer interconnect sutructure for ball grid arrays |
JPH0992748A (ja) * | 1995-09-21 | 1997-04-04 | Mitsubishi Materials Corp | 半導体素子用パッケージ |
US5843808A (en) | 1996-01-11 | 1998-12-01 | Asat, Limited | Structure and method for automated assembly of a tab grid array package |
US5696031A (en) | 1996-11-20 | 1997-12-09 | Micron Technology, Inc. | Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
US5919329A (en) | 1997-10-14 | 1999-07-06 | Gore Enterprise Holdings, Inc. | Method for assembling an integrated circuit chip package having at least one semiconductor device |
JPH11219984A (ja) | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JP3610769B2 (ja) * | 1998-03-25 | 2005-01-19 | イビデン株式会社 | 多層電子部品搭載用基板 |
JP2000077563A (ja) * | 1998-08-31 | 2000-03-14 | Sharp Corp | 半導体装置およびその製造方法 |
JP2000174180A (ja) * | 1998-12-02 | 2000-06-23 | Shibafu Engineering Kk | 半導体装置 |
JP3512657B2 (ja) | 1998-12-22 | 2004-03-31 | シャープ株式会社 | 半導体装置 |
JP3344362B2 (ja) * | 1999-05-07 | 2002-11-11 | 日本電気株式会社 | フィルムキャリア型半導体装置 |
JP2000332160A (ja) * | 1999-05-24 | 2000-11-30 | Sumitomo Metal Electronics Devices Inc | キャビティダウン型半導体パッケージ |
JP3589109B2 (ja) * | 1999-08-27 | 2004-11-17 | 日立電線株式会社 | スティフナ付きtabテープおよびbgaパッケージ |
US6184580B1 (en) * | 1999-09-10 | 2001-02-06 | Siliconware Precision Industries Co., Ltd. | Ball grid array package with conductive leads |
JP4253992B2 (ja) | 2000-03-16 | 2009-04-15 | 株式会社デンソー | 樹脂封止型半導体装置 |
JP2001267476A (ja) * | 2000-03-17 | 2001-09-28 | Aronshiya:Kk | 半導体パッケージ用ヒートスプレッダの製造方法 |
TW466723B (en) * | 2000-12-01 | 2001-12-01 | Siliconware Precision Industries Co Ltd | Super thin package having high heat-dissipation property |
-
2002
- 2002-02-07 US US10/072,167 patent/US6858932B2/en not_active Expired - Lifetime
-
2003
- 2003-01-30 CN CNB031023126A patent/CN1319138C/zh not_active Expired - Lifetime
- 2003-01-30 CN CN2006101075528A patent/CN101150098B/zh not_active Expired - Lifetime
- 2003-02-04 EP EP03002380A patent/EP1335426A3/en not_active Withdrawn
- 2003-02-06 KR KR1020030007424A patent/KR100995478B1/ko not_active IP Right Cessation
- 2003-02-07 JP JP2003030887A patent/JP4653383B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1202983A (zh) * | 1995-11-28 | 1998-12-23 | 株式会社日立制作所 | 半导体器件及其制造方法以及装配基板 |
CN1187037A (zh) * | 1996-12-30 | 1998-07-08 | Lg半导体株式会社 | 半导体封装及其制造方法 |
TW429494B (en) * | 1999-11-08 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Quad flat non-leaded package |
Also Published As
Publication number | Publication date |
---|---|
CN101150098B (zh) | 2011-11-23 |
EP1335426A3 (en) | 2008-07-30 |
CN1437233A (zh) | 2003-08-20 |
KR100995478B1 (ko) | 2010-11-22 |
EP1335426A2 (en) | 2003-08-13 |
JP2003243565A (ja) | 2003-08-29 |
JP4653383B2 (ja) | 2011-03-16 |
US20030148554A1 (en) | 2003-08-07 |
US6858932B2 (en) | 2005-02-22 |
CN101150098A (zh) | 2008-03-26 |
KR20030067542A (ko) | 2003-08-14 |
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