JP2007295592A - レジスタ制御ディレイロックループを備えた半導体デバイス - Google Patents
レジスタ制御ディレイロックループを備えた半導体デバイス Download PDFInfo
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- JP2007295592A JP2007295592A JP2007134665A JP2007134665A JP2007295592A JP 2007295592 A JP2007295592 A JP 2007295592A JP 2007134665 A JP2007134665 A JP 2007134665A JP 2007134665 A JP2007134665 A JP 2007134665A JP 2007295592 A JP2007295592 A JP 2007295592A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
- H03K2005/00104—Avoiding variations of delay using feedback, e.g. controlled by a PLL using a reference signal, e.g. a reference clock
Abstract
【解決手段】レジスタ制御ディレイロックループ及びそこから出力されたDLLクロックを用いる内部回路を備えた半導体デバイスにおいて、半導体デバイスに対する作動信号及び非作動信号に応答して、内部回路に印加されるDLLクロックをイネーブルしたりディスエーブルしたりするクロックイネーブル信号を生成する手段を備える。その場合、クロックイネーブル信号を生成する手段は、作動信号又は非作動信号に応答してプルダウン又はプルアップ動作を行う駆動手段と、半導体デバイスに対する作動信号に応答して駆動手段の出力ノードをリセットするリセット手段と、駆動手段の出力ノードに印加された信号をラッチし、バッファリングして出力する出力手段とを備えている。
【選択図】図1
Description
Claims (4)
- レジスタ制御ディレイロックループと、そこから出力されたDLLクロックを用いる内部回路とを備えた半導体デバイスであって、
前記半導体デバイスに対する作動信号に応答して、前記内部回路に印加される前記DLLクロックをイネーブルし、前記半導体デバイスに対する非作動信号に応答して、前記内部回路に印加される前記DLLクロックをディスエーブルするためのDLLクロックイネーブル信号を生成する手段を備えてなり、
前記DLLクロックイネーブル信号を生成する手段は、
前記作動信号又は前記非作動信号に応答してプルダウン又はプルアップ動作を行う駆動手段と、
前記半導体デバイスに対する作動信号に応答して前記駆動手段の出力ノードをリセットするリセット手段と、
前記駆動手段の前記出力ノードに印加された信号をラッチし、バッファリングして出力する出力手段とを備えている
ことを特徴とする半導体デバイス。 - 請求項1に記載の半導体デバイスであって、
さらに、入力されたクロックを、前記DLLクロックイネーブル信号のイネーブル状態/ディスエーブル状態に応答してオン/オフさせるためのクロック制御手段を備えてなる
ことを特徴とする半導体デバイス。 - 請求項2に記載の半導体デバイスにおいて、
前記半導体デバイスに対する作動信号は、メモリに対する作動指令、読出し指令、列アドレスストローブ信号又は行アドレスストローブ信号である
ことを特徴とする半導体デバイス。 - 請求項1に記載の半導体デバイスにおいて、
前記半導体デバイスに対する非作動信号は、プリチャージ指令である
ことを特徴とする半導体デバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0038872A KR100422572B1 (ko) | 2001-06-30 | 2001-06-30 | 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자 |
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JP2002181633A Division JP4250379B2 (ja) | 2001-06-30 | 2002-06-21 | 半導体デバイス用レジスタ制御ディレイロックループ |
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JP2011052054A Division JP2011147165A (ja) | 2001-06-30 | 2011-03-09 | レジスタ制御ディレイロックループを備えた半導体デバイス |
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JP2007295592A true JP2007295592A (ja) | 2007-11-08 |
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JP2002181633A Expired - Fee Related JP4250379B2 (ja) | 2001-06-30 | 2002-06-21 | 半導体デバイス用レジスタ制御ディレイロックループ |
JP2007134665A Pending JP2007295592A (ja) | 2001-06-30 | 2007-05-21 | レジスタ制御ディレイロックループを備えた半導体デバイス |
JP2011052054A Pending JP2011147165A (ja) | 2001-06-30 | 2011-03-09 | レジスタ制御ディレイロックループを備えた半導体デバイス |
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JP2002181633A Expired - Fee Related JP4250379B2 (ja) | 2001-06-30 | 2002-06-21 | 半導体デバイス用レジスタ制御ディレイロックループ |
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Country Status (4)
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US (2) | US6768690B2 (ja) |
JP (3) | JP4250379B2 (ja) |
KR (1) | KR100422572B1 (ja) |
TW (1) | TW577087B (ja) |
Cited By (1)
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---|---|---|---|---|
US7808290B2 (en) | 2008-08-08 | 2010-10-05 | Hynix Semiconductor Inc. | Semiconductor integrated circuit and method of controlling the same |
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Also Published As
Publication number | Publication date |
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TW577087B (en) | 2004-02-21 |
KR20030002131A (ko) | 2003-01-08 |
KR100422572B1 (ko) | 2004-03-12 |
US20030002357A1 (en) | 2003-01-02 |
JP4250379B2 (ja) | 2009-04-08 |
US6914798B2 (en) | 2005-07-05 |
US6768690B2 (en) | 2004-07-27 |
US20040233700A1 (en) | 2004-11-25 |
JP2003132680A (ja) | 2003-05-09 |
JP2011147165A (ja) | 2011-07-28 |
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