JP6179206B2 - メモリ制御装置 - Google Patents
メモリ制御装置 Download PDFInfo
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- JP6179206B2 JP6179206B2 JP2013122353A JP2013122353A JP6179206B2 JP 6179206 B2 JP6179206 B2 JP 6179206B2 JP 2013122353 A JP2013122353 A JP 2013122353A JP 2013122353 A JP2013122353 A JP 2013122353A JP 6179206 B2 JP6179206 B2 JP 6179206B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Memory System (AREA)
Description
先ず、DLL(Delay Locked Loop)を用いた遅延値の制御について説明する。DLLを使えば、基準クロックを入力することにより、クロック周期の期間に相当する遅延素子の段数を出力したり、DLL自体が基準クロックに対し固定位相差を持つ遅延回路として利用したりすることができる。例えば、上記技術を使って初期化時に、ある端子に基準クロックの1/4位相差相当の遅延値を設定したい場合、下記式(1)より求められる端子遅延設定値B0を、前記端子に接続されている遅延回路に設定すれば良い。
ここで、A0はDLLの出力値である。
ここで、A1はDLLの出力値である。
すなわち、
・DQSの遅延設定値=Nで、クロックエッジがDQSエッジより速い.
・DQSの遅延設定値=N+1で、DQSエッジがクロックエッジより速い.
この条件の場合、DQSの遅延設定値は、NまたはN+1で良い。
ここで、A0:初期化時のDLL出力値
B0:初期化時の端子遅延設定値
A1:現在のDLL出力値
B1:補正後の端子遅延設定値
である。
図2は、実施例2によるメモリ制御装置の要部構成を示したブロック図である。本実施例のメモリ制御装置30では、メモリ制御ブロック11とタイミング発生回路15とが接続され、メモリ制御ブロック11からタイミング発生回路15にリフレッシュフラグに関する信号が入力される。そして、タイミング発生回路15は、前記信号に基づいてメモリ22のリフレッシュサイクルに同期した(つまり、リフレッシュ毎に)タイミング信号を、遅延演算回路17に出力するよう構成されている。他の構成は、実施例1の場合と同様である。
図3は、実施例3の要部構成を示したブロック図である。本実施例では、タイミング発生回路15に温度センサ35が接続され、この温度センサ35での検出温度の信号がタイミング発生回路15に入力されるよう構成されている。他の構成は実施例1の場合と同様である。
図4は、実施例4によるメモリ制御装置の要部構成を示したブロック図である。本実施例のメモリ制御装置40では、新たにストローブ遅延制御回路としてWL制御回路41が設けられ、このWL制御回路41は第2レジスタ19に接続されている。なお、図示してないが、WL制御回路41は、第2レジスタ19の代わりに、第2レジスタ20または21に接続されていても良い。
11 メモリ制御ブロック
12,13,14 遅延回路
15 タイミング発生回路
16 DLL(Delay Locked Loop)
17 遅延演算回路
18 第1レジスタ
19,20,21 第2レジスタ
22 メモリ
30 メモリ制御装置
35 温度センサ
40 メモリ制御装置
41 WL制御回路
Claims (3)
- メモリに接続され端子毎に出力遅延値の設定が可変可能な複数の遅延回路と、
前記遅延回路と同じ遅延特性の遅延素子を内蔵するDLL(Delay Locked Loop)と、
前記DLLのロック状態時の出力値を任意のタイミングでレジスタ値として保持する第1レジスタと、
端子毎の遅延設定値をレジスタ値として保持する複数の第2レジスタと、
前記DLLの出力値、前記第1レジスタのレジスタ値、及び前記第2レジスタのレジスタ値に基づいて遅延値を演算する遅延演算回路とを備え、
前記遅延演算回路は、前記演算結果を前記第2レジスタのレジスタ値に上書きすることを特徴とするメモリ制御装置。 - 前記メモリの少なくとも一つの端子には前記遅延回路からストローブ信号が入力され、
WL(Write Leveling)コマンドの応答値により、前記ストローブ信号の遅延設定値を(+1)または(−1)にするストローブ遅延制御回路が設けられていることを特徴とする請求項1に記載のメモリ制御装置。 - 前記遅延回路と前記第2レジスタは、同数設けられていることを特徴とする請求項1又は請求項2に記載のメモリ制御装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013122353A JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
US14/302,044 US20140362653A1 (en) | 2013-06-11 | 2014-06-11 | Memory control device and a delay controller |
US14/879,925 US9396789B2 (en) | 2013-06-11 | 2015-10-09 | Memory control device and a delay controller |
Applications Claiming Priority (1)
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JP2013122353A JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
Publications (2)
Publication Number | Publication Date |
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JP2014241003A JP2014241003A (ja) | 2014-12-25 |
JP6179206B2 true JP6179206B2 (ja) | 2017-08-16 |
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JP2013122353A Expired - Fee Related JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
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JP (1) | JP6179206B2 (ja) |
Cited By (1)
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-
2013
- 2013-06-11 JP JP2013122353A patent/JP6179206B2/ja not_active Expired - Fee Related
-
2014
- 2014-06-11 US US14/302,044 patent/US20140362653A1/en not_active Abandoned
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10930329B2 (en) | 2018-11-07 | 2021-02-23 | Samsung Electronics Co., Ltd. | Storage device adjusting a timing of a data signal and a data strobe signal |
US11158359B2 (en) | 2018-11-07 | 2021-10-26 | Samsung Electronics Co., Ltd. | Storage device adjusting a timing of a data signal and a data strobe signal |
Also Published As
Publication number | Publication date |
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US20160035408A1 (en) | 2016-02-04 |
US9396789B2 (en) | 2016-07-19 |
JP2014241003A (ja) | 2014-12-25 |
US20140362653A1 (en) | 2014-12-11 |
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