JP2005064226A5 - - Google Patents

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Publication number
JP2005064226A5
JP2005064226A5 JP2003292166A JP2003292166A JP2005064226A5 JP 2005064226 A5 JP2005064226 A5 JP 2005064226A5 JP 2003292166 A JP2003292166 A JP 2003292166A JP 2003292166 A JP2003292166 A JP 2003292166A JP 2005064226 A5 JP2005064226 A5 JP 2005064226A5
Authority
JP
Japan
Prior art keywords
wiring
dummy
wiring structure
dielectric constant
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003292166A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005064226A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2003292166A priority Critical patent/JP2005064226A/ja
Priority claimed from JP2003292166A external-priority patent/JP2005064226A/ja
Priority to US10/791,751 priority patent/US20050035457A1/en
Priority to TW093106028A priority patent/TWI315542B/zh
Priority to CN2004100485795A priority patent/CN1581475B/zh
Priority to KR1020040044127A priority patent/KR20050018585A/ko
Priority to DE102004028925A priority patent/DE102004028925A1/de
Publication of JP2005064226A publication Critical patent/JP2005064226A/ja
Priority to US11/532,603 priority patent/US7605085B2/en
Publication of JP2005064226A5 publication Critical patent/JP2005064226A5/ja
Priority to KR1020060096963A priority patent/KR100770486B1/ko
Pending legal-status Critical Current

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JP2003292166A 2003-08-12 2003-08-12 配線構造 Pending JP2005064226A (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2003292166A JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造
US10/791,751 US20050035457A1 (en) 2003-08-12 2004-03-04 Interconnecting structure with dummy vias
TW093106028A TWI315542B (en) 2003-08-12 2004-03-08 Interconnecting structure
CN2004100485795A CN1581475B (zh) 2003-08-12 2004-06-14 互连结构的制造方法
DE102004028925A DE102004028925A1 (de) 2003-08-12 2004-06-15 Zwischenverbindungsstruktur mit Pseudo-Durchkontakten
KR1020040044127A KR20050018585A (ko) 2003-08-12 2004-06-15 배선 구조
US11/532,603 US7605085B2 (en) 2003-08-12 2006-09-18 Method of manufacturing interconnecting structure with vias
KR1020060096963A KR100770486B1 (ko) 2003-08-12 2006-10-02 반도체 장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003292166A JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008324268A Division JP4850891B2 (ja) 2008-12-19 2008-12-19 配線構造の製造方法

Publications (2)

Publication Number Publication Date
JP2005064226A JP2005064226A (ja) 2005-03-10
JP2005064226A5 true JP2005064226A5 (enExample) 2006-09-21

Family

ID=34131700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003292166A Pending JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造

Country Status (6)

Country Link
US (2) US20050035457A1 (enExample)
JP (1) JP2005064226A (enExample)
KR (2) KR20050018585A (enExample)
CN (1) CN1581475B (enExample)
DE (1) DE102004028925A1 (enExample)
TW (1) TWI315542B (enExample)

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CN105378897B (zh) * 2013-08-21 2019-11-05 英特尔公司 用引导过孔来接触紧密间距的导电层的方法和结构
US9054164B1 (en) 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
KR102326120B1 (ko) * 2015-06-29 2021-11-15 삼성전자주식회사 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치
KR102382826B1 (ko) 2015-09-08 2022-04-04 삼성전자주식회사 반도체 장치의 제조 방법
KR102521554B1 (ko) * 2015-12-07 2023-04-13 삼성전자주식회사 배선 구조물, 배선 구조물 설계 방법, 및 배선 구조물 형성 방법
US20190109090A1 (en) * 2017-08-15 2019-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure lined by isolation layer
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