US20050035457A1 - Interconnecting structure with dummy vias - Google Patents

Interconnecting structure with dummy vias Download PDF

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Publication number
US20050035457A1
US20050035457A1 US10/791,751 US79175104A US2005035457A1 US 20050035457 A1 US20050035457 A1 US 20050035457A1 US 79175104 A US79175104 A US 79175104A US 2005035457 A1 US2005035457 A1 US 2005035457A1
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United States
Prior art keywords
wirings
vias
dummy
film
interconnecting structure
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Abandoned
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US10/791,751
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English (en)
Inventor
Kazuo Tomita
Keiji Hashimoto
Yasutaka Nishioka
Susumu Matsumoto
Mitsuru Sekiguchi
Akihisa Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Panasonic Corp
Original Assignee
Renesas Technology Corp
Matsushita Electric Industrial Co Ltd
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Application filed by Renesas Technology Corp, Matsushita Electric Industrial Co Ltd filed Critical Renesas Technology Corp
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., RENESAS TECHNOLOGY CORP. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUMOTO, SUSUMU, HASHIMOTO, KEIJI, IWASAKI, AKIHISA, NISHIOKA, YASUTAKA, SEKIGUCHI, MITSURU, TOMITA, KAZUO
Publication of US20050035457A1 publication Critical patent/US20050035457A1/en
Priority to US11/532,603 priority Critical patent/US7605085B2/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an interconnecting structure, and more specifically to an interconnecting structure of an electronic device represented by a semiconductor device having dummy vias.
  • FIG. 12 is a schematic top view for illustrating an interconnecting structure in a conventional semiconductor device.
  • FIG. 13 is a sectional view taken along the line F-F′ of FIG. 12 showing the interconnecting structure manufactured using a dual damascene method.
  • first dummy wirings 15 a are formed on the peripheries of the first wirings 15
  • second dummy wirings 29 a are formed on the peripheries of the second wirings 29 .
  • the source voltage is lowered to reduce power consumption. Therefore, a problem of malfunction is often caused by external noise.
  • the present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful interconnecting structure.
  • the interconnecting structure comprises first wirings formed on a substrate.
  • a low-k dielectric film is formed on the first wirings, the low-k dielectric film having dielectric constant of 3 or less.
  • Vias are formed in the low-k dielectric film and connected to the first wiring.
  • Second wirings are formed on the vias and connected to the vias.
  • Dummy vias are formed on the periphery of an isolated via of the vias.
  • FIG. 1 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a first embodiment of the present invention
  • FIGS. 2A and 2B are sectional views taken along the line A-A′ of FIG. 1 showing the interconnecting structure manufactured using a dual damascene method;
  • FIGS. 3A to 3 F are sectional process diagrams for illustrating the method for manufacturing the interconnecting structure shown in FIG. 2A ;
  • FIG. 4 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a second embodiment of the present invention
  • FIG. 5 is a sectional view taken along the line B-B′ of FIG. 4 showing the interconnecting structure manufactured using a dual damascene method
  • FIG. 6 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a sectional view taken along the line C-C′ of FIG. 6 showing the interconnecting structure manufactured using a dual damascene method
  • FIG. 8 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 9 is a sectional view taken along the line D-D′ of FIG. 8 showing the interconnecting structure manufactured using a dual damascene method
  • FIG. 10 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 11 is a sectional view taken along the line E-E′ of FIG. 10 showing the interconnecting structure manufactured using a dual damascene method;
  • FIG. 12 is a schematic top view for illustrating an interconnecting structure in a conventional semiconductor device.
  • FIG. 13 is a sectional view taken along the line F-F′ of FIG. 12 showing the interconnecting structure manufactured using a dual damascene method.
  • FIG. 1 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 2A and 2B are sectional views taken along the line A-A′ of FIG. 1 showing the interconnecting structure manufactured using a dual damascene method.
  • An HDP oxide film as an interlayer dielectric film 2 is formed on a substrate 1 .
  • the substrate 1 is, for example, a P-type silicon wafer having a resistivity of 10 ⁇ cm.
  • a p-SiC film is formed as a stopper film 11 on the HDP oxide film 2
  • a p-SiOC film is formed as a low-k dielectric film 12 on the p-SiC film 11 .
  • First wirings (M 1 ) 15 are formed in the p-SiC film 11 and the p-SiOC film 12
  • first dummy wirings (M 1 _D) 15 a are formed on the peripheries of the first wirings 15 .
  • the first dummy wirings 15 a have a dimension of, for example, 1 ⁇ m ⁇ 1 ⁇ m, and are formed in a pitch of 2 ⁇ m.
  • a p-SiC film as a stopper film 21 is formed on the p-SiOC film 12 , the first wirings 15 , and the first dummy wirings 15 a ; and the p-SiOC film as a low-k dielectric film 22 is formed on the p-SiC film 21 .
  • a cap film 23 is formed on the p-SiOC film 22 .
  • the cap film 23 is formed to prevent causing ashing damage to the low-k dielectric film 22 , and is an insulating film of a kind different from the low-k dielectric film 22 .
  • the cap film 23 may be removed finally by a CMP method as FIG. 2B shows.
  • Dual damascene wirings 28 and 29 including vias 28 connected to first wirings 15 and second wirings 29 connected to the vias 28 , are formed in the cap film 23 the p-SiOC film 22 and the p-SiC film 21 .
  • dummy vias 28 a not connected to any wirings, and second dummy wirings 29 a are formed.
  • the dummy vias 28 a have a dimension of, for example, 0.15 ⁇ m, and are formed in a pitch of 0.5 ⁇ m.
  • the second dummy wirings 29 a have a dimension of, for example, 1 ⁇ m ⁇ 1 ⁇ m, and are formed in a pitch of 2 ⁇ m.
  • FIGS. 3A to 3 F are sectional process diagrams for illustrating the method for manufacturing the interconnecting structure shown in FIG. 2A .
  • a trench (not shown) of a depth, for example, of 300 nm is formed in a substrate 1 using an STI (shallow trench isolation) method.
  • STI shallow trench isolation
  • an oxide film 2 (hereafter referred to as “HDP oxide film”) of a thickness of 1,000 nm is formed on the substrate 1 using the HDP-CVD method, and the HDP oxide film 2 is polished by 300 nm using a CMP method.
  • a p-SiC film 11 of a thickness, for example, of 50 nm is formed on the HDP oxide film 2 using a CVD method.
  • a p-SiOC film 12 of a thickness, for example, of 400 nm is formed thereon using a CVD method, and the p-SiOC film 12 is polished by 150 nm using a CMP method.
  • a chemically amplified resist pattern (hereafter referred simply to as “resist pattern”) 13 for forming first wirings and first dummy wirings is formed. Thereby, a structure as shown in FIG. 3A is obtained.
  • first wirings 15 and first dummy wirings 15 a are formed in the p-SiOC film 12 and the p-SiC film 11 using a damascene method.
  • openings 14 and 14 a are formed in the p-SiOC film 12 and the p-SiC film 11 by dry etching using the resist pattern 13 .
  • barrier metals for example, Ta/TaN films of each thickness of 10 nm/10 nm are formed, and a Cu seed layer of a thickness of, for example, 100 nm is deposited on the barrier metal using sputtering, and Cu of a thickness of 500 nm is deposited using plating. Thereafter, unnecessary Cu and barrier metal is removed using a CMP method.
  • a p-SiC film 21 of a thickness, for example, of 50 nm is formed using a CVD method
  • a p-SiOC film 22 of a thickness, for example, of 600 nm is formed thereon using a CVD method
  • the p-SiOC film 22 is polished by 200 nm using a CMP method.
  • a cap film 23 of a thickness, for example, of 50 nm to 200 nm is formed on the p-SiOC film 22 using a CVD method.
  • a resist pattern 24 for forming vias/dummy vias is formed on the cap film 23 .
  • a via hole (connecting hole) 25 reaching the surface of the stopper film 21 is formed in the cap film 23 and the p-SiOC film 22 by dry etching using the resist pattern 24 as a mask, and dummy via holes 25 a are formed on the periphery of an isolated via hole 25 .
  • the stopper film 21 is subjected to dry etching to extend the via hole 25 and connect the via hole 25 to the first wiring 15 .
  • a resist pattern 26 is formed on the cap film 23 including the inside of the dummy via holes 25 a . Thereby, resist vias, which are dummy via holes 25 a filled with the resist are formed.
  • openings (trenches for wirings) 27 and 27 a are formed in the cap film 23 and the p-SiOC film 22 by dry etching using the resist pattern 26 as a mask.
  • dual damascene wirings 28 and 29 including vias 28 connected to first wirings 15 and second wirings 29 connected to the via 28 , are formed. Furthermore, dummy vias 28 a are formed on the periphery of the isolated via 28 , and second dummy wirings 29 a are formed on the periphery of the second wiring 29 .
  • the cap film 23 may be removed when Cu and the barrier metal is subjected to CMP.
  • the presence of the cap film 23 is optional in the final interconnecting structure (The same applies to Embodiments 2 to 5 described later.). Even when the cap film 23 is removed, the equivalent device characteristics as in the case where the cap film 23 remains ( FIG. 2A ) can be obtained.
  • dummy vias 28 a are formed on the periphery of an isolated via 28 in the p-SiOC film 22 , which is a low-k dielectric film.
  • the opening ratio of vias is high, the endpoint of etching for forming via holes 25 and 25 a can be detected stably. Thereby, the via holes passing through the underlying films, or defective openings can be prevented, and a wide process margin can be secured.
  • the above-described effects can be obtained as long as the dimension of dummy vias is 1 to 10 times the minimum dimension of the via 28 .
  • the pitch of dummy vias is not limited to 0.5 ⁇ m, but may be optional if the occupation ratio of vias to the pattern is constant within a range between 0.5% and 30%.
  • the shape of the dummy vias is not limited to the shape having a square opening cross section as shown in FIG. 1 , but the above-described effects can also be obtained from cylindrical shapes, or slit shapes having rectangular opening cross sections (The same applies to second to fifth embodiments described later.).
  • p-SiOC films are used as low-k dielectric films 12 and 22
  • the present invention is not limited thereto, but any low-k dielectric films can be applied as long as dielectric constant of the low-k dielectric film is 3 or less.
  • ultra-low-k dielectric films such as porous films, can also be applied.
  • p-SiC films are used as stopper films 11 and 21
  • p-SiN films can also be used, and laminated films of p-SiC films and p-SiN films can also be used.
  • the stopper film is not necessarily required if a sufficient selection ratio to underlying films can be secured.
  • W or Cu are used as the material for the vias (plugs), other conductive materials, such as TaN, TiN, Ta and Ti, or the laminate thereof can also be used (The same applies to second to fifth embodiments described later.).
  • FIG. 4 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a second embodiment of the present invention.
  • FIG. 5 is a sectional view taken along the line B-B′ of FIG. 4 showing the interconnecting structure manufactured using a dual damascene method.
  • dummy vias 28 a not connected to the first and second wirings 15 and 29 are disposed on the periphery of the isolated via 28 in the first embodiment
  • dummy vias 28 b connected to the first wirings 15 are disposed on the periphery of the isolated via 28 in the second embodiment.
  • the use of the dual damascene method can reduce the stress migration of first and second wirings 15 and 29 having large wiring width.
  • the dummy vias 28 b are connected only to the first wirings 15
  • the dummy vias may be connected only to the second wirings 29 , and the mixture of these dummy vias may be present on the periphery of the isolated via 28 .
  • FIG. 6 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a sectional view taken along the line C-C′ of FIG. 6 showing the interconnecting structure manufactured using a dual damascene method.
  • dummy vias 28 a not connected to the first and second wirings 15 and 29 are disposed on the periphery of the isolated via 28 in the first embodiment
  • dummy vias 28 c connected to both the first dummy wirings 15 a and the second dummy wirings 29 a are disposed on the periphery of the isolated via 28 in the third embodiment.
  • the use of the dual damascene method can reduce the stress migration of first and second wirings 15 and 29 having large wiring width.
  • FIG. 8 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 9 is a sectional view taken along the line D-D′ of FIG. 8 showing the interconnecting structure manufactured using a dual damascene method.
  • FIGS. 8 and 9 show, in an interconnecting structure according to the fourth embodiment, dummy vias 28 a connected to neither first wirings 15 nor second wirings 29 , dummy vias 28 b connected to first wirings 15 , and dummy vias 28 c connected to both first dummy wirings 15 a and second dummy wirings 29 a are disposed on the periphery of the isolated via 28 .
  • all of dummy vias 28 a , 28 b , and 28 c in the first to third embodiments are applied.
  • the equivalent effects as the effects obtained in the first embodiment can be obtained.
  • the fourth embodiment is suitable for the reduction of stress migration particularly when wirings 15 and 29 having large wiring width are formed.
  • FIG. 10 is a schematic top view for illustrating an interconnecting structure in a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 11 is a sectional view taken along the line E-E′ of FIG. 10 showing the interconnecting structure manufactured using a dual damascene method.
  • first and second dummy wirings 15 a and 29 a of a size of 1 ⁇ m ⁇ 1 ⁇ m are formed on the peripheries of first and second wirings 15 and 29 , and the wirings 15 a and 29 a are connected with dummy vias 28 c.
  • first dummy wirings 15 b including line patterns of a line width of 0.5 ⁇ m are formed in a pitch of 2 ⁇ m on the periphery of the first wirings 15 .
  • second dummy wirings 29 b including line patterns of a line width of 0.5 ⁇ m are formed in a pitch of 2 ⁇ m on the periphery of the first wirings 15 so as to intersect the first dummy wirings 15 b .
  • dummy vias 28 d are disposed on the intersections of the first dummy wirings 15 b and the second dummy wirings 29 b .
  • the potential of the dummy pattern including the first and second dummy wirings 15 b and 29 b and the dummy vias 28 d , was equalized. Furthermore, at least one of the first and second dummy wirings 15 b and 29 b and the dummy vias 28 d was connected to the ground potential.
  • the first dummy wirings 15 b and second dummy wirings 29 b are disposed in a lattice pattern, and dummy vias 28 d are disposed on the intersections thereof.
  • dummy vias 28 d are disposed on the periphery of the isolated via 28 , the equivalent effects as the effects obtained in the first embodiment can be obtained.
  • dummy patterns 15 b , 28 d and 29 b having the same potential through the dummy vias 28 d , are connected to a ground potential at optional locations. Since circuit patterns 15 , 28 , and 29 are shielded by these dummy patterns 15 b , 28 d and 29 b , the malfunction of the circuit patterns due to external noise can be inhibited. Therefore, an interconnecting structure having a high margin against external noise, and the manufacturing method thereof can be obtained.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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US9054164B1 (en) 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
KR102326120B1 (ko) 2015-06-29 2021-11-15 삼성전자주식회사 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치
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