CN1581475B - 互连结构的制造方法 - Google Patents

互连结构的制造方法 Download PDF

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Publication number
CN1581475B
CN1581475B CN2004100485795A CN200410048579A CN1581475B CN 1581475 B CN1581475 B CN 1581475B CN 2004100485795 A CN2004100485795 A CN 2004100485795A CN 200410048579 A CN200410048579 A CN 200410048579A CN 1581475 B CN1581475 B CN 1581475B
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CN
China
Prior art keywords
film
wiring
dummy
wiring structure
sioc film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2004100485795A
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English (en)
Chinese (zh)
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CN1581475A (zh
Inventor
富田和朗
桥本圭司
西冈康隆
松本晋
关口满
岩崎晃久
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Renesas Electronics Corp
Panasonic Holdings Corp
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Renesas Technology Corp
Matsushita Electric Industrial Co Ltd
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Publication of CN1581475A publication Critical patent/CN1581475A/zh
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Publication of CN1581475B publication Critical patent/CN1581475B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN2004100485795A 2003-08-12 2004-06-14 互连结构的制造方法 Expired - Fee Related CN1581475B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP292166/2003 2003-08-12
JP292166/03 2003-08-12
JP2003292166A JP2005064226A (ja) 2003-08-12 2003-08-12 配線構造

Publications (2)

Publication Number Publication Date
CN1581475A CN1581475A (zh) 2005-02-16
CN1581475B true CN1581475B (zh) 2010-05-26

Family

ID=34131700

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004100485795A Expired - Fee Related CN1581475B (zh) 2003-08-12 2004-06-14 互连结构的制造方法

Country Status (6)

Country Link
US (2) US20050035457A1 (enExample)
JP (1) JP2005064226A (enExample)
KR (2) KR20050018585A (enExample)
CN (1) CN1581475B (enExample)
DE (1) DE102004028925A1 (enExample)
TW (1) TWI315542B (enExample)

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CN1988146A (zh) * 2005-12-22 2007-06-27 中芯国际集成电路制造(上海)有限公司 哑元图案和机械增强低k介电材料的制造方法
US20070287279A1 (en) * 2006-06-08 2007-12-13 Daubenspeck Timothy H Methods of forming solder connections and structure thereof
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US8669597B2 (en) 2008-05-06 2014-03-11 Spansion Llc Memory device interconnects and method of manufacturing
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JP2012148428A (ja) * 2011-01-17 2012-08-09 Toshiba Tec Corp インクジェットヘッドの製造方法
US8847393B2 (en) * 2011-02-28 2014-09-30 Freescale Semiconductor, Inc. Vias between conductive layers to improve reliability
CN102437105B (zh) * 2011-11-28 2014-08-13 上海华力微电子有限公司 具有部分冗余通孔的集成电路制作方法及集成电路
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US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
US8629559B2 (en) * 2012-02-09 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stress reduction apparatus with an inverted cup-shaped layer
US9343411B2 (en) * 2013-01-29 2016-05-17 Intel Corporation Techniques for enhancing fracture resistance of interconnects
FR3003962B1 (fr) 2013-03-29 2016-07-22 St Microelectronics Rousset Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants
WO2015026342A1 (en) * 2013-08-21 2015-02-26 Intel Corporation Method and structure to contact tight pitch conductive layers with guided vias
US9054164B1 (en) * 2013-12-23 2015-06-09 Intel Corporation Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
KR102326120B1 (ko) * 2015-06-29 2021-11-15 삼성전자주식회사 배선 구조물 및 그 형성 방법, 및 상기 배선 구조물을 갖는 반도체 장치
KR102382826B1 (ko) 2015-09-08 2022-04-04 삼성전자주식회사 반도체 장치의 제조 방법
KR102521554B1 (ko) * 2015-12-07 2023-04-13 삼성전자주식회사 배선 구조물, 배선 구조물 설계 방법, 및 배선 구조물 형성 방법
US20190109090A1 (en) * 2017-08-15 2019-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure lined by isolation layer
US11705395B2 (en) * 2018-06-25 2023-07-18 Intel Corporation Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects
KR102866394B1 (ko) 2020-07-01 2025-09-29 삼성전자주식회사 3차원 반도체 메모리 장치
US20230411212A1 (en) * 2022-06-15 2023-12-21 International Business Machines Corporation Shallow and deep contacts with stitching

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US6468894B1 (en) * 2001-03-21 2002-10-22 Advanced Micro Devices, Inc. Metal interconnection structure with dummy vias
US6492259B2 (en) * 1999-05-12 2002-12-10 International Business Machines Corporation Process for making a planar integrated circuit interconnect

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US5625232A (en) * 1994-07-15 1997-04-29 Texas Instruments Incorporated Reliability of metal leads in high speed LSI semiconductors using dummy vias
US5675187A (en) * 1994-07-15 1997-10-07 Texas Instruments Incorporated Reliability of metal leads in high speed LSI semiconductors using dummy vias
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US6468894B1 (en) * 2001-03-21 2002-10-22 Advanced Micro Devices, Inc. Metal interconnection structure with dummy vias

Also Published As

Publication number Publication date
TW200507010A (en) 2005-02-16
KR20050018585A (ko) 2005-02-23
CN1581475A (zh) 2005-02-16
KR20060108601A (ko) 2006-10-18
DE102004028925A1 (de) 2005-04-28
US7605085B2 (en) 2009-10-20
KR100770486B1 (ko) 2007-10-25
US20070007658A1 (en) 2007-01-11
US20050035457A1 (en) 2005-02-17
JP2005064226A (ja) 2005-03-10
TWI315542B (en) 2009-10-01

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Effective date: 20100920

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Co-patentee after: Matsushita Electric Industrial Co., Ltd.

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Patentee before: Renesas Technology Corp.

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Granted publication date: 20100526

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