CN1649119A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1649119A
CN1649119A CNA2005100058713A CN200510005871A CN1649119A CN 1649119 A CN1649119 A CN 1649119A CN A2005100058713 A CNA2005100058713 A CN A2005100058713A CN 200510005871 A CN200510005871 A CN 200510005871A CN 1649119 A CN1649119 A CN 1649119A
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CN
China
Prior art keywords
wiring
semiconductor
semiconductor device
constituting body
plate
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Granted
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CNA2005100058713A
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English (en)
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CN100341127C (zh
Inventor
定别当裕康
三原一郎
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Publication of CN1649119A publication Critical patent/CN1649119A/zh
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本发明的提供一种减少在半导体构成体的周围产生的无效空间的半导体器件。本发明的半导体器件包括：基底构件(22)；半导体构成体(3)，设置在所述基底构件(22)上，并且具有半导体衬底(5)和在该半导体衬底(5)上设置的多个外部连接用电极(13)；布线板(26)，设置在所述半导体构成体(3)的周围，至少在一个面上具有第1布线(33、34)；以及第2布线(19)，设置在所述半导体构成体(3)和所述布线板(26)上，被连接到所述半导体构成体(3)的外部连接用电极(13)。这种情况下，由于在半导体构成体(3)的周围设有布线板(26)，所以可以减少在半导体构成体(3)的周围产生的无效空间。

Description

半导体器件
技术领域
本发明涉及内置半导体构成体的半导体器件。
背景技术
日本特开2003-298005号公报(日本)中公开的现有的半导体器件，具有以下结构：为了在硅衬底的尺寸以外还配有作为外部连接用连接端子的焊料球，将上表面具有多个连接焊盘的硅衬底设置在基板的上表面，在硅衬底周围的基板的上表面设置绝缘层，在硅衬底和绝缘层的上表面设置上层绝缘膜，在上层绝缘膜的上表面设置与硅衬底的连接焊盘连接的上层布线，用最上层绝缘膜覆盖上层布线的、除了连接焊盘部以外的部分，在上层布线的连接焊盘部上设有焊料球。
可是，在上述现有的半导体器件中，由于在硅衬底周围的基板的上表面设置的绝缘层如文字表述那样是绝缘层，所以在增大绝缘层的平面尺寸而增大整体的平面尺寸的情况下，存在绝缘层会出现大的无效空间(dead space)的问题。
发明内容
因此，本发明的目的在于提供一种半导体器件，可以减少在硅衬底等半导体衬底的周围产生的无效空间。
根据本发明，提供一种半导体器件，包括：基底构件22；半导体构成体3，设置在所述基底构件22上，并且具有半导体衬底5和在该半导体衬底5上设置的多个外部连接用电极13；布线板26，设置在所述半导体构成体3的周围，至少在一个面上具有第1布线33、34；以及第2布线19，设置在所述半导体构成体3和所述布线板26上，被连接到所述半导体构成体3的外部连接用电极13。
根据本发明，由于在具有半导体基板和外部连接用电极的半导体构成体的周围设置布线板，所以可以减少在半导体基板周围产生的无效空间。
附图说明
图1是作为本发明第1实施方式的半导体器件的剖面图。
图2是制造图1所示的半导体构成体时、最初准备的半导体构成体的剖面图。
图3是接续图2的工序的剖面图。
图4是接续图3的工序的剖面图。
图5是接续图4的工序的剖面图。
图6是接续图5的工序的剖面图。
图7是接续图6的工序的剖面图。
图8是接续图7的工序的剖面图。
图9是接续图8的工序的剖面图。
图10是接续图9的工序的剖面图。
图11是接续图10的工序的剖面图。
图12是接续图11的工序的剖面图。
图13是接续图12的工序的剖面图。
图14是接续图13的工序的剖面图。
图15是接续图14的工序的剖面图。
图16是接续图15的工序的剖面图。
图17是接续图16的工序的剖面图。
图18是接续图17的工序的剖面图。
图19是接续图18的工序的剖面图。
图20是作为本发明的第2实施方式的半导体器件的剖面图。
图21是制造图20所示的半导体构成体时、规定的工序的剖面图。
图22是作为本发明的第3实施方式的半导体器件的剖面图。
具体实施方式
(第1实施方式)
图1表示作为本发明第1实施方式的半导体器件的剖面图。该半导体器件包括半导体块1。如果简单说明，半导体块1具有：支承板2；半导体构成体3；绝缘层15；上层绝缘膜16；上层布线19(第2布线)。即，半导体块1包括平面方形的支承板2。支承板2可以是树脂、硅、陶瓷等的绝缘板，也可以是铜箔等的金属板，而且，也可以是后述的预浸渍(prepreg)材料或复合(build-up)材料。
在支承板2的上表面，通过由管芯键合(die bond)材料构成的粘结层4，来粘结尺寸比支承板2的尺寸小一些的平面方形的半导体构成体3的下表面。这种情况下，半导体构成体3具有后述的布线12、柱状电极13、密封膜14，一般被称为CSP(chip size package：芯片尺寸封装)，如后述那样，在硅晶片上形成布线12、柱状电极13、密封膜14后，采用通过切割来获得各个半导体构成体3的方法，所以被特别称为晶片级CSP(W-CSP)。以下，说明半导体构成体3的结构。
半导体构成体3包括平面方形的硅衬底(半导体基板)5。硅衬底5的下表面通过粘结层4被粘结在支承板2上。在硅衬底5的上表面上设有规定功能的集成电路(未图示)，在上表面周边部设有由铝类金属等构成的、与集成电路连接的多个连接焊盘6。在除了连接焊盘6的中央部以外的硅衬底5的上表面上设有由氧化硅等构成的绝缘膜7，连接焊盘6的中央部通过在绝缘膜7中设置的开口部8而露出。
在绝缘膜7的上表面上设有由环氧类树脂或聚酰亚胺类树脂等构成的保护膜9。这种情况下，在与绝缘膜7的开口部8对应的部分的保护膜9中设有开口部10。在保护膜9的上表面上设有铜等构成的基底金属层11。在基底金属层11的整个上表面上设有铜构成的布线12。包含基底金属层11的布线12的一端部通过两开口部8、10连接到连接焊盘6上。
在布线12的连接焊盘部上表面上设有铜构成的柱状电极(外部连接用电极)13。在包含布线12的保护膜9的上表面上设有环氧类树脂或聚酰亚胺类树脂等构成的密封膜14，其上表面与柱状电极13的上表面成为同一面。这样，被称为W-CSP的半导体构成体3包括硅衬底5、连接焊盘6、绝缘膜7，还包括保护膜9、布线12、柱状电极13、密封膜14。
在半导体构成体3周围的支承板2的上表面上设有方框状的绝缘层15，其上表面与半导体构成体3的上表面大致为同一面。绝缘层15例如由环氧类树脂或聚酰亚胺类树脂等的热固化性树脂、或在这样的热固化性树脂中混入玻璃纤维或二氧化硅填料等的补强材料而构成。
在半导体构成体3和绝缘层15的上表面上设有使其上表面平坦的上层绝缘膜16。上层绝缘膜16用于多层电路板，通常被称为复合材料，例如，由在环氧类树脂或聚酰亚胺类树脂等的热固化性树脂中混入玻璃纤维或二氧化硅填料等补强材料的物质构成。在与柱状电极13的上表面中央部对应的部分的上层绝缘膜16中设有开口部17。
在上层绝缘膜16的上表面上设有铜等构成的上层基底金属层18。在上层基底金属层18的整个上表面上设有铜构成的上层布线19。包含上层基底金属层18的上层布线19的一端部，通过上层绝缘膜16的开口部17而连接到柱状电极13的上表面。这样，半导体块1包括支承板2、半导体构成体3、绝缘层15、上层绝缘膜16、上层布线19而构成。
然后，半导体块1的支承板2被粘结固定在平面方形的下侧布线板(基底构件)21的上表面的规定部位。下侧布线板21的构造是：通过设置于绝缘衬底22内的通路(via)25来连接在绝缘衬底(基底构件)22的上表面上设置的上表面布线(第3布线)23、在绝缘衬底22的下表面上设置的下表面布线(第3布线)24。这种情况下，绝缘衬底22通常是被称为预浸渍材料的物质，例如，由在玻璃布或芳族聚酰胺纤维等构成的基材中浸渍环氧类树脂等热固化性树脂而构成，但也可以使用复合材料。上表面布线23和下表面布线24由铜箔构成。通路25由金属膏或导电性树脂膏等构成。
在半导体块1周围的下侧布线板21的上表面上设有方框状的中间布线板26，其上表面与半导体构成体3的上表面大致成为同一面。中间布线板26由多层布线板构成，例如，具有以下构造：在第1绝缘衬底27的上下表面上叠层第2、第3绝缘衬底28、29，在第2绝缘衬底28内设置的通路30、以及在第3绝缘衬底29内设置的通路31，通过在第1绝缘衬底27内设置的通路32和在第1绝缘衬底27的上下表面设置的上表面布线(第1布线)33、下表面布线(第1布线)34而连接。
这种情况下，第1～第3绝缘衬底27～29由与下侧布线板21的绝缘衬底22相同的材料—预浸渍材料或复合材料构成。上表面布线33和下表面布线34由铜箔构成。通路25由金属膏或导电性树脂膏等构成。因而，第3绝缘衬底29的通路31被连接到下侧布线板21的上表面布线23。
在半导体块1和中间布线板26的上表面上设有上侧布线板35。上侧布线板35具有以下构造：在绝缘衬底36的上表面上设置的上表面布线37(第4布线)、以及在绝缘衬底36的下表面上设置的下表面布线(第4布线)38，通过在绝缘衬底36内设置的通路39而连接。这种情况下，绝缘衬底36由与下侧布线板2 1的绝缘衬底22相同的材料—预浸渍材料或复合材料构成。上表面布线37和下表面布线38由铜箔构成。通路39由金属膏或导电性树脂膏等构成。
并且，上侧布线板35的下表面布线38被连接到中间布线板26的第2绝缘衬底28的通路30。此外，在上侧布线板35的上表面布线37下面设置的通路39的一部分连接到半导体块1的上层布线19的连接焊盘部，而不连接到下表面布线38。
在上侧布线板35的上表面上设有阻焊剂等构成的上层外敷膜40。在与上侧布线板35的上表面布线37的连接焊盘部对应的部分的上层外敷膜40中设有开口部41。在开口部41内和其上方设有焊料球42，其连接到上侧布线板35的上表面布线37的连接焊盘部。多个焊料球42在上层外敷膜40的上表面上矩阵状地配置。
在下侧布线板21的下表面上设有阻焊剂等构成的下层外敷膜43。在与下侧布线板21的下表面布线24的连接焊盘部对应的部分的下层外敷膜43中设有开口部44。在开口部44内设有由金属膏或导电性树脂膏等构成的导电连接部45。在下层外敷膜43的下表面上，由电容器和电阻等构成的片式部件(电子部件)46设置为其两侧的电极连接到导电连接部45。
可是，在半导体块1中，支承板2的尺寸比半导体构成体3的尺寸大一些的原因在于，随着硅衬底5上的连接焊盘6的数目的增加，上层布线19的连接焊盘部的配置区域比半导体构成体3的尺寸大一些，由此，使上层布线19的连接焊盘部的尺寸和节距比柱状电极13的尺寸和节距大。
因此，矩阵状配置的上层布线19的连接焊盘部不仅配置在对应于半导体构成体3的区域，而且还配置在与半导体构成体3的侧面外侧设置的绝缘层15对应的区域上。即，在矩阵状配置的上层布线19的连接焊盘部中，至少最外周的连接焊盘部被配置在比半导体构成体3更位于外侧的周围。
此外，在该半导体器件中，在具有硅衬底5的半导体块1周围的下侧布线板21的上表面上，设有方框状的中间布线板26，所以即使作为整体的平面尺寸增大某种程度，也可以减少在硅衬底5周围产生的无效空间。
而且，在该半导体器件中，由于在半导体块1周围的下侧布线板21的上表面上设有方框状的中间布线板26，所以与设置了简单的绝缘层来取代中间布线板26的情况比较，可以形成高密度布线构造。即，在设有简单的绝缘层来取代中间布线板26的情况下，在该绝缘层中形成通孔，从而只将上侧布线板35和下侧布线板21连接，不能形成高密度布线构造。
下面，说明该半导体器件的制造方法的一例。首先，说明半导体构成体3的制造方法的一例。这种情况下，首先，如图2所示，准备如下的半导体构成体：在晶片状态的硅衬底(半导体衬底)5上设置由铝类金属等构成的连接焊盘6、由氧化硅等构成的绝缘膜7和由环氧类树脂或聚酰亚胺类树脂等构成的保护膜9，连接焊盘6的中央部通过在绝缘膜7和保护膜9中形成的开口部8、10而露出。在上述中，在晶片状态的硅衬底5中，在形成各半导体构成体的区域形成规定功能的集成电路，连接焊盘6分别与在对应的区域中形成的集成电路电连接。
接着，如图3所示，在包含了通过两开口部8、10露出的连接焊盘6的上表面的保护膜9整个上表面上，形成基底金属层11。这种情况下，基底金属层11可以只是通过无电解电镀形成的铜层，或者只是通过溅射形成的铜层，而且也可以在通过溅射形成的钛等的薄膜层上形成铜层。这对后述的上层基底金属层18也是同样的。
接着，在基底金属层11的上表面上构图形成电镀抗蚀剂膜51。这种情况下，在与布线12形成区域对应的部分的电镀抗蚀剂膜51中形成开口部52。接着，通过以基底金属层11作为电镀电流路径来进行铜的电解电镀，从而在电镀抗蚀剂膜51的开口部52内的基底金属层11的上表面上形成布线12。接着，将电镀抗蚀剂膜51剥离。
接着，如图4所示，在包含布线12的基底金属层11的上表面上构图形成电镀抗蚀剂膜53。这种情况下，在与柱状电极13形成区域对应的部分的电镀抗蚀剂膜53中形成开口部54。接着，通过将基底金属层11作为电镀电流路径进行铜的电解电镀，从而在电镀抗蚀剂膜53的开口部54内的布线12的连接焊盘部上表面形成柱状电极13。接着，将电镀抗蚀剂膜53剥离，然后，以布线12作为掩模而腐蚀除去基底金属层11的无用部分，如图5所示，只在布线12下面留下基底金属层11。
接着，如图6所示，通过丝网印刷法、旋转涂敷法、双涂敷法等，在包含柱状电极13和布线12的保护膜9的整个上表面上，形成厚度大于柱状电极13的高度、且由环氧类树脂或聚酰亚胺类树脂等构成的密封膜14。因此，在该状态下，柱状电极13的上表面被密封膜14覆盖。
接着，对密封膜14和柱状电极13的上表面侧适当地进行研磨，如图7所示，使柱状电极13的上表面露出，并且，对包含该露出的柱状电极13的上表面的密封膜14的上表面进行平坦化。这里，对柱状电极13的上表面侧适当地进行研磨的原因在于，通过电解电镀形成的柱状电极13的高度有偏差，所以消除这种偏差，从而使柱状电极13的高度均匀。
接着，如图8所示，将粘结层4粘结在硅衬底5的整个下表面上。粘结层4由环氧类树脂、聚酰亚胺类树脂等的管芯键合材料构成，通过加热加压，在半固化的状态下粘结在硅衬底5上。接着，将固定粘结在硅衬底5上的粘结层4粘贴在分割带(未图示)上，经过图9所示的分割工序后，与分割带剥离，则如图1所示，获得多个在硅衬底5的下表面上具有粘结层4的半导体构成体3。
在这样获得的半导体构成体3中，由于在硅衬底5的下表面上具有粘结层4，所以不需要在分割工序后在各半导体构成体3的硅衬底5的下表面上分别设置粘结层的极其麻烦的作业。再有，与在分割工序后分别在各半导体构成体3的硅衬底5的下表面上设置粘结层的作业相比，在分割工序后与分割带剥离的作业非常简单。
接着，说明用这样获得的半导体构成体3制造图1所示的半导体块1时的一例。首先，如图10所示，以能够采取多片图1所示的支承板2的尺寸，没有限定的意思，来准备平面方形状的支承板2。接着，在支承板2的上表面的规定的多个部位中粘结被分别粘结在半导体构成体3的硅衬底5的下表面上的粘结层4。这里的粘结通过加热加压使粘结层4固化。
接着，如图11所示，在半导体构成体3周围的支承板2的上表面上，例如通过丝网印刷法或旋转涂敷法等，形成绝缘层形成用层15a。绝缘层形成用层15a例如是在环氧类树脂或聚酰亚胺类树脂等的热固化性树脂、或者在这样的热固化性树脂中混入玻璃纤维或二氧化硅填料等的补强材料的层。
接着，在半导体构成体3和绝缘层形成用层15a的上表面上配置上层绝缘膜形成用片16a。上层绝缘膜形成用片16a，没有限定的意义，但片状的复合材料较好，作为这种复合材料，是在环氧类树脂等的热固化性树脂中混入二氧化硅填料、使热固化性树脂为半固化状态的材料。再有，作为上层绝缘膜形成用片16a，也可以使用在由玻璃等无机材料构成的织布或非织布中浸渍环氧类树脂等热固化性树脂、使热固化性树脂为半固化状态而形成片状的预浸渍材料，或者不混入二氧化硅填料、仅使用热固化性树脂构成的片状材料。
接着，如图12所示，用一对加热加压板55、56从上下方对绝缘层形成用层15a和上层绝缘膜形成用片16a进行加热加压。于是，在半导体构成体3周围的支承板2的上表面上形成绝缘层15，在半导体构成体3和绝缘层15的上表面上形成上层绝缘膜16。这种情况下，上层绝缘膜16上表面被上侧加热加压板55的下表面挤压，所以成为平坦面。因此，不需要用于使上层绝缘膜16上表面平坦化的研磨工序。
接着，如图13所示，通过照射激光束的激光加工，在与柱状电极13的上表面上央部对应的部分的上层绝缘膜16中形成开口部17。接着，根据需要，通过去污处理而除去在开口部17内等产生的污迹等。接着，如图14所示，在包含了通过开口部17露出的柱状电极13的上表面的上层绝缘膜16的整个表面上，通过进行铜的无电解电镀，形成上层基底金属层18。接着，在上层基底金属层18的上表面上构图形成电镀抗蚀剂膜57。这种情况下，在与上层布线19的形成区域对应的部分的电镀抗蚀剂膜57中形成开口部58。
接着，以上层基底金属层18作为电镀电流路径进行铜的电解电镀，从而在电镀抗蚀剂膜57的开口部58内的上层基底金属层18的上表面上形成上层布线19。接着，将电镀抗蚀剂膜57剥离，接着，以上层布线19作为掩模来腐蚀除去上层基底金属层18的无用部分后，如图15所示，只有上层布线19下面的上层基底金属层18被保留。接着，如图16所示，在相互邻接的半导体构成体3间，切断上层绝缘膜16、绝缘层15和支承板2后，获得多个图1所示的半导体块1。
接着，说明用这样获得的半导体块1制造图1所示的半导体器件时的一例。首先，如图17所示，以能够采用多片图1所示的下侧布线板21的尺寸，没有限定的意思，准备平面方形状的下侧集合布线板21a。此外，准备与下侧集合布线板21a相同尺寸的上侧集合布线板35a。而且，准备用于形成与下侧集合布线板21a相同尺寸的中间集合布线板26a的第1～第3绝缘衬底27～29。
这里，由于各集合布线板21a、26a、35a的基本构造相同，所以作为代表，说明下侧集合布线板21a的形成方法的一例。首先，准备在由预浸渍材料或复合材料构成的片状的绝缘衬底22的一面或上下面层叠了铜箔的带有铜箔的布线用基板。这种情况下，绝缘衬底22中的环氧类树脂等的热固化性树脂为半固化状态。接着，在绝缘衬底22中，通过光刻技术或照射激光束的激光加工而形成通孔，并在通孔内填充金属膏等而形成通路25，对绝缘衬底22的一面或上下表面上层叠的铜箔进行构图来形成上表面布线23和下表面布线24。这种情况下，也可以将由导电材料构成的管脚压入在通孔内来形成通路25。
作为另一形成方法，在形成了通孔后，通过无电解电镀和电解电镀，或者通过溅射法和电解电镀，也可以形成上表面布线23、下表面布线24和通路25。然后，在第1～第3绝缘衬底27～29的情况下，通过分组，形成多个方形的开口部61，并形成平面形状为格子状的开口部。
接着，将半导体块1的支承板2的下表面分别暂时压接在下侧集合布线板21a的绝缘衬底22上表面的规定的多个部位上。即，使用带有加热机构的键合工具(未图示)，在加热状态下施加一定的压力，同时将半导体块1暂时压接在包含了半固化状态的热固化性树脂的绝缘衬底22上表面的规定部位上。作为一例，暂时压接条件为温度90～130℃、压力0.1～1Mpa。
接着，一边用管脚等进行定位，一边将第1～第3绝缘衬底27～29配置在半导体块1周围的下侧集合布线板21a的上表面上。在该状态下，第1～第3绝缘衬底27～29的开口部61的尺寸比半导体块1的尺寸稍大，所以在第1～第3绝缘衬底27～29的开口部61和半导体块1之间形成间隙62。此外，在该状态下，第2绝缘衬底28的上表面被配置在比半导体块1的上表面高一些的位置上。
接着，一边用管脚等进行定位，一边将上侧集合布线板35a配置在第2绝缘衬底28的上表面上。在上述的工序中，在下侧集合布线板21a上配置半导体块1和第1～第3绝缘衬底27～29的顺序也可以相反，可以先配置第1～第3绝缘衬底27～29后，在该第1～第3绝缘衬底27～29的各开口部61内配置半导体块1。
接着，如图18所示，使用一对加热加压板63、64从上下侧对下侧集合布线板21a、第1～第3绝缘衬底27～29和上侧集合布线板35a进行加热加压。于是，下侧集合布线板21a的绝缘衬底23中的热固化性树脂被固化，将半导体块1的支承板2下表面粘结在绝缘衬底22的上表面上。
此外，第1～第3绝缘衬底27～29中的熔融的热固化性树脂被挤出，填充到图17所示的间隙62中，并且，该热固化性树脂被固化，使第1～第3绝缘衬底27～29成为一体，中间集合布线板26a被粘结形成在半导体块1的侧面和下侧集合布线板21a的上表面上。而且，上侧集合布线板35a的绝缘衬底36中的热固化性树脂被固化，上侧集合布线板36a被粘结在半导体块1和中间集合布线板26a的上表面上。
在这种状态下，在中间集合布线板26a中，第2绝缘衬底28的通路30和第3绝缘衬底29的通路31通过第1绝缘衬底27的上表面布线33、通路32和下表面布线34而连接。此外，中间集合布线板26a的第3绝缘衬底29的通路31连接到下侧集合布线板21a的上表面布线23上。此外，上侧集合布线板35a的下表面布线38连接到中间集合布线板26a的第2绝缘衬底28的通路30上。而且，上侧集合布线板35a的通路39的一部分连接到半导体块1的上层布线19的连接焊盘部。
这样，通过使用一对加热加压板63、64进行一次加热加压，将下侧集合布线板21a、中间集合布线板26a和上侧集合布线板35a成为一体，此外，将半导体块1粘结在下侧集合布线板21a的上表面上，而且，由于将半导体块1的侧面和上表面用中间集合布线板26a和上侧集合布线板35a覆盖，所以可以减少制造工序数。再有，在上述中，中间集合布线板26a使第1～第3绝缘衬底27～29相互预先暂时粘结，将该暂时粘结的绝缘衬底配置在上侧集合布线板35a和下侧集合布线板21a之间，并用一对加热加压板63、64进行加热就可以。
接着，如图19所示，通过丝网印刷法或旋转涂敷法等，在上侧集合布线板35a的上表面上形成阻焊剂等构成的上层外敷膜40，此外，在下侧集合布线板21a的下表面上形成阻焊剂等构成的下层外敷膜43。这种情况下，在与上侧集合布线板35a的上表面布线37的连接焊盘部对应的部分的上层外敷膜40中形成有开口部41。此外，在与下侧集合布线板21a的下表面布线24的连接焊盘部对应的部分的下层外敷膜43中形成有开口部44。
接着，在下层外敷膜43的开口部44内形成由金属膏等构成的导电连接部45，该导电连接部45连接到下表面布线24的另一端部。接着，在下层外敷膜43的下表面上设置电容器和电阻等构成的片式部件46，该片式部件46的两侧的电极连接到导电连接部45。接着，在上层外敷膜40的开口部41内和其上方形成焊料球42，该焊料球42连接到上表面布线37的连接焊盘部。接着，在相互相邻的半导体构成体3间，切断上层外敷膜40、上侧集合布线板35a、集合中间布线板26a、下侧集合布线板21a和下层外敷膜43后，获得多个图1所示的半导体器件。
(第2实施方式)
图20表示作为本发明的第2实施方式的半导体器件的剖面图。在该半导体器件中，与图1所示情况较大的不同点在于，半导体块1具有以下构造：在包含上层布线19的上层绝缘膜16的上表面上设置阻焊剂等构成的上层外敷膜71，在与上层布线19的连接焊盘部对应的部分的上层外敷膜71中设置开口部72，在开口部72内设置金属膏等构成的导电连接部73，该导电连接部73连接到上层布线19的连接焊盘部。因而，上侧布线板35的下表面布线38连接到半导体块1的导电连接部73。
在制造这种半导体器件的情况下，在与第1实施方式的图17对应的工序中，如图21所示，使上下方向与图20所示的情况相反，通过将半导体块1的导电连接部73连接到上侧布线板35的下表面布线38，从而将半导体块1配置在上侧布线板35的上表面上，并在半导体块1周围的上侧集合布线板35a的上表面上配置第1～第3绝缘衬底27～29，在第3绝缘衬底29的上表面上配置下侧集合布线板21a。
(第3实施方式)
在第1、第2实施方式中，构成在半导体构成体3的周围设置了绝缘层15的半导体块1，在该半导体块1的周围设置了中间布线板26。对此，在图23所示的第3实施方式中，具有在半导体构成体3的周围直接设置中间布线板26的结构。在该第3实施方式中，省略了绝缘层15的部分，可以缩小半导体器件整体的面积。第3实施方式的其他结构与第1实施方式相同，所以在对应的构件上附以相同的参照标号并省略其说明。但是，在对半固化状态的支承板2进行加热加压而固化时，根据支承板2的粘结力而形成用于保持半导体构成体3的硅衬底5的结构，所以粘结层4被省略。此外，在第3实施方式中，上层绝缘膜16只形成在半导体构成体3的上表面上，但也可以中间布线板26的上表面与半导体构成体3的上表面大致为相同面，上层绝缘膜16跨越中间布线板26的上表面和半导体构成体3的上表面，以覆盖整体。
(其他的实施方式)
在上述实施方式中，作为中间布线板26，使用多层布线板，例如，说明了使用将预浸渍材料构成的第1～第3绝缘衬底27～29层叠的布线板的情况，但不限于此，例如，也可以使用具有通孔电镀导电部的双面布线构造的布线板。
此外，在上述实施方式中，作为半导体构成体3，形成具有作为外部连接用电极的柱状电极13的半导体构成体，但不限于此，也可以没有柱状电极，而是具有作为外部连接用电极的连接焊盘部的布线的半导体构成体，此外，也可以没有柱状电极和布线，而是具有作为外部连接用电极的连接焊盘6的半导体构成体。此外，在上述实施方式中，说明了半导体块1的上层布线为一层的情况，但不限于此，也可以为两层以上。
此外，在上述实施方式中，相互邻接的半导体构成体3之间被切断，但不限于此，也可以将两个或两个以上的半导体构成体3作为一组进行切断。这种情况下，多个为一组的半导体构成体3可以是相同种类、不同种类的其中之一。
此外，在上述实施方式中，作为电子部件，搭载了片式部件46，但不限于此，也可以搭载由裸片或CSP等构成的半导体构成体。此外，无论是搭载了片式部件的情况，还是搭载了半导体构成体的情况，都可以使用焊料球来取代导电连接部45。此外，也可以使用焊料球来取代图20所示的导电连接部73。

Claims (21)

1.一种半导体器件，其特征在于，包括：基底构件(22)；半导体构成体(3)，设置在所述基底构件(22)上，并且具有半导体衬底(5)和在该半导体衬底(5)上设置的多个外部连接用电极(13)；布线板(26)，设置在所述半导体构成体(3)的周围，至少在一个面上具有第1布线(33、34)；以及第2布线(19)，设置在所述半导体构成体(3)和所述布线板(26)上，被连接到所述半导体构成体(3)的外部连接用电极(13)。
2.如权利要求1所述的半导体器件，其特征在于，所述半导体构成体(3)具有在半导体衬底(5)上的外部连接用电极(13)间形成的密封膜(14)。
3.如权利要求1所述的半导体器件，其特征在于，所述基底构件(22)至少在一个面上具有与所述布线板(26)的所述第1布线(33、34)电连接的第3布线(23、24)。
4.如权利要求1所述的半导体器件，其特征在于，所述基底构件(22)由包含热固化性树脂的材料构成。
5.如权利要求4所述的半导体器件，其特征在于，所述基底构件(22)由包含补强材料的材料构成。
6.如权利要求4所述的半导体器件，其特征在于，在所述半导体构成体(3)和所述第2布线(19)上形成有对置面侧绝缘膜(36)。
7.如权利要求6所述的半导体器件，其特征在于，所述对置面侧绝缘膜(36)具有与所述基底构件(22)实质上相同的面积。
8.如权利要求6所述的半导体器件，其特征在于，所述对置面侧绝缘膜(36)由包含热固化性树脂的材料构成。
9.如权利要求6所述的半导体器件，其特征在于，所述对置面侧绝缘膜(36)由包含补强材料的材料构成。
10.如权利要求6所述的半导体器件，其特征在于，在所述对置面侧绝缘膜(36)上形成有第4布线(37)。
11.如权利要求10所述的半导体器件，其特征在于，所述第4布线(37)具有延伸到所述对置面侧绝缘膜(36)上、对应所述布线板(26)而被配置在其上方的连接焊盘部。
12.如权利要求11所述的半导体器件，其特征在于，具有外敷膜(40)，覆盖除了在所述对置面侧绝缘膜(36)上设置的第4布线(37)的连接焊盘部以外的部分。
13.如权利要求12所述的半导体器件，其特征在于，在所述外敷膜(40)的表面设有连接到所述连接焊盘部的焊料球(42)。
14.如权利要求1所述的半导体器件，其特征在于，所述布线板(26)由多层布线板构成。
15.如权利要求1所述的半导体器件，其特征在于，在所述半导体构成体(3)和所述布线板(26)之间，设有绝缘层(15)。
16.如权利要求1所述的半导体器件，其特征在于，在所述半导体构成体(3)的上表面设有上层绝缘膜(16)，所述第2布线(19)被设置在所述上层绝缘膜(16)上。
17.如权利要求1所述的半导体器件，其特征在于，在所述半导体构成体(3)和所述基底构件(22)之间配置有支承板(2)。
18.如权利要求1所述的半导体器件，其特征在于，所述半导体构成体(3)通过所述基底构件(22)的粘结力而保持在该基底构件(22)上。
19.如权利要求1所述的半导体器件，其特征在于，所述半导体构成体(3)具有在作为外部连接用电极(13)的柱状电极和所述半导体衬底(5)上的所述柱状电极间形成的密封膜(14)。
20.如权利要求1所述的半导体器件，其特征在于，所述半导体构成体(3)将具有比所述半导体衬底(5)大的面积并支承所述半导体衬底(5)的支承板(2)、和覆盖所述半导体衬底(5)及密封膜(14)的侧面的绝缘层(15)形成为一体，并且，与所述半导体衬底(5)、所述柱状电极(13)、所述密封膜(14)、所述支承板(2)和所述绝缘层(15)一起构成半导体块(1)。
21.如权利要求1所述的半导体器件，其特征在于，所述基底构件(21)在与搭载了所述半导体构成体(3)的面相反的面上具有第3布线(24)，并且在所述第3布线(24)上电连接着电子部件(46)。
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