CN1167122C - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1167122C
CN1167122C CNB981166547A CN98116654A CN1167122C CN 1167122 C CN1167122 C CN 1167122C CN B981166547 A CNB981166547 A CN B981166547A CN 98116654 A CN98116654 A CN 98116654A CN 1167122 C CN1167122 C CN 1167122C
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China
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mentioned
base substrate
semiconductor chip
semiconductor device
conductor layer
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Expired - Fee Related
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CNB981166547A
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English (en)
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CN1206936A (zh
Inventor
藤泽敦
ʷ
今野贵史
大坂慎吾
春田亮
一谷昌弘
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Hitachi Renesas Semiconductor Inc
Hitachi Ltd
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Hitachi Renesas Semiconductor Inc
Hitachi Ltd
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Publication of CN1206936A publication Critical patent/CN1206936A/zh
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Abstract

一种网格焊球阵列型半导体封装件，用粘接材料将半导体芯片安装在柔性膜衬底的表面上，在上述衬底的背面将多个突块电极排列成矩阵，并用树脂密封半导体芯片。具体地说，制作一个绝缘层来覆盖制作在衬底表面上的导体层图形，并用粘接材料将半导体芯片安装在绝缘层上。上述绝缘层在上述半导体芯片下方的区域中被分割成多个互不相连的部分，利用这种被分割的绝缘层，防止了上述半导体芯片与上述导体层图形之间的短路，并抑制了含有上述柔性膜的衬底的变形。

Description

半导体器件
本发明涉及到半导体器件技术，特别是带有含柔性膜的基底衬底的半导体器件。
作为用于高管脚数封装件的合适的半导体器件，已开发了BGA(网格焊球阵列)结构的半导体设备。这种BGA结构的半导体器件用粘合材料将半导体芯片安装在基底衬底主表面的芯片安装区，并在与基底衬底上述主表面相反的背面的阵列中安置一些突块电极。
上述基底衬底由带有例如环氧树脂、聚酰亚胺树脂、马来酰亚胺树脂等浸渍的玻璃纤维的坚硬树脂衬底制成。用于布线连接的电极焊点安置在环绕基底衬底主表面芯片安装区周围的外围区域中，并在基底衬底的背面安置用于突块连接的一些电极。突块电极包含例如Pb-Sn组分的焊料材料，在电学上和机械上固定并连接于突块连接用的电极焊点。
上述半导体芯片包含主要由例如包括单晶硅的半导体衬底构成的结构。半导体芯片上制作有逻辑电路系统、储存电路系统或其它混合电路系统。并在半导体芯片的主表面(元件制作面)上安置一些外部端点(键合点)。这些外部端点被引线电连接于安置在基底衬底主表面上的布线连接用的电极焊点。
上述半导体芯片、引线、引线连接用电极焊点等被密封在制作于基底衬底主表面上的树脂密封体中。此树脂密封体用适合于大批量生产的转移注模方法来制作。
这样组成的BGA结构的半导体器件利用将突块电极熔接到制作在印刷电路板表面上的电极焊点的方法而安装到印刷电路板的表面上。
而且，在例如NIKKEI BP公司出版的NIKKEI Electronics(1994年2月28日号，pp.111-117)中已指出了上述BGA结构的半导体器件。
近年已开发采用柔性膜作为基底衬底的BGA结构半导体器件。比之采用坚硬的树脂衬底作为基底衬底的半导体器件，这种BGA结构的半导体器件能够做得更薄、能够做成插脚数目多的封装件并可小型化。但这些发明人在开发采用柔性膜作为基底衬底的半导体器件时发现有下列问题。
含有柔性膜的基底衬底通常按下列工序制作。首先制作柔性膜突块连接区的连接孔。再用粘接材料将例如含有铜(Cu)的金属箔连接于柔性膜的一侧表面。然后用对金属膜进行图形化的方法制作含有突块连接电极焊点、导体、引线连接电极焊点以及电镀导体等的导体层。再制作保护导体层的绝缘层。然后完成电镀以制作突块连接和引线连接电极焊点的电镀层。电镀过程是用电解电镀方法完成的。这一电镀过程有时在制作绝缘层之前的步骤中完成。此电镀层制作在例如金(Au)/镍(Ni)膜或金(Au)/钯(Pd)/镍(Ni)膜上。
上述绝缘层用例如下列工序制作。首先，在柔性膜的一侧表面上制作感光树脂膜。在烘焙之后，再用印相技术完成感光、显影和冲洗。此绝缘层被制作在含有导体层的柔性膜的一侧表面中除了引线连接电极焊点之外的几乎整个区域。亦即，绝缘层被制作在柔性膜一侧表面的几乎整个区域。因此，在基底衬底中出现翘曲和变形等。基底衬底的这一变形在半导体器件的制造过程(装配过程)中引起传送方面的麻烦。而且，基底衬底的这一变形还是半导体芯片安装工序中粘接材料浸润性能变坏的原因。
至于上述基底衬底的变形，绝缘层的热膨胀系数和凝固收缩率高是主要因素。但倘若不制作绝缘层，则出现下列问题。
(1)突块连接电极焊点被安置在基底衬底主表面的芯片安装区中。因此，当用绝缘粘接材料将半导体芯片安装到基底衬底主表面的芯片安装区时，难以控制粘接材料的厚度。而且，由于半导体芯片接触到突块连接电极焊点而在它们之间引起短路。
(2)突块连接电极焊点被安置在基底衬底主表面的芯片安装区中。安置在基底衬底背面的突块电极，通过制作在基底衬底的芯片安装区中的连接孔，被连接到这些突块连接电极焊点。亦即，突块电极被安置在半导体芯片下方的区域中。
安置在上述基底衬底的芯片安装区的突块连接电极焊点被集成并通过导体电连接到安置在环绕基底衬底主表面芯片安装区外围的周边区域中。亦即，在基底衬底主表面周边区域中，导体被安置在半导体芯片与引线连接电极焊点之间的区域。因此，当用引线连接半导体芯片外端和引线连接焊点时，靠近导体的其它导体就电连接到引线，且这些引线有时自己交叉。在引线连接高度足够的情况下，不会出现问题。但当引线和其它导体在半导体芯片的角落处不平行时，有可能发生与引线和其它导体的短路。而且，在引线和其它导体在引线连接电极焊点侧上彼此交叉的情况下，有可能还出现与引线和其它导体的短路。
本发明的一个目的是提供一种能够抑制带有含柔性膜基底衬底的半导体器件中基底衬底的变形(翘曲和变形)的技术。
本发明的另一目的是提供一种能够抑制带有含柔性膜基底衬底的半导体器件中基底衬底的变形，并防止与基底衬底的导体和半导体芯片短路的技术。
本发明的另一目的是提供一种能够抑制带有含柔性膜基底衬底的半导体器件中基底衬底的变形，并防止基底衬底的导体层和引线发生短路的技术。
本发明的这些和其它目的、特征和优点，在下列描述和附图中将变得更为明显。
下面来解释本申请所公开的本发明的慨要。
(1)一种半导体器件，其中的导体层安置在含有柔性膜的基底衬底的主表面中，且用粘接材料将半导体芯片安装在基底衬底的上述主表面上。而绝缘层被分成基底衬底主表面的上述导体层上的块状结构。绝缘层被分成块状结构例如各个导体层。
(2)一种半导体器件，其中的导体层安置在含有柔性膜的基底衬底主表面的芯片安装区中，且用粘接材料将半导体芯片安装在基底衬底主表面的上述芯片安装区上。而绝缘层被分成基底衬底主表面的上述导体层上的块状结构。绝缘层被分成块状结构例如各个导体层。
(3)一种半导体器件，其中的半导体芯片用粘接材料安置在由柔性膜制成的基底衬底的主表面的芯片安装区中，引线连接电极焊点制作在环绕上述芯片安装区的周边区域中。导体安装在上述周边区域中的上述半导体芯片与上述引线连接电极焊点之间。上述半导体芯片的外端通过引线与上述引线连接电极焊点电连接。而绝缘层被分成上述导体上的块状结构。
利用上述(1)，由于应力被绝缘膜的膨胀和凝固的收缩释放，故可抑制基底衬底的变形(翘曲和变形)。
利用上述(2)，由于半导体芯片不接触到导体层，故当用粘接材料将半导体芯片安装到基底衬底主表面的芯片安装区域上时，可防止与导体层和半导体芯片的短路。
利用上述(3)，由于引线不接触导体，故可防止基底衬底的导体与引线短路。
图1是本发明一个实施例的半导体器件平面图；
图2是沿图1中A-A线的放大剖面图；
图3是图2主要部位的放大剖面图；
图4是移去上述半导体器件的树脂密封体时的平面图；
图5是基底衬底的平面图；
图6是上述半导体器件的主要部位放大剖面图；
图7是上述半导体器件制造工序中所用的框架结构的主要部位平面图；
图8是沿图7中B-B线的放大剖面图；
图9是用来解释上述框架结构的制造方法的主要部位剖面图；
图10是用来解释上述框架结构的制造方法的主要部位剖面图；
图11是用来解释上述半导体器件的制造方法的主要部位剖面图；
图12是用来解释上述半导体器件的制造方法的主要部位剖面图；
图13是用来解释上述半导体器件的制造方法的主要部位剖面图；
图14是用来解释上述半导体器件的制造方法的主剖面图；
图15是用来解释上述半导体器件的制造方法的主要部位平面图；
图16是用来解释上述半导体器件的制造方法的主要部位平面图；
图17是用来解释上述半导体器件的制造方法的主要部位剖面图；
图18是上述框架结构堆叠成多层时的外形结构图；
图19是用来解释上述框架结构的制造方法的主要部位剖面图；
图20是用来解释上述框架结构的制造方法的主要部位剖面图；
图21是主要部位剖面图，示出了本发明一个实施例的半导体器件的第一制作例子；
图22是基底衬底的平面图，示出了本发明一个实施例的半导体器件的第一制作例子；
图23是基底衬底的平面图，示出了本发明一个实施例的半导体器件的第二制作例子；
图24是采用图23所示基底衬底的半导体器件的主要部位剖面图；
图25是基底衬底的平面图，示出了本发明一个实施例的半导体器件的第三制作例子；
图26是基底衬底的平面图，示出了本发明一个实施例的半导体器件的第四制作例子；
下面用用于BGA结构的本发明的实施例来进行解释。用相同的参考号来表示各个图中具有相同功能的元件，略去其重复的解释。
图1是本发明一个实施例的半导体器件平面图。图2是沿图1中A-A线的放大剖面图。图3是图2主要部位的放大剖面图。图4是移去树脂密封体时的平面图。图5是基底衬底的平面图。图6是上述半导体器件的主要部位的放大剖面图。
如图1、图2和图3所示，半导体器件有下述结构。用粘接材料12将半导体芯片10安装在基底衬底1的主表面的芯片安装区上。在基底衬底主表面的背面，将一些突块电极15安装成阵列。突块电极15制作成例如组分重量比Pb∶Sn＝63％∶37％的焊接材料。本实施例的半导体器件是一种表面安装型BGA(网格焊球阵列)封装件，称为CSP(芯片尺寸封装件)，其芯片安装区几乎等于半导体芯片的尺寸。
上述基底衬底1的平面形状为方形。此基底衬底1由含有例如环氧系绝缘树脂或聚酰亚胺系绝缘树脂的柔性膜组成。基底衬底1的厚度被定为例如50μm。
包含突块连接电极焊点2(突块岛)、导体3和引线连接电极焊点4、电镀导体5等的导体层被安置在上述基底衬底1的主表面上。提供了一些突块连接电极焊点2和一些引线连接电极焊点4，并提供了一些电镀用的导体3和导体5。亦即，一些导体层被安置在基底衬底1的主表面上。突块连接电极焊点2与引线连接电极焊点4通过导体3被集成并彼此电连接。电镀用的导体5与引线连接电极焊点4集成并彼此电连接。突块连接电极焊点2、导体3、引线连接电极焊点4以及电镀用的导体5等的制作方法是：在用粘接材料将金属箔(例如铜箔)粘接到柔性膜的主表面之后，在金属箔上进行腐蚀。这些突块连接电极焊点2和导体3、引线连接电极焊点4和电镀用的导体5的厚度被设定为例如18μm。
上述半导体芯片10的平面形状为方形。此半导体芯片10变成主要为例如含有单晶硅的半导体衬底的结构。为半导体芯片10制作了逻辑电路系统、存储电路系统或混合电路系统。这些电路系统是用将一些制得的半导体元件，通过导体而连接到半导体芯片10的主表面侧(元件制作面)10A的方法来制作的。
沿半导体芯片10各边安置的一些外端(键合焊点)11被安置在上述半导体芯片10的主表面10A上。各个外端11被制作于制作在半导体衬底主表面上的导体层的顶层上，并由例如铝(Al)膜或铝合金膜构成。而且，各个外端11被电连接于制作在半导体芯片10上的电路系统。
大部分的上述突块连接电极焊点2被安置在基底衬底1主表面的芯片安装区中。剩下的其它突块连接电极焊点2被安置在环绕基底衬底1主表面的芯片安装区周围的周边区域。安置在基底衬底背面的一些突块电极15，通过制作在基底衬底1中的连接孔而固定在各个突块连接电极焊点2的背面上，并将它们电学上和机械上连接起来。在本实施例中，突块连接电极焊点2的平面形状为圆形。
如图2、图3和图4所示，上述各个引线连接电极焊点4被安置于基底衬底1的主表面的周边区域并沿半导体芯片10的各边安排。各个引线连接电极焊点4通过引线13被电连接于安置在半导体芯片10的主表面10A上的各个外端11。例如，金引线被用作引线13。引线13用超声结合例如热塑的键合方法来连接。
与安置在基底衬底1的主表面的芯片安装区中的突块连接电极焊点2集成的导体3，存在并延伸于芯片安装区以及基底衬底1主表面的周边区域中。而且，与安置在基底衬底1的主表面的周边区域的突块连接电极焊点2集成的导体3，存在并延伸于基底衬底1主表面的周边区域中。亦即，在基底衬底1主表面的周边区域中，导体3被安置在半导体芯片1和引线连接电极焊点4之间的区域中。
上述半导体芯片10、导体3、引线连接电极焊点4以及引线13等，被密封在树脂密封体14中。树脂密封体14由环氧树脂制成，其中加有酚系硬化剂、硅橡胶和填充剂以降低应力。树脂密封体14用适合于大批量生产的转移注模方法来制作。转移注模方法使用装配有坩锅、浇口、门、腔等的压模。这是一种通过浇口和门从坩锅将树脂注入腔中并制作树脂密封体的方法。
各个电镀用的导体5被安置在基底衬底1的表面周边区域中的引线连接电极焊点4的外面。各个电镀导体5沿半导体芯片10的各边安置。一部分电镀导体5被安置在树脂密封体14里面，而其它部分被安置在树脂密封体外面。
如图2、图3和图5所示，绝缘层9被安置在排列于上述基底衬底1主表面的芯片安装区域中的各个突块连接电极焊点2的表面上方。每个突块连接电极焊点2的这些绝缘层9被分割并安置在基底衬底1主表面的芯片安装区域中。绝缘层9被分成几部分，以致被分散在基底衬底1主表面的芯片安装区域中。亦即，本实施例的半导体器件将绝缘层9分成在基底衬底1主表面的芯片安装区域的几部分，并将这一分割的绝缘层9安置在突块连接电极焊点2上。而且，本实施例中排列在突块连接电极焊点2上的绝缘层9的平面形状是圆形。
绝缘层9被安置在排列于上述基底衬底1的一个表面的周边区域的各个电镀用导体5的表面上。这些绝缘层9存在并沿基底衬底各边延伸，且被分成基底衬底1的各边。绝缘层9被分成基底衬底1周边区域中的一些点。亦即，本实施例的半导体器件将绝缘层9分成基底衬底1的一个表面的周边区域中的几个，并将这些绝缘层9排列在电镀用的导体5上。
排列在上述电镀用导体5上的那部分绝缘层9被安置在树脂密封体14里面，而其它部分被安置在树脂密封体14的外面。亦即，绝缘层9位于电镀用导体5与树脂密封体14之间。
如图5和图6所示，在上述基底衬底1的芯片安装区域中提供有排气孔7。这样，借助于在基底衬底1的芯片安装区域中提供排气孔7，在将粘接材料12涂于基底衬底1的一个表面的芯片安装区域并在其上安装半导体芯片10的粘接材料12的凝固过程中产生的出气就能够排出到外面。而且，由将半导体器件安装于安装衬底表面的表面安装时的热，或由半导体器件制作完成之后的环境测试的温度循环测试时的热在粘接材料12中产生的蒸汽也能够排出到外面。
在上述基底衬底1主表面的芯片安装区上，建有环绕出气孔7的挡板8。本实施例的挡板8由导电膜8A和安置在导电膜8A上的绝缘层9组成。
如图5所示，上述出气孔7被置于偏离基底衬底1的X方向(图中的水平方向)中心线P1和基底衬底1的Y方向(图中的垂直方向)中心线P2的位置。亦即，出气孔7被安置在偏离基底衬底1的中心。这样，在从基底衬底1的背面看半导体器件的情况下，可以清楚地看到出气孔7偏离基底衬底1的中心的安排，就像一个方向标志。由于方向能够像标志一样看清，故出气孔7可用作标志。
下面解释上述半导体器件制造工序中所用的框架结构。
框架结构20由单方向安置几个如图7(主要部分平面图)框架体21所规定的区域的矩阵框架结构组成，虽然不局限于此。膜的基底材料1A被安置在框架体21中指定的各个区域中。本实施例的膜基底材料1A预备了4个树脂密封区域22。亦即，安排了在框架体21中指定的每个区域中制作4个产品的膜基底材料1A。而且在树脂密封区22上制作了图5所示的导体层图形。
借助于在板材上进行腐蚀或冲压而制作上述框架体21。所用的板材含有例如铜系合金。
如图7和图8(沿图7中B-B线的剖面图)所示，上述膜基底材料1A用粘接材料固定在部分框架体21彼此相对处的二个粘接区域。在各个框架体21的粘接区域中预备有槽口23。这一槽口在框架结构20的纵向开出了一个特定的间隙，并配置了一些。这样，借助于在框架体21的粘接区预备槽口23，就可以释放由框架体21材料与膜基底材料1A之间的差别所引起的应力，可以抑制膜基底材料1A的翘曲畸变的形变。
下面用图9和图10(用来解释制造方法的主要部位剖面图)来解释上述框架结构20的制造方法。
首先，如图9(A)所示制备膜基底材料1A。膜基底材料1A由例如环氧系绝缘树脂或聚酰亚胺系绝缘树脂制成。然后，如图9(B)所示，将粘接材料30粘附到上述膜基底材料1A的一侧表面上。也可以不用粘接材料30，而用热塑方法来粘附。
然后，如图9(C)所示，在上述膜基底材料1A的突块连接区制作连接孔6的同时，在膜基底材料1A的芯片安装区制作出气孔7(未示出)。连接孔6和出气孔7用例如模压、激光等方法来制作。然后，如图9(D)所示，将金属箔(例如铜箔)31用连接材料30粘附到膜基底材料1A的一侧表面。在将金属箔31粘附到膜基底材料1A之后，可用压模或激光等方法来制作连接孔6和出气孔7。
然后，在膜基底材料1A的一个表面上制作突块连接电极焊点2的同时，由于如图9(E)所示上述金属箔31上进行了图形化，故可制作电镀用和引线连接用的导体3和电极焊点4等(未示出)。亦即，在此工序中制作了导体层图形。并制作了也环绕膜基底材料1A一个表面的芯片安装区中的出气孔7的周边的导电膜8A(亦未示出)。
然后如图10(F)所示，在包括上述导体层图形的膜基底材料1A的整个表面上制作膜厚度均匀的感光树脂膜32。在涂覆感光树脂之后，用网板印刷方法制作感光树脂膜32。然后在烘焙之后，完成照相印刷，亦即感光、显影和冲洗等工序，并如图10(G)所示，制作特定图形的绝缘层9。在此工序中，如图5所示，在导体层上安置分成几个部分的绝缘层9。在此工序中还制作了导电膜8A和含有排列在此导电膜8A上的绝缘层9的挡板8。在绝缘层9排列在膜基底材料1A的整个表面的情况下，由于膜基底材料1A、导体层和绝缘层9等材料特性之间的差别，使基底衬底1弯曲，并发生畸变等形变。但借助于如本实施例那样分割并安置绝缘层9，由于绝缘层9膨胀收缩和凝固所引起的应力被释放了，故可抑制基底衬底1的形变。
然后在不被上述绝缘层覆盖的导体层上，用电解电镀方法制作可能由电镀工序键合的电镀层(例如Au/Ni层、Au/Pd/Ni层、Pd/Ni层和Sn/Ni层等)。之后，借助于切割膜基底材料1A并用粘接材料24将其粘附到框架体21的粘接区，而制作图7所示的框架结构。在半导体器件制造工序(装备工序)中的膜基底材料1A的传送得到了改善，在框架体21的指定区域中如此地具有膜基底材料1A以致膜基底材料1A粘附于框架体21的粘附区的框架结构的制作改善了处理。
下面解释上述半导体器件的制造方法。
首先制备图7所示的框架结构20。框架结构20在框架体21的指定区域中有膜基底材料1A。树脂密封区22安置在膜基底材料1A中，并在此树脂密封区22中制作图5所示的导体层图形。
然后如图11(主要部位剖面图)所示，用粘接材料12将半导体芯片10安装在上述膜基底材料1A主表面的芯片安装区上。用多点浇注方法将粘接材料12涂于膜衬底1A一个表面的芯片安装区。可热固化的例如环氧系或聚酰亚胺系的绝缘树脂被用作粘接材料12。例如环氧系或聚酰亚胺系的热塑绝缘树脂也可用作粘接材料12。由于在本工序中在膜基底材料1A的芯片安装区提供了图7所示的出气孔，故粘接材料12固化时放出的气体能够放到外面。而且，由于在膜基底材料12一个表面的芯片安装区上建有环绕图6所示的出气孔7周围的挡板8，故可阻止和停止粘接材料12流入出气孔7。因此，可防止出气孔7被粘接材料12阻塞，并防止粘接材料12通过出气孔到达膜基底材料1A的背面。而且，即使半导体芯片10倾斜地安装，且粘接材料12的膜厚减小，由于绝缘层9安置在突块连接电极焊点2上，半导体芯片10也不会接触到突块连接电极焊点2。而且，即使安装时半导体芯片10倾斜且粘接材料12的膜厚减小，由于受到绝缘层9的支持，半导体芯片10也接触到绝缘层9而不接触到导体3。
然后如图12(主要部位剖面图)所示，上述半导体芯片的外端和膜元件1A的引线连接电极焊点4被引线13电连接。金丝被用作引线13。
然后将上述框架结构20置于注模。如图13(主要部位剖面图)所示，膜基底材料1A的树脂密封区22、半导体芯片10、引线13等被安置在制作于注模的上压模35A和下压模35B中的腔36中。如图14(主要部位剖面图)所示，注模装置配备了附属浇口(主浇口)37和凸块38(未示出)、每个坩锅安置了一个流入门和主浇口。坩锅通过各个主浇口、附属浇口37和流入门被连接到腔36。
上述注模装置的下压模35B有安置框架结构20的框架体21的台阶式部位39以及安置膜基底材料1A的台阶式部位40。亦即，框架结构20的框架体21被安置在下压模35B的台阶式部位39中，而框架结构20的膜基底材料1A被安置在下压模35B的台阶式部位40中。在框架体21-粘接材料24-膜基底材料1A的结构中完成了上压模35A和下压模35B的垂直匹配。
虽然未详细示出，但上述附属浇口37穿过安置有框架结构20的框架体21的台阶式部位39和安置有膜基底材料1A的台阶式部位40并存在于从框架结构20的内部到框架结构20的外部，且通过流入门连接到腔36。上述主浇口沿框架结构20外面的纵向存在并延伸，并连接到框架结构20外面的上述附属浇口37的一端。而且，为了方便粘附在附属浇口37内部的树脂而提供了突块38。此突块38位于制作在框架结构20和膜基底材料1A中的台阶式部位区。
然后将树脂片剂放入上述坩锅。此树脂片剂在转移模压设备的活塞中被压缩，并通过各个主浇口、附属浇口37和流入门，从坩锅馈入腔36。这样就制作了树脂密封体14。之后，从注模装置取出框架结构20。图15(主要部位平面图)示出了从注模装置取出的框架结构20的状态。在图15中，参考号41是粘附在模压装置附属浇口37中的附属浇口树脂，而参考号42是粘附在模压装置主浇口内部的主浇口树脂42。主浇口树脂42沿框架结构20的纵向存在。附属浇口树脂41存在于从框架体21的内部到框架体21的外部。图14示出了沿图15中C-C线的剖面图。
然后清除附属浇口粘附的树脂41和上述框架体21外部的主浇口粘附树脂42。上述框架体21内部的附属浇口树脂41被留下。图16(主要部位平面图)示出了这一状态。
然后如图17所示，通过制作在膜基底材料1A中的连接孔6，将突块电极15连接到突块连接电极焊点2的背面。突块电极15馈以例如衬底上的球，并借助于红外回熔等而连接。图18(外形结构图)示出了形成突块电极15之后的传送状态。在框架结构20堆叠到几层的情况下，在上一步提供的框架结构20的附属浇口粘附树脂41中，可确保上下步骤的框架结构20之间有间隙。因此，可保护在下一步骤的框架结构20中制造的半导体器件的突块电极15。由于能够实现框架结构20堆叠到几层的状态，故改善了框架结构20的转移。而且改善了半导体器件制造工艺的生产合理性。
然后，将膜基底材料1A切割成特定的形状(基底衬底形状)，就几乎完成了带有含膜基底材料1A的基底衬底1的半导体器件。之后，半导体器件就作为产品出厂。作为产品出厂的半导体器件被安装在印刷电路板的表面上。
而且，借助于在制作树脂密封体14之后切割膜基底材料1A，突块电极15可连接成单片状态。
而且，在制作绝缘层9之前的步骤中可进行电镀过程。在如本实施例那样在制作绝缘层9之后的步骤中完成电镀过程的情况下，如图19(主要部位剖面图)所示，电镀层33制作在突块连接电极焊点2、安置在基底衬底(膜基底材料1A)主表面周边区域的导体3和引线连接电极焊点4以及突块连接电极焊点2的背面上。亦即，电镀层33不制作在导体层与绝缘层9之间。在电镀过程于制作绝缘层9之前的步骤中完成的情况下，如图20(主要部位剖面图)所示，电镀层33制作在突块连接电极焊点2、导体3、引线连接电极焊点4、排列在基底衬底1(膜基底材料1A)主表面的芯片安装区外围的电镀用的导体5、以及突块连接电极焊点2的背面。亦即，电镀层33制作在导体层和绝缘层9之间。
如上所述，根据本实施例，得到了下列效果。
(1)借助于将绝缘层9分割并安置在导体层上，由于释放了绝缘层9膨胀收缩和凝固引起的应力，故可抑制基底衬底1(膜基底材料1A)的翘曲和畸变等变化。
而且，由于能够抑制基底衬底1的形变，故改善了半导体器件制造工艺的成品率。
(2)借助于制作环绕出气孔7周围的挡板8，可阻止并停止粘接材料12流入出气孔7。其结果是可防止出气孔7被粘接材料12阻塞，并防止粘接材料12向内进入膜基底材料1A的背面。
(3)在从基底衬底1的背面看半导体器件的情况下，可以看清出气孔7排列在偏离基底衬底中心的位置，就像一个标志。
(4)借助于用印刷的方法制作绝缘层9，比之粘接和制作形成片状绝缘层9的情况，可得到低成本的半导体器件。
而且由于能够自由设定绝缘层9的图形形状而改善了半导体器件的生产合理性。
(5)借助于膜基底材料1A排列在框架体21指定区域的框架结构20，改善了半导体器件制造工艺中膜基底材料1A的传送，并改善了对半导体器件制造的管理。
(6)由于能够防止粘附于膜基底材料1A和框架体21的树脂芒刺，故借助于在转移注模方法中用附属浇口路径中带有安装框架结构20的框架体21的台阶式部位39和安装框架结构20的膜基底材料1A的台阶式部位40的压模装置制作树脂密封体14，能够减少密封和切割时出现的外来物质。
(7)在框架结构20的框架体21中存在浇口树脂41的状态下，突块电极15被连接。倘若由此将框架结构20堆叠几层，则由于上部框架结构中的附属浇口树脂41可在上部框架结构20与下部框架结构20之间保持间隙，而能够保护制作在下部框架结构20中的半导体器件的突块电极15。因此，由于能够进入框架结构20堆叠成多层的状态而改善了框架结构20的传送。而且改善了半导体器件制造工艺的生产合理性。
(8)由于绝缘层9安置在突块连接电极焊点2上，故当在基底衬底1(膜基底材料1A)主表面的芯片安装区上添加粘接材料12并安装半导体芯片时，即使半导体芯片倾斜地安装且粘接材料12的膜厚度减小，半导体芯片10也不会接触到突块连接电极焊点2。因此，防止了突块连接电极焊点2与半导体芯片10的短路，亦即，也可防止导体层与半导体芯片10的短路。
而且，即使半导体芯片10倾斜地安装且粘接材料12的膜厚度减小，半导体芯片10也接触到绝缘层9并由此绝缘层9支持。结果就防止了导体3与半导体芯片10的短路，亦即，可防止导体层与半导体芯片10的短路。
(9)借助于在框架体21的粘接区中制备槽口，由于能够降低框架体21材料与膜基底材料1A之间的差别引起的应力而可抑制膜基底材料1A的翘曲和畸变等变化。
而且，虽然在上述实施例中解释的是在基底衬底1的芯片安装区中的突块连接电极焊点2上制作绝缘层9的例子，但绝缘层9也可以制作在导体3上。而且，绝缘层9可以制作在突块连接电极焊点2以及导体3上。在这些情况下，当在基底衬底1(膜基底材料1A)主表面的芯片安装区上添加粘接材料12并安装半导体芯片10时，同上述实施例一样，即使半导体芯片倾斜地安装且粘接材料12的膜厚度减小，也可防止突块连接电极焊点2与导体3短路，亦即，可防止导体层与半导体芯片10短路。
而且，如图21(半导体器件的主要部位剖面图)和图22(基底衬底的平面图)，绝缘层9可在基底衬底1上分割，以便在作为基底衬底1主表面周边区且制作在半导体芯片10与引线连接电极焊点4之间区域的导体3上安装绝缘层9。此时，由于引线13不接触到导体3，故可防止靠近电连接于引线13的导体3与这些引线13短路，亦即，可防止导体层与引线13短路。
而且，如图23(基底衬底平面图)和图24(半导体器件的主要部位剖面图)所示，绝缘层9被分割成基底衬底1上的各个导体层。然后可在除引线连接电极焊点4之外的导体层的整个范围(突块连接电极焊点2、导体3和电镀用的导体5)内制作绝缘层9。此时，即使外来的导电材料在半导体器件制造过程中粘附在各个导体层之间，由于外来导电材料不接触到导体层，故仍可防止各个导体层之间的短路。
而且，如图25(基底衬底平面图)所示，绝缘层9可在基底衬底1上被分割，且这些被分割的绝缘层9能够排列在导体层上。各个绝缘层9制作成方形，有指定的间隙，排列成矩阵。
而且，如图26(基底衬底的平面图)所示，绝缘层9可在基底衬底1上被分割，且这些被分割的绝缘层9能够排列在导体层上。各个绝缘层9制作成长板形，有间隙地径向排列。
而且，虽然在上述实施例中解释的是安置在基底衬底1背面的球形突块电极例子15，但柱形突块之类的伸出电极甚至由球键合形成的电极，也可用作本发明的电极。
虽然已根据上述实施例具体解释了本发明，但本发明不仅仅局限于上述实施例，而是可以在不超越本发明的要旨的范围内对其做各种改变。
下面解释一下由本申请所公开的本发明所获得的代表性效果。
在带有含柔性膜的基底衬底的半导体器件中，能够抑制基底衬底的形变(翘曲和畸变)。
在带有含柔性膜的基底衬底的半导体器件中，能够抑制基底衬底的形变，并可防止基底衬底的导体与半导体芯片短路。
在带有含柔性膜的基底衬底的半导体器件中，能够抑制基底衬底的形变，并可防止基底衬底的导体层与引线短路。

Claims (20)

1、半导体器件，包括：
由薄膜制成的基底衬底，具有第一表面和面对上述第一表面的第二表面；
在上述基底衬底的上述第一表面上形成的多个导体层；
用粘接材料安装在上述基底衬底的上述第一表面上且安置于上述多个导体层上的半导体芯片，上述半导体芯片具有多个半导体元件和形成于其主表面上的多个外部端子；
形成于上述导体层和上述半导体芯片之间的多个绝缘层；
与上述外部端子和上述导体层分别电连接的多个键合引线；
安置于上述第二表面上且电连接于上述导体层的多个突块电极；以及
密封上述半导体芯片、上述导体层和上述键合引线的树脂元件；
其中上述多个绝缘层在安装上述半导体芯片区域的平面视图中彼此隔开。
2、权利要求1的半导体器件，还包括：
分布于上述区域中在上述多个导体层各端上形成的多个岛焊点，
其中各上述绝缘层覆盖各上述岛焊点。
3、权利要求2的半导体器件，还包括：
分布于上述区域中在上述多个导体层各端上形成的多个岛焊点，
其中各上述绝缘层形成于各上述岛焊点上以便覆盖各上述岛焊点的一部分。
4、权利要求1的半导体器件，其特征在于：上述基底衬底由绝缘环氧树脂制成。
5、权利要求1的半导体器件，其特征在于：上述基底衬底由聚酰亚胺绝缘树脂制成。
6、权利要求1的半导体器件，其特征在于：上述基底衬底具有从上述第一表面到达上述第二表面的多个连接孔，
上述连接孔的一端电连接于一个上述导体层，上述连接孔的另一端电连接于一个上述突块电极。
7、权利要求1的半导体器件，还包括：
上述半导体芯片和连接于上述导体层的上述引线之间的绝缘层，上述绝缘层分布于上述半导体芯片周围。
8、权利要求1的半导体器件，还包括：
形成于上述半导体芯片外围区域的多个电镀用导体层，各上述电镀用导体层与上述多个导体层连续延伸并到达上述基底衬底的每一边；
在上述半导体芯片的上述外围区域处形成于上述基底衬底的上述第一表面上的多个绝缘层，用来覆盖上述多个电镀用导体层。
9、权利要求8的半导体器件，其特征在于：上述绝缘层分割成对应于上述基底衬底每一边的多个。
10、权利要求1的半导体器件，其特征在于：上述绝缘层被安置成使上述半导体芯片的背面不直接接触上述导体层。
11、半导体器件，包括：
由薄膜制成的基底衬底，具有第一表面和面对上述第一表面的第二表面；
在上述基底衬底的上述第一表面上形成的多个导体层和形成于上述半导体芯片外围区域的多个电镀用导体层，各上述电镀用导体层与上述多个导体层连续延伸并到达上述基底衬底的每一边；
用粘接材料安装在上述基底衬底的上述第一表面上且安置于上述多个导体层上的半导体芯片，上述半导体芯片具有多个半导体元件和形成于其主表面上的多个外部端子；
在上述半导体芯片的上述外围区域处形成于上述基底衬底的上述第一表面上的多个绝缘层，用来覆盖上述多个电镀用导体层；
分别电连接于上述外部端子和上述导体层之间的多个键合引线；
安置于上述第二表面上且电连接于上述导体层的多个突块电极；以及
其中密封有上述半导体芯片、上述导体层和上述键合引线的树脂元件；
其中上述多个绝缘层在平面视图中彼此隔开。
12、权利要求11的半导体器件，其特征在于：上述基底衬底的平面图形为方形，上述绝缘层在上述基底衬底的角部区域被分割。
13、权利要求11的半导体器件，其特征在于：上述基底衬底的平面图形为方形，上述绝缘层被分割成对应于上述基底衬底每一边的多个。
14、权利要求11的半导体器件，其特征在于：上述基底衬底由绝缘环氧树脂制成。
15、权利要求11的半导体器件，其特征在于：上述基底衬底由聚酰亚胺绝缘树脂制成。
16、权利要求11的半导体器件，其特征在于：上述基底衬底具有从上述第一表面到达上述第二表面的多个连接孔，
上述连接孔的一端电连接于一个上述导体层，上述连接孔的另一端电连接于一个上述突块电极。
17、权利要求11的半导体器件，还包括：
上述半导体芯片和连接于上述导体层的上述引线之间的绝缘层，上述绝缘层分布于上述半导体芯片周围。
18、权利要求11的半导体器件，还包括：
在安装有上述半导体芯片的区域中形成于上述导体层和上述半导体芯片之间的多个绝缘层；
其中的上述多个绝缘层在平面视图中彼此隔开。
19、权利要求18的半导体器件，其特征在于：形成于上述导体层和上述半导体芯片之间的上述绝缘层被安置成使上述半导体芯片的背面不直接接触上述导体层。
20、权利要求11的半导体器件，其特征在于：用上述树脂元件密封上述绝缘层使得部分上述绝缘层与上述树脂元件彼此重叠。
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Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154658A (ja) 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
DE19905055A1 (de) * 1999-02-08 2000-08-17 Siemens Ag Halbleiterbauelement mit einem Chipträger mit Öffnungen zur Kontaktierung
JP2000236040A (ja) * 1999-02-15 2000-08-29 Hitachi Ltd 半導体装置
JP4151164B2 (ja) * 1999-03-19 2008-09-17 株式会社デンソー 半導体装置の製造方法
JP2001024085A (ja) * 1999-07-12 2001-01-26 Nec Corp 半導体装置
JP3521325B2 (ja) * 1999-07-30 2004-04-19 シャープ株式会社 樹脂封止型半導体装置の製造方法
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
US6257857B1 (en) * 2000-01-31 2001-07-10 Advanced Semiconductor Engineering, Inc. Molding apparatus for flexible substrate based package
JP3701542B2 (ja) * 2000-05-10 2005-09-28 シャープ株式会社 半導体装置およびその製造方法
US6541844B2 (en) * 2000-07-17 2003-04-01 Rohm Co., Ltd. Semiconductor device having substrate with die-bonding area and wire-bonding areas
US6563299B1 (en) * 2000-08-30 2003-05-13 Micron Technology, Inc. Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer
KR100351926B1 (ko) * 2000-11-08 2002-09-12 앰코 테크놀로지 코리아 주식회사 비·지·에이 패키지
US6960824B1 (en) * 2000-11-15 2005-11-01 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless chip carrier
US20020117753A1 (en) * 2001-02-23 2002-08-29 Lee Michael G. Three dimensional packaging
KR100868419B1 (ko) * 2001-06-07 2008-11-11 가부시끼가이샤 르네사스 테크놀로지 반도체장치 및 그 제조방법
JP4701563B2 (ja) * 2001-08-23 2011-06-15 日本テキサス・インスツルメンツ株式会社 半導体チップ搭載基板及びそれを用いた半導体装置
US6957111B2 (en) * 2001-08-24 2005-10-18 Koninklijke Philips Electronics N.V. Automated system for cooking and method of use
EP1915040A3 (en) 2001-09-28 2008-04-30 Ibiden Co., Ltd. Printed wiring board and printed wiring board manufacturing method
US6657870B1 (en) * 2001-10-01 2003-12-02 Lsi Logic Corporation Die power distribution system
JP2003204009A (ja) * 2001-11-01 2003-07-18 Sanyo Electric Co Ltd 半導体装置
SG107584A1 (en) * 2002-04-02 2004-12-29 Micron Technology Inc Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such masks
US7368391B2 (en) 2002-04-10 2008-05-06 Micron Technology, Inc. Methods for designing carrier substrates with raised terminals
US7799611B2 (en) * 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8236612B2 (en) * 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
KR100958400B1 (ko) 2002-06-05 2010-05-18 가부시끼가이샤 르네사스 테크놀로지 반도체장치
JP3580803B2 (ja) * 2002-08-09 2004-10-27 沖電気工業株式会社 半導体装置
US20040058478A1 (en) * 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
DE10247959A1 (de) * 2002-10-15 2004-04-29 Bock 1 Gmbh & Co. Linear-Schiebeführung insbesondere für zueinander verschiebbare Komponenten von Bürostühlen
US7109573B2 (en) * 2003-06-10 2006-09-19 Nokia Corporation Thermally enhanced component substrate
US6992380B2 (en) * 2003-08-29 2006-01-31 Texas Instruments Incorporated Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area
TWI228304B (en) * 2003-10-29 2005-02-21 Advanced Semiconductor Eng Method for manufacturing ball grid package
JP2005236176A (ja) * 2004-02-23 2005-09-02 Torex Semiconductor Ltd 電極パッケージ及び半導体装置
DE102004012818B3 (de) 2004-03-16 2005-10-27 Infineon Technologies Ag Verfahren zum Herstellen eines Leistungshalbleiterbauelements
DE112004002862T5 (de) * 2004-05-20 2007-04-19 Spansion Llc, Sunnyvale Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
US7453157B2 (en) * 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
JP2006073586A (ja) * 2004-08-31 2006-03-16 Renesas Technology Corp 半導体装置の製造方法
TWI240393B (en) * 2004-09-29 2005-09-21 Siliconware Precision Industries Co Ltd Flip-chip ball grid array chip packaging structure and the manufacturing process for the same
MY136179A (en) * 2004-10-23 2008-08-29 Freescale Semiconductor Inc Packaged device and method of forming same
US7355283B2 (en) * 2005-04-14 2008-04-08 Sandisk Corporation Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging
JP2006344824A (ja) * 2005-06-09 2006-12-21 Nec Electronics Corp 半導体装置および半導体装置の製造方法
DE102006015222B4 (de) * 2006-03-30 2018-01-04 Robert Bosch Gmbh QFN-Gehäuse mit optimierter Anschlussflächengeometrie
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8310060B1 (en) * 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US7863761B2 (en) * 2006-08-03 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with molding vents
WO2008057770A2 (en) * 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
KR100829385B1 (ko) * 2006-11-27 2008-05-13 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US8937372B2 (en) * 2007-03-21 2015-01-20 Stats Chippac Ltd. Integrated circuit package system with molded strip protrusion
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
JP5353153B2 (ja) * 2007-11-09 2013-11-27 パナソニック株式会社 実装構造体
US7976769B2 (en) * 2007-11-30 2011-07-12 Corning Incorporated Method of manufacturing a ceramic honeycomb structure
TWI428995B (zh) 2008-10-20 2014-03-01 United Test & Assembly Ct Lt 板上縮小封裝
US9054111B2 (en) * 2009-04-07 2015-06-09 Freescale Semiconductor, Inc. Electronic device and method of packaging an electronic device
US8288869B2 (en) * 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US8367473B2 (en) * 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
TW201041105A (en) * 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
US8384114B2 (en) 2009-06-27 2013-02-26 Cooledge Lighting Inc. High efficiency LEDs and LED lamps
TWI425603B (zh) * 2009-09-08 2014-02-01 Advanced Semiconductor Eng 晶片封裝體
JP5542399B2 (ja) * 2009-09-30 2014-07-09 株式会社日立製作所 絶縁回路基板およびそれを用いたパワー半導体装置、又はインバータモジュール
TWI405273B (zh) * 2009-10-13 2013-08-11 Unimicron Technology Corp 封裝結構之製法
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8786062B2 (en) * 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8653539B2 (en) 2010-01-04 2014-02-18 Cooledge Lighting, Inc. Failure mitigation in arrays of light-emitting devices
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
EP2589082B1 (en) 2010-06-29 2018-08-08 Cooledge Lighting Inc. Electronic devices with yielding substrates
TW201225238A (en) * 2010-07-26 2012-06-16 Unisem Mauritius Holdings Ltd Lead frame routed chip pads for semiconductor packages
US8410604B2 (en) * 2010-10-26 2013-04-02 Xilinx, Inc. Lead-free structures in a semiconductor device
US9627337B2 (en) 2011-03-31 2017-04-18 Novatek Microelectronics Corp. Integrated circuit device
TWI424544B (zh) * 2011-03-31 2014-01-21 Novatek Microelectronics Corp 積體電路裝置
US20130241058A1 (en) * 2012-03-16 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wire Bonding Structures for Integrated Circuits
US9768102B2 (en) * 2012-03-21 2017-09-19 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with support structure and method of manufacture thereof
US9231178B2 (en) 2012-06-07 2016-01-05 Cooledge Lighting, Inc. Wafer-level flip chip device packages and related methods
CN103594425B (zh) * 2012-08-15 2016-06-22 长华电材股份有限公司 软性基材的封装工艺及其结构
US8822327B2 (en) 2012-08-16 2014-09-02 Infineon Technologies Ag Contact pads with sidewall spacers and method of making contact pads with sidewall spacers
TWI546923B (zh) * 2013-02-06 2016-08-21 矽品精密工業股份有限公司 封裝基板、半導體封裝件及其製法
US20150049443A1 (en) * 2013-08-13 2015-02-19 Infineon Technologies Ag Chip arrangement
CN103779286A (zh) * 2014-01-26 2014-05-07 清华大学 一种封装结构、封装方法及在封装方法中使用的模板
PL3180117T3 (pl) * 2014-08-13 2021-02-08 Ozbekoglu Ith. Ihc. Ins. Muh. Ltd. Ti. Układ do analizy i ponownego użycia odpadowych cieczy
CN107079541B (zh) * 2014-11-14 2020-01-21 琳得科株式会社 密封片材、电子器件用部件和电子器件
DE102014017535B4 (de) 2014-11-26 2018-10-04 Mühlbauer Gmbh & Co. Kg Identifikationsdokument mit Informationen aus thermochromer Tinte und Verfahren zum Herstellen eines ldentifikationsdokuments sowie Verfahren zum Verifizieren eines ldentifikationsdokuments
TWI641087B (zh) * 2015-12-28 2018-11-11 矽品精密工業股份有限公司 電子封裝件及封裝用之基板
JP6674284B2 (ja) * 2016-02-29 2020-04-01 株式会社フジクラ 実装構造及びモジュール
CN106920779B (zh) 2017-03-09 2019-09-06 三星半导体(中国)研究开发有限公司 柔性半导体封装件的组合结构及其运输方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR694965A (fr) 1930-05-03 1930-12-10 Perfectionnements aux hameçons destinés à la pêche
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
KR0134902B1 (ko) * 1991-07-08 1998-04-20 다니엘 케이. 니콜스 칩 캐리어 패키지 및 집적 회로 패키지
US5218234A (en) * 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
DE69225896T2 (de) * 1992-12-15 1998-10-15 Sgs Thomson Microelectronics Träger für Halbleitergehäuse
JPH0714976A (ja) * 1993-06-24 1995-01-17 Shinko Electric Ind Co Ltd リードフレーム及び半導体装置
TW368745B (en) * 1994-08-15 1999-09-01 Citizen Watch Co Ltd Semiconductor device with IC chip highly secured
JP2595909B2 (ja) * 1994-09-14 1997-04-02 日本電気株式会社 半導体装置
JP3414017B2 (ja) * 1994-12-09 2003-06-09 ソニー株式会社 半導体装置
JP2561448B2 (ja) * 1994-12-28 1996-12-11 九州日本電気株式会社 ディスペンスノズル
JP3471111B2 (ja) * 1995-03-20 2003-11-25 三菱電機株式会社 半導体装置
US5620927A (en) * 1995-05-25 1997-04-15 National Semiconductor Corporation Solder ball attachment machine for semiconductor packages
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
JP3263288B2 (ja) * 1995-09-13 2002-03-04 株式会社東芝 半導体装置
JP3176542B2 (ja) * 1995-10-25 2001-06-18 シャープ株式会社 半導体装置及びその製造方法
US5756380A (en) * 1995-11-02 1998-05-26 Motorola, Inc. Method for making a moisture resistant semiconductor device having an organic substrate
JPH09148481A (ja) * 1995-11-24 1997-06-06 Hitachi Ltd 半導体装置およびその製造方法
JP3345541B2 (ja) * 1996-01-16 2002-11-18 株式会社日立製作所 半導体装置及びその製造方法
JP3170199B2 (ja) * 1996-03-15 2001-05-28 株式会社東芝 半導体装置及びその製造方法及び基板フレーム
CA2198305A1 (en) * 1996-05-01 1997-11-02 Yinon Degani Integrated circuit bonding method and apparatus
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6144101A (en) * 1996-12-03 2000-11-07 Micron Technology, Inc. Flip chip down-bond: method and apparatus
JPH10185724A (ja) * 1996-12-26 1998-07-14 Matsushita Electric Works Ltd 半導体圧力センサ
JPH10199931A (ja) * 1997-01-07 1998-07-31 Toshiba Corp 半導体装置、半導体装置の製造方法及び半導体装置の製造装置
KR100251859B1 (ko) * 1997-01-28 2000-04-15 마이클 디. 오브라이언 가요성 회로 기판 스트립을 이용하여 제조되는 볼그리드 어레이반도체 패키지의 싱귤레이션 방법
FR2764111A1 (fr) * 1997-06-03 1998-12-04 Sgs Thomson Microelectronics Procede de fabrication de boitiers semi-conducteurs comprenant un circuit integre
JPH1154658A (ja) * 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US6157085A (en) * 1998-04-07 2000-12-05 Citizen Watch Co., Ltd. Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate
JP3310617B2 (ja) * 1998-05-29 2002-08-05 シャープ株式会社 樹脂封止型半導体装置及びその製造方法
US6490166B1 (en) * 1999-06-11 2002-12-03 Intel Corporation Integrated circuit package having a substrate vent hole
JP3827520B2 (ja) * 2000-11-02 2006-09-27 株式会社ルネサステクノロジ 半導体装置
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法

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