TW201225238A - Lead frame routed chip pads for semiconductor packages - Google Patents

Lead frame routed chip pads for semiconductor packages Download PDF

Info

Publication number
TW201225238A
TW201225238A TW100125855A TW100125855A TW201225238A TW 201225238 A TW201225238 A TW 201225238A TW 100125855 A TW100125855 A TW 100125855A TW 100125855 A TW100125855 A TW 100125855A TW 201225238 A TW201225238 A TW 201225238A
Authority
TW
Taiwan
Prior art keywords
package
array
platforms
semiconductor device
side surface
Prior art date
Application number
TW100125855A
Other languages
Chinese (zh)
Inventor
Antonio Romarico Santos San
Anang Subagio
Shafidul Islam
Original Assignee
Unisem Mauritius Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/843,183 priority Critical patent/US8304864B2/en
Application filed by Unisem Mauritius Holdings Ltd filed Critical Unisem Mauritius Holdings Ltd
Publication of TW201225238A publication Critical patent/TW201225238A/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Abstract

A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages.

Description

201225238 VI. Description of the Invention: [Technical Field] The present invention relates to a lead frame for a molded plastic package of the type used for encapsulation or a plurality of semiconductor devices. More specifically, the lead frame is formed from a single-conducting substrate by a sequential metal removal process that selectively patterns the outer wire ends, routing circuitry, and internal wire ends. [Prior Art] One type of package for mounting a semiconductor device is a molded plastic package. The semiconductor device is loaded into a polymer resin block that provides environmental protection. Electrical signals are transmitted between the semiconductor device and an external circuit, such as a printed circuit board ("PCB"), by a plurality of different conductive structures. In a wire package, the conductive lead frame has an inner wire end and an opposite outer wire end Usually, the lead frame configuration is formed by chemical money engraving, and the spacing of the inner wire ends is limited to the consideration of the cost to the lead frame at a distance from the semiconductor device and by a small distance. Diameter wire = conductance = input/output port connected to the semiconductor device. The wire extends outward from the inner wire end to terminate at the outer wire end of the contact pad soldered to the external circuit. This type of wire package occupies The footprint (the surface area on printed circuit boards or other external structures) is significantly larger than the footprint of semiconductor devices. In the semiconductor packaging industry, it is necessary to minimize the footprint of the semiconductor package to obtain a wafer-scale package (where the package occupies) The target is no larger than the area occupied by the semiconductor device. In the wire package, the bonding at the inner wire (four) There is always a considerable difference from the spacing of the platform 157702.doc 201225238 outside the package for board attachment. The bond pad spacing tends to achieve finer geometry to maximize the use of the area, while the board The step spacing remains widely spaced for PCB routing and soldering. The lead frame fanout from the wafer bond pad pitch to the external platform pitch results in a much larger footprint than the semiconductor device. This is a wafer scale package (" The concept of csp") is inconsistent with the demand. The trend towards CSP has driven the development of "array" packages with external platforms configured as grid arrays with appropriate board attachment pitches. This grid array is constrained to the wafer. The package is required to be routed to the desired platform position by using an interface (often referred to as an interposer). As disclosed in U.S. Patent No. 6,477,034, the insert is multi-layered (usually thin). 2 or 3 layers of flexible or similar substrate with energized pitch fanout and routing. U.S. Patent No. 6,477, No. 34 The manner is incorporated herein. Inserts are not preferred. In addition to the major cost additions, additional processing steps are required during package assembly. Ball Grid Array ("BGA") packages use printed circuit board substrates for circuit routing It is also used to support platform relocation within application limits, that is, to compromise the technical limitations of routing features/capabilities and board attachment soldering limitations. Many BGA substrates utilize through-holes for enabling dense package and platform positioning. Multi-layer configuration. However, the use of such BGA substrates and the addition of vias add significant cost and processing steps. A method for fabricating leadframes for quad flat no-wire ("QFN") packages is disclosed in In U.S. Patent No. 6,498,099 to McLeUan et al. A semiconductor device is bonded to the partially defined pad attachment and the semiconductor device is electrically interconnected to the partially defined inner wire end by a wire bond or the like. The semiconductor device, the partially defined pad attachment, the partially defined inner conductor, and the wire bond are then encapsulated in a polymeric molding resin. The etched first side of the conductive substrate to electrically isolate the pad attachment from the inner wire end and define the outer wire end. Another method for making a QFN package is disclosed in commonly-owned U.S. Patent No. 6,812,552. And the entire disclosure of this patent is incorporated herein by reference. The application issued as US Patent No. 6,812,552 is disclosed as US Patent Application Publication No. A1 on January 30, 2003. However, it is still required to manufacture internal wire ends and external parts with accurate positioning. Wire ends and methods of wafer scale packaging and other semiconductor packages that do not require complicated manufacturing steps or routing circuits that do not include complementary interposer circuits. In addition, there is still a need for a package manufactured by this method. SUMMARY OF THE INVENTION According to a first embodiment of the present invention, there is provided a package for loading at least a conductor device, including a first side and a second side having opposite sides. Flattening the first side surface and each of the 4's of the platforms; and the surface of the crucible includes a first side surface: a knife that is adapted to be coupled to an external circuit and The second side of the LED lead frame has a flat second side surface and a 157702.doc 201225238 - wafer attachment site array. Each of the wafer attachment sites includes a portion of the second side surface. The wafer attachment sites are configured in a second pattern and are directly electrically interconnected to the input/output pads on the semiconductor device. The plurality (4) isolated routing circuitry is located on the second side of the leadframe. - having a surface comprising a portion of the second side surface and coplanar with the wafer attachment (four), each of the routing circuits having an individual combination of an array of electrical interconnection platforms and an array of wafer attachment sites. And these: the attachment point of the sheet is from the single conductive junction Forming. The first molding compound disposed between the first side of the lead frame and the individual platforms has a surface including a portion of the first side surface. The second molding compound encapsulates the semiconductor device, the array of wafer attachment sites, and Routing circuit. According to another embodiment of the present invention, a package for mounting at least one semiconductor device has a leadframe, a wafer attachment site, and a routing circuit as described above, but the surface of the first molding compound The recess is recessed relative to the flat first side surface. The platform thus has a stand-off distance between the package and the external printed circuit board. According to an additional embodiment of the present invention, a package for mounting at least one semiconductor device There is a leadframe, a wafer attachment site, and a routing circuit as described with respect to the first embodiment, except that the wafer attachment sites are not coplanar with the routing circuitry and instead protrude from the second side surface. The increased spacing between the routing circuits facilitates the flow of the second molding compound on the underside of the device. According to another embodiment of the invention, a loading The package of at least one semiconductor device has a wire 157702.doc 201225238 shelf, a wafer attachment site, and a routing circuit as described above with respect to the first embodiment, except that the surface of the first molding compound is opposite to the flat first side surface The recesses are such that the platform has a avoidance distance' and the wafer attachment sites are not coplanar with the routing circuitry and instead protrude from the second side surface. According to yet another embodiment of the present invention, a package is provided that includes opposing a lead frame on the first side and the second side. The first side of the lead frame has a flat first side surface and a flat (four) column, and a surface of each of the platforms includes a portion of the first side surface; The platforms are adapted to be coupled to an external circuit and configured in a first pattern. The second side of the leadframe has a flat second side surface (having a die pad) and an array of wire bonding sites. Each of the wire bonding sites can include a portion of the second side surface. The wire bonding sites are configured in a second pattern and are directly electrically interconnected to the input/output pads on the semiconductor device. A plurality of electrically isolated routing circuits coplanar with the die are located on the second side of the leadframe. Each of the routing circuits has a linguistic sign - also a surface having a portion of the first side surface of the 匕 3 and coplanar with the wire junction site 'each of the routing circuits Individual combinations of electrical interconnect platform arrays and wire bond site arrays. The platforms and the bonding sites are formed from a single conductive structure. The first molding compound disposed between the first side of the lead frame and the individual platforms has a surface including a portion of the first side surface. The second molding compound encapsulates the semiconductor device, the crystal pad, the wire bonding site array, and the routing circuit. In accordance with an additional embodiment of the present invention, a package includes a leadframe and wire bond site as just described above but with a non-conductive layer on the second side of the leadframe rather than a die. A semiconductor device is disposed on the non-conductive layer 157702.doc 201225238 and forms a wire bond connection to the device. At least one of the routing circuits extends below the non-conductive layer, and at least one of the platforms is located on the first side surface of the __ portion thereof (corresponding to a portion of the second side surface covered by the semiconductor device) The at least one electrical conductor extends from the first side surface to the second side surface under the semiconductor device and is electrically connected to a routing circuit extending below the non-conductive layer. According to these embodiments, it is easy to provide a wafer scale package and a package for encapsulating a plurality of devices. In addition, the lead frame can be formed from a single conductive structure and supported by a first molding compound. This results in very few problems with the lead frame being stable and the loss of heart and coplanarity. The details of various embodiments of the invention are set forth in the drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and appended claims. The same reference numerals and names in the various drawings indicate the same elements. Figure 1 illustrates, in cross-section, a conductive substrate 1 that will be patterned into a leadframe for routing electrical signals in a semiconductor package for mounting at least a semiconductor device. Conductive substrate 10 can be formed from any suitable electrically conductive material, and is preferably formed from a copper or copper based alloy. In the case of a steel-based alloy, it means that the conductive substrate ίο contains more than 50% by weight of copper. The conductive substrate has a thickness from (MG mm to 0.25 Å to GG (four)), and is usually in the form of a substrate attached by a single-pass (usually a step after the manufacturing process) Representation of flip chip package with wafer attachment posts 157702.doc -9-201225238 Referring to Figure 2B, the first side 12 of the conductive substrate 10 is partially patterned to form an array of platforms 14 separated by channels 16. The surface of each of the platforms 14 above one side includes a portion of the flat first side surface of the leadframe. The channels can be formed by any controlled subtractive process such as chemical etching or laser ablation. The portion of the first surface that is intended to form the land can be coated with a chemical resist and expose the first surface to a suitable etchant for a time effective to form the channel 16. Typically, the channel 16 will have a conductive substrate. a depth of 40% to 99% of the thickness, and preferably, the channel depth will be 45°/. to 65% of the thickness of the conductive substrate. As shown in FIG. 2A, the platform 14 is adapted to be bonded to an external circuit. (such as matching external printing Formed by an array pattern of bond pads on the circuit board. To facilitate attachment to an external circuit board by soldering, the platform 14 can be surface trimmed or plated with various solderable materials (such as solder paste, Sn, Ag, Au, NiAu, etc.) The first molding compound is then placed in the channel 16. As shown in Figure 3B, the first polymer molding resin 18 preferably fills the channel 16 flush such that the first side of the platform 14 becomes Adapted to a wireless platform bonded to an external circuit. In this embodiment, the surface of the platform 14 is coplanar with the surface of the molding compound 18 and the surfaces comprise a flat first side surface of the leadframe. The first polymer molding resin is added to a depth slightly smaller than the depth of the channel such that the surface of the molding compound is recessed with respect to the first side surface and the platform has a avoidance distance between the package and the external printed circuit board. Preferably, the first molding resin 18 is non-conductive, and is preferably a polymer molding resin (such as epoxy) having a flow temperature in the range of 157702.doc •10·201225238 250° C. to 300° C. Resin Alternatively, the first molding resin can be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite used to attach the leadframe to a ceramic substrate in a CERPAK or CERDIP package, which can be assembled by a leadframe supplier (eg, The leadframe precursor 20) illustrated in Figure 3A is supplied to a package assembly factory for further processing, or the leadframe manufacturer can continue the process. As shown in Figure 4, the patterned conductive substrate 1 is then opposed. The second side 22 is formed to form wafer attachment sites 24 that are formed to be effectively electrically interconnected directly to an array of input/output ports on the semiconductor device. Patterning can be performed using any suitable method Wafer attachment sites 24, such as chemical etching or laser ablation. Preferably, the chemical resistant material is applied to the pattern of the array and then the second side is exposed to the etching solution to effectively remove sufficient material to define the time of wafer attachment site 24. As illustrated in Figures 5A and 5B, the second side 22 is further patterned to form routing circuitry 26 that electrically interconnects the wafer attachment sites 24 with the platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wafer attachment sites, routing circuits, and platforms. The routing circuits 26 each have a surface comprising a portion of the flat second side surface and an individual combination of an array of electrically interconnected platforms 14 and an array of wafer attachment locations 24. In this embodiment, each of the wafer attachment sites 24 protrudes from the second side surface of the leadframe. Semiconductor device 28 is directly attached and electrically interconnected to the leadframe at wafer attachment site 24, as shown in Figures 6A and 6B. By "direct," it is meant that the interconnection is by flip chip method without the use of an intervening wire bond or tape-and-tape type (TAB) tape. The wafer attachment sites 24 are disposed opposite the input/output ports of the device 28 and are interconnected by interconnects 30. Suitable interconnects 3 include solder having a primary component selected from the group consisting of gold, tin, and marine (having a melting temperature in the range between 180 ° C and 240 ° C). In this embodiment the wafer attachment post 34 extends upwardly from the routing circuit 26; the lower side of the device 28 is thus located a distance 32 above the surface of the routing circuit 26. The spacing 32 between the semiconductor device 28 and the routing circuitry 26 is selected to promote flow of the second molding compound, as described in more detail below. This spacing is typically at least 25 microns; in this embodiment the 'interval is at least 75 microns. In other embodiments, the spacing can range from about 100 microns to about 150 microns. Preferably, 50% to 75% (height) of the spacing 32 is due to the wafer attachment post 34, and 50%-25°/〇 (height) of the spacing is due to the interconnect 3〇. Referring to Figure 7, a second molding compound 36 then encapsulates the semiconductor device 28, the wafer attachment site 24, and the routing circuitry 26 to complete the package 38 for loading at least half of the conductor device. Like the first molding compound μ, the second molding compound 36 is non-conductive and preferably has 250. (: to a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 300. Or, the second molding compound may also be a low-temperature heat-resistant glass composite (such as for attaching a lead frame) A low temperature pair of hot glass composites to a ceramic substrate in a CERPAK or CERDIP package. The combination of wafer attachment sites 24, wafer attachment posts 34, routing circuitry 26, and platform 14 is referred to as a "redistribution leadframe" or RDLF. The RDLFs are formed from a single conductive substrate that is a unitary structure. In the package embodiment shown in Figure 7, the array of platforms 14 occupies a larger surface than the array of wafer attachment sites 24 157702.doc • 12· 201225238 product This type of package is a QFN (Four Flat Flat Wireless) flip chip package. The advantages of the package 38 of the present invention over the prior QFN flip chip package are: a. The routing circuit is supported flat on the first molding compound, and Different from the flatness problem associated with the circuit traces that are stuck or blocked; b. The coplanarity problem of the wire fingers disappears when supported; C. The Ba interconnection is stable and suitable for all Package size and format; d. There are no exposed circuit traces or routing circuitry under the package (exposed circuit traces or routing circuitry in the etched wireless flip chip package); e. Adapt to any wafer pad location and spacing; f. Close to 100% good Rate and quality consistency; g. Eliminate the need for inserts' and adapt to existing wafer designs; h. Package areas can be gathered and mixed interconnects (wire bonds, aluminum ultrasonic joints, flip chip attachments, etc.) i. is suitable for encapsulating multiple wafers and surface-adhesive passive electronic components; j. no circuit traces or routing circuits are exposed at the bottom of the package, only the non-wireless platform with or without the desired avoidance distance; k. The package can be very thin because it does not require a separate insert; and the package provides a heat resistant pad that is exposed to the bottom of the package, such as a die pad that can be attached to a ground or heat resistant bump on the wafer. Additional RDLF package Figure 8 illustrates the RDLF (Redistribution Lead Frame Package) of the present invention in a wafer scale package 40. In this embodiment, the outermost platform 14 is positioned at the footprint of the semiconductor device 28. The face, and then the platform if, is located at 157702.doc •13- 201225238 by the outermost platform 14, defined by the perimeter. csp semiconductor device 40 has the same amount of area. ^ Figure 9 to Figure U illustrates more Embodiments of the invention within a device package. Any of the illustrated RDLP configuration wipers can be equally poised-in-package. Figure 9 is a bottom plan view of a platform array for multi-device packages in accordance with the present invention. In addition to the platform 14 for electrical interconnection to an external circuit, the first side of the conductive substrate can also be patterned into a heat sink 42 for thermal interconnection to an external heat dissipator. Figure 10 is illustrated in a top plan view An array of wafer attachment sites 24 interconnected by routing circuitry 26 to platform 14 of FIG. Other features that are patterned in the second side include die pad 44 thermally interconnected to heat sink 42 and bonding sites 46 for passive devices such as resistors or capacitors. Portions of the bonding sites 46 may be coated with a weldable metal such as gold to facilitate attachment of the passive device. Figure 11 illustrates some of the flexibility achieved by the RDLP of the present invention. The first semiconductor device 28 is flip-chip bonded to the wafer attachment site. The second semiconductor device 28' is attached to the die pad 44 and the wire bond 48 is attached to the wire bond pad 50. Passive device 52 is soldered to bonding site 46 and electrically interconnected 54 to second semiconductor die 28'. The features and devices illustrated in Figure 11 are then encapsulated in a second molding resin (not shown) to complete the multi-device package. A flip chip package having a wafer attachment site coplanar with a routing circuit. Figures 12 through 15 illustrate the formation of a semiconductor package in accordance with another embodiment of the present invention. As in the first embodiment, the conductive substrate 10 is patterned into a lead frame for routing electrical signals in a semiconductor package in which at least one semiconductor device is mounted, 157702.doc -14 201225238. The conductive substrate 1 (formed preferably from any suitable conductive material to a copper or copper based alloy) has a first side that is partially patterned to form an array of platforms 14 separated by channels. The surface of each of the stages 14 on the first side includes a portion of the first side surface 121 of the lead frame. Channels can be formed by any controlled subtractive process (such as chemical surrogate or laser stripping). For example, the portion of the first surface that is intended to form a flat surface may be coated with a chemical anti-surname agent and expose the first surface to a time that the remaining agent is effective to form the channel over time. Typically, the channel will have a depth of from 4% to 99% of the thickness of the conductive substrate, and preferably the channel depth will be from 45% to 65% of the thickness of the conductive substrate. The platform 14 is shaped by an array pattern adapted to be coupled to an external circuit, such as a matching array of social pads on an external printed circuit board. As indicated above, to facilitate attachment to an external circuit board by soldering, the platform 14 may be surface trimmed or otherwise bonded with various solderable materials (such as solder paste, Sn, Ag, au, NiAu, etc.). As shown in Fig. 12, the first molding compound 18 is then placed in the passage of the separation platform 14. The first molding compound (typically a polymer molding resin) preferably fills the channels flush such that the platform 14 on the first side 12 becomes a wireless platform adapted for bonding to an external circuit. In this embodiment, the surface of the platform 14 is coplanar with the surface of the molding compound 18, and the surfaces include the flat first side surface 121 of the leadframe. Alternatively, the polymeric molding resin can be added to a depth slightly less than the depth of the channel such that the surface of the molded compound is recessed relative to the first side surface and the platform is provided with a avoidance distance between the package and the external printed circuit board. 157702.doc -15· 201225238 Preferably, the first molding compound 18 is non-conductive and preferably has a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 eC to 30 (TC). Alternatively, the first molding compound can be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a leadframe to a ceramic substrate in a CERpAK or cerdip package. This assembly can be supplied by a leadframe supplier. Supply to the package assembly plant for further processing' or the lead frame manufacturer can continue the process. As shown in Figure 12, the conductive substrate 10 has a second side 22 opposite the first side 12. The patterned side 22 is formed Routing circuit 26, as shown in Figure 13 and Figure i3B. Any suitable method can be used to pattern the conductive material such as chemical etching or laser ablation. Preferably, the chemically resistant material is applied to the pattern of the circuit. And then exposing the second side 22 to the etching solution to effectively remove sufficient conductive material to define the time of the routing circuit 26. As shown in Figures 13A and 13B, removed in the area between the routing circuits 26 foot The material is sufficient to expose the surface 120 of the molding compound 18, and the routing circuitry is coplanar with the surface 122 of the electrically conductive material. As best shown in Figure 13B, the leadframes in this embodiment thus have flat first side surfaces, respectively. 21 and a flat second side surface 122. In Figure 13B and other cross-sectional views, the conductive regions on the second side of the leadframe may appear to be in contact with each other. However, 'comparison with a corresponding plan view (e.g., Figure 13A) It will be appreciated that this is only an effect of viewing the regions on the edges. The regions that appear to be in contact are actually separated and located at different distances from the viewer. The wafer attachment site 124 is best shown in Figure 13A. The array is formed on the second side of the lead frame 157702.doc •16·201225238. The routing circuit 26 electrically interconnects the wafer attachment site 124 with the platform 14. The metal between the routing circuits is removed to attach the wafer to the site _ Routing Circuit - The individual combination of the platform is electrically isolated. In this embodiment, the wafer attachment site 124 is coplanar with the routing circuit 26; the wafer attachment post is not formed (compare Figure 5A and Figure 6 with Figure 13 and Figure 14) Chip The junction 124 is formed as an array that is effectively electrically interconnected directly to the input/output pads on the semiconductor device. The semiconductor device 28 is directly attached and electrically interconnected to the wafer attachment site 124, as shown in Figures 14A and 14B. By r direct, it is meant that the interconnect is by flip chip method without the use of an intervening wire bond or tape automated bonding (TAB) tape. The wafer attachment site 124 is placed in contact with the device 28 / The output pads are opposite and interconnected by interconnects 30. Suitable interconnects 3A include solder having a primary component selected from the group consisting of gold, tin, and mis (having 180 ° C and 240 ° C) The melting temperature in the range) the spacing between the beta semiconductor device 28 and the routing circuitry 26 is sufficient to allow the second molding compound to flow at both the top and bottom of the device 28. In this embodiment, the spacing is at least 25 microns. Referring to Figure 15, the second molding compound 36 then encapsulates the semiconductor device 28, the wafer attachment site 124, and the routing circuitry 26 to complete the package 138 for loading at least half of the conductor devices. Like the first molding compound 18, the second molding compound 36 is non-conductive, and is preferably a polymer molding resin having a flow temperature in the range of 25 Torr to 3 Torr. Epoxy resin). Alternatively, the second molding compound may also be a low temperature heat resistant glass composite (such as 157702.doc 17 201225238 low temperature heat resistant glass composite for attaching the lead frame to a ceramic substrate in a CERPAK or CERDIP package). The distance from the routing circuit 26 is at least about 25 microns; the space defined by the distance is filled with the second molding compound 36. The combination of the wafer attachment site 124, the routing circuit 26, and the platform 14 is referred to as a "redistribution lead frame" or rDlf in accordance with this embodiment. RDLF is formed from a single conductive substrate having a monomer structure. In the package 138 of this embodiment, the array of 'platforms 14' has a lateral extent L! greater than the lateral extent L2 of the array of wafer attachment sites ι 24 (see Figure 13 A). This type of package is a QFN (Four Flat Flat Wireless) flip chip package. The QFN package 138 has the same advantages as discussed above with reference to package 38, and additionally has the advantage of further reduced height and fewer processing steps. It will be appreciated that the RDLF of package 138 can also be used in a redistribution leadframe package (rdlp), similar to package 38 as discussed above and illustrated in Figures 8 through η. For example, an RDLP having a package 138 can be used in a wafer scale package (see Figure 8) where the lateral extents of the device 28, the array of wafer sites 124, and the array of platforms 14 are all substantially equal. Wire Bonded Wafer Package with Die Pad FIG. 16A through 18 illustrate the formation of a semiconductor package in accordance with another embodiment of the present invention. As in the embodiments described above, the conductive substrate is patterned into a lead frame for routing electrical wiring in a semiconductor package for mounting at least one semiconductor device. The conductive substrate 1 (formed from any suitable electrically conductive material, preferably copper or copper based alloy) has a first side that is partially patterned to form an array of platforms 14 separated by channels. The surface of each of the platforms 14 on the first side of 157702.doc •18·201225238 includes a portion of the first side surface 121 of the leadframe (see Figure 12). The channels can be formed by any controlled subtractive process such as chemical etching or laser ablation. For example, the portion of the first surface that is intended to form the platform 14 can be coated with a chemical resist and exposed to the appropriate surface for a suitable period of time to effectively form the channel. Typically, the channel will have a depth of from 4% to 99% of the thickness of the conductive substrate, and preferably, the channel depth will be from 45% to 65% of the thickness of the conductive substrate. The platform 14 is formed with an array pattern that is adapted to be bonded to an external circuit, such as an array of bond pads that match the external printed circuit board. As noted above, to facilitate attachment to an external circuit board by soldering, the platform 14 can be surface trimmed or plated with various solderable materials (such as solder paste, Sn, Ag, Au, NiAu, etc.). The first molding compound 18 is then placed in the passage of the separation platform 14. The first molding compound (typically a polymeric molding resin) preferably fills the channels flush so that the platform 14 on the first side becomes adapted for bonding. A non-wired platform for P circuits. In this embodiment, the surface of the platform crucible 4 is coplanar with the surface of the molding compound 18, and the surfaces include the flat first side surface 22 of the lead frame or the polymer molding resin can be added to the channel. The depth of the depth is such that the surface of the molding compound is concave with respect to the first side surface, and the platform has a distance between the package and the external printed circuit board. Preferably, the first molding compound i 8 is non-conductive. And preferably a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 ° C to 300 ° C. Alternatively, the first molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAK or CERDIP package. This assembly can be supplied by the leadframe supplier to the package assembly plant for further processing' or the lead frame manufacturer can continue the process. As in the embodiments described above, the conductive substrate 丨〇 has a second side opposite the first side. The second side is patterned to form a die pad 225 and routing circuitry 226, as shown in Figures 16A and 16B. The conductive material can be patterned using any suitable method, such as chemical surrogate or laser stripping. Preferably, the chemical resistant material is applied to the pattern of the circuit and then the second side is exposed to the etching solution to effectively remove sufficient conductive material to define the time of the beta θ 塾 225 and routing circuit 226. As shown in Figures 16A and 16B, sufficient material is removed between the die pad and the routing circuitry and between the routing circuitry to expose the surface 22 of the molding compound 18, while the die pad and routing The circuitry is coplanar with the surface 222 of the electrically conductive material. The lead frame in this embodiment as shown in Fig. 16B thus has a flat first side surface 221 and a flat second side surface 222, respectively. As best shown in Figure 16A, an array of wire bonding sites 224 is formed on the second side of the wireframe that is spaced from the die pad 225 and surrounds the die pad 225. Routing circuit 226 electrically interconnects wire bonding sites 224 and platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wire bonding sites - routing circuits - platforms. In this embodiment, the wire bonding site 224 is coplanar with the routing circuit 226. Wire bond site 224 is configured for electrical connection to an input/output pad on a semiconductor device. In particular, the wire bonding sites 224 can advantageously be surface trimmed or plated with materials useful to facilitate wire bonding (e.g., 157702.doc • 20·201225238)

Ag, NiPdAu, NiAu, etc.). In this embodiment, the die pad occupies a central portion of the second side surface, and both the platform and the wire bonding site are disposed around the periphery of the die pad. The die pad is placed in the centerless portion of the substrate. Figure 6C is a bottom plan view of the leadframe in this embodiment; the portion of the substrate corresponding to the location of the die pad has an exposed bottom surface 214' and is surrounded by the platform 14 (compare Figure 3A). The semiconductor device 228 is directly attached to the die pad 225 and is electrically connected to the wire bonding site 224 by wires 223, as shown in Figures 17A and 17B. Routing circuit 226 can follow a variety of different paths; this allows the wire to be coupled to site 224 to improve the routing layout. Referring to Figure 18, a second molding compound 36 then encapsulates semiconductor device 228, wire bonding sites 224, and routing circuitry 226 to complete package 238 for mounting at least one semiconductor device. Like the first molding compound 18, the second molding compound 36 is non-conductive, and is preferably a polymer molding resin (such as a ring having a flow temperature in the range of 25 ° C > c to 300 C) Oxygen resin). Alternatively, the second molding compound may also be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching the lead frame to a ceramic substrate in a CERPAK or CERDIP package. A redistribution lead frame (RDLF) formed by a single conductive substrate of the bulk structure. In the cover 238 of this embodiment, the array of 'platforms 14 has a lateral extent L2i greater than the lateral extent L22 of the array of wire bonding sites 224 (see Figure 16A). This type of package is a QFN (Four-Sided Flat Wireless Package) similar to the package described above and shown in Figures 9 through 11, which is also enclosed by RD 157702.doc -21 - 201225238 238 Can be used for redistribution leadframe package (RDLp)*. Wire bonded chip package with additional wire bonding sites. Figure 19 to circle 21 illustrate the formation of a semiconductor package in accordance with yet another embodiment of the present invention. In the depicted embodiment, the conductive substrate 1 is patterned into a leadframe for routing electrical signals in a semiconductor package for mounting at least one semiconductor device. Conductive substrate 1 (from any suitable guide The material is formed, preferably a copper or copper based alloy, having a first side patterned to form an array of platforms 14 separated by channels. Each of the platforms 14 on the first side The surface of the person includes a portion of the first side surface 121 of the lead frame (see Figure 12). The channel can be formed by any controlled subtractive process such as chemical etching or laser ablation. For example, the first surface The portion of the platform 14 that is intended to be formed may be coated with a chemical resist and expose the first surface to a suitable etchant for a time effective to form the channel. Typically the channel will have a thickness of 4% to 99 for the thickness of the conductive substrate. The depth of %, and preferably the 'channel depth will be 45% to 65% of the thickness of the conductive substrate. The platform 14 is an array that is adapted to be bonded to an external circuit, such as an array of bond pads that match an external printed circuit board. Formed as a pattern. As indicated above, 'to facilitate the attachment to an external circuit board by soldering, the platform 14 may be surface-finished or plated with various solderable materials (such as solder paste, Sll, Ag, Au, NiAu, etc.) Connect The first molding compound 18 is disposed within the passage of the separation platform 14. The first molding compound (typically a polymer molding resin) preferably fills the channel flush so that the platform 14 on the first side becomes adapted In the embodiment, the surface of the platform 丨4 is coplanar with the surface of the 157702.doc •22-201225238 molding compound 18, and the surfaces include the flattening of the lead frame One side surface 221. Alternatively, the polymer molding resin may be added to a depth slightly smaller than the depth of the channel such that the surface of the molding compound is recessed relative to the first side surface, and the platform is provided between the package and the external printed circuit board Avoid the distance. Preferably, the first molding compound 18 is non-conductive, and is preferably a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 °C to 300 °C. Alternatively, the first molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAk or CERDIP package. The supply is supplied for further processing' or the lead frame manufacturer can continue the process. As in the embodiments described above, the conductive substrate 1 has a second side opposite the first side. The second side is patterned to form routing circuitry 226' including wire bonding sites 224 as shown in Figures 19A and 19B. The conductive material can be patterned using any suitable method, such as chemical etching or laser ablation. Preferably, the chemical resistant material is applied to the pattern of circuitry and then the second side is exposed to the etching solution to effectively remove sufficient conductive material to define the routing circuit 226. As shown in the prior embodiments as shown in Figures 19A and 19B, sufficient material is removed in the region between the die and the routing circuitry and between the routing circuitry to expose the surface of the molding compound 18. 220, and the die pad and routing circuitry are coplanar with the surface of the conductive material. As best shown in Fig. 19, the lead frame in this embodiment thus has a flat first side surface and a flat second side surface. 157702.doc • 23- 201225238 As shown in FIG. 19A, an array of 'wire bonding sites 224' is formed on the second side of the leadframe. Routing circuitry 226 electrically interconnects the wire bonding sites 224 and the platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wire bonding sites _ routing circuits - platforms. In this embodiment, the wire bonding site 224 is coplanar with the routing circuit 226. The wire bonding site 224 is configured for electrical connection to an input/output pad on the semiconductor device. In particular, the wire bonding sites 224 can advantageously be surface trimmed or plated with materials useful to facilitate wire bonding (e.g., 'Ag, NiPdAu, NiAu, etc.). In this embodiment, the second side surface is gathered with wire bonding sites 224 that create electrical connections to the platform 14, wherein the platforms are disposed on the first side surface in a regular array (see Figure 19C). Accordingly, some routing circuits have exposed metal surfaces in a central portion of the second side surface. A non-conductive layer 230 covers the metal surfaces as shown in Figure 2A. Layer 230 can be a non-conductive epoxy or non-conductive paste. Wire bond sites 224 are disposed around the perimeter of the area covered by layer 23A. Semiconductor device 228 is disposed on layer 230 and is electrically coupled to wire bonding site 224 by wire 223, as shown in Figures 20A and 20B. The non-conductive material for layer 230 can be applied to the second side surface, or alternatively the non-conductive material can be applied to the back side of the device prior to attaching the device. At least one of the routing circuits directs the underlying device 228 and layer 23 to the platform in the central portion of the leadframe (compare Figures 19A and 20A). Correspondingly, the routing circuit is coupled to an electrical conductor ("active pillar") located beneath the device, the electrical conductor extending from the first side to the second side of the leadframe. This configuration provides a number of wire bonding sites 157702.doc • 24· 201225238 (compare Figures 17A and 20A) that are larger than the number in the previous embodiment. Accordingly, the lead frame of this embodiment provides greater I/O capability. Referring to Figure 21, a second molding compound 36 then encapsulates semiconductor device 228, wire bonding sites 224, and routing circuitry 226 to complete package 248 for intrusion into at least one semiconductor device. Like the first molding compound 18, the second molding compound 36 is non-conductive 'and preferably a polymer molding resin having a flow temperature in the range of 25 Torr to 300 ° C (such as epoxy) Resin). Alternatively, the second molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAK or CERDIP package. As in other embodiments, the leadframe in this embodiment is a redistribution leadframe (rdlf) formed from a single conductive substrate that is a unitary structure. In package 248 of this embodiment, the array of platforms 14 has a lateral extent greater than or equal to the lateral extent of the array of wire bonding sites 224. This type of package is a QFN (four-sided flat no-wire) package. Similar to the package discussed above and illustrated in Figures 9 through ,, the RDLF of package 248 can also be used in a redistribution leadframe package (RDLp). Several embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conductive substrate before being patterned into a lead frame. Figure 2A is illustrated in a top plan view and Figure (5) is shown in cross-section to illustrate a partially patterned lead frame on the first side of 157702.doc • 25-201225238. Figure 3A is illustrated in a top plan view and Figure 3 is a cross-sectional view showing a wire having a material embedded in a polymer molding resin. Figure 4 is shown in cross section in two sides. Form a wire post. Figure 5A is illustrated in a top plan view and Figure (9) is shown in cross-section to illustrate the formation of routing leadframe features in the second side of the partially patterned leadframe. The figure is illustrated in a top plan view and is shown in cross-section to illustrate the attachment of a semiconductor device to a conductor post. Figure 7 is a cross-sectional view showing a lead frame routing semiconductor package in accordance with a first embodiment of the present invention. A cross-sectional representation is used to illustrate a wafer-scale package in accordance with the present invention. Figure 9 illustrates a platform array for a multi-device package in accordance with the present invention in a bottom plan view. Figure 10 illustrates a wafer attachment location for the multi-device package of Figure 9 in a top plan view. Point array. Figure 11 illustrates a wafer attachment site array of Figure 9 with a plurality of attached devices in a top plan view. Figure 12 is a cross-sectional view illustrating the inclusion of a conductive material as shown in Figure 2A, in accordance with another embodiment. a lead frame of a substrate, wherein the platform and the wafer attachment site are located on opposite first and second sides of the lead frame. Figure 13 is a top plan view and Figure 13 is a cross-sectional view illustrating one implementation in accordance with the present invention. Example of forming a routing leadframe feature on the second side of the partially patterned lead frame 157702.doc -26-201225238 of Figure 2, the routing leadframe features including the road The device and the wafer are attached to the site. Figure 14A is illustrated in a top plan view and Figure 14B is shown in cross-section to illustrate the attachment of the semiconductor device to the die attach site of the leadframe of Figures 13A and 13B. Figure 15 The cross-hatched representation is illustrative of a leadframe routing semiconductor package in accordance with an embodiment in which a molding compound encapsulates the semiconductor device, wafer attachment sites, and routing circuitry of Figures 4A and 4B. Figure 16A is illustrated in a top plan view 16B is a cross-sectional view illustrating the formation of a routing leadframe feature on a first side of a partially patterned leadframe in accordance with another embodiment of the present invention. The routing leadframe features include routing circuitry and die pads. Figure 16C illustrates the lead frame of Figures 16A and 16B in a bottom perspective view. Figure 17A is illustrated in a top plan view and Figure 17B is shown in cross-section to illustrate the attachment of the semiconductor device to the die and lead frame of Figures 16A and 16B. Figure 18 is a cross-sectional view showing a lead frame routing semiconductor package according to an embodiment in which a molding compound encapsulates the semiconductor device, die pad and routing circuit of Figures 17A and 17B 19A is illustrated in a top plan view and FIG. 19B is a cross-sectional view illustrating the formation of routing leadframe features on a second side of a partially patterned leadframe in accordance with another embodiment of the present invention, the routing leadframe features Figure 19C illustrates the leadframe of Figures 19A and 19B in a bottom perspective view. Figure 20A is illustrated in a top plan view and Figure 2B is illustrated in cross-section to illustrate 157702.doc -27-201225238 semiconductor device to Figure 19A and Figure 19B is a cross-sectional view illustrating a leadframe routing semiconductor package in accordance with an embodiment in which a molding compound encapsulates the semiconductor device and routing circuitry of Figures 20A and 20B. [Main component symbol description] 10 Conductive substrate 12 First side of conductive substrate 14 Platform 14' Platform 14" Platform 16 Channel 18 First polymer molding resin 20 Lead frame precursor 22 Second side of conductive substrate 24 Wafer attachment Site 26 Routing Circuit 28 Semiconductor Device 28' Second Semiconductor Device 30 Interconnect 32 Distance 34 Wafer Attachment Post 36 Second Molding Compound 38 Package 40 Wafer Scale Package 157702.doc -28- 201225238 42 Heat Sink 44 Grain塾46 bonding site 48 wire bond 50 wire bond pad 52 passive device 54 electrical interconnect 120 surface of molded compound 121 flat first side surface of lead frame 122 flat second side surface of lead frame / surface 124 of conductive material Wafer attachment site 138 package 214 bottom surface 220 surface of molding compound 221 flat first side surface of lead frame 222 flat second side surface of lead frame / surface 223 of conductive material wire 224 wire bonding site 225 grain 塾226 routing circuit 228 semiconductor device 230 non-conductive layer s 238 package 248 package 157702. Doc •29- 201225238 L, lateral breadth l2 lateral breadth L21 lateral breadth L22 lateral breadth 157702.doc

Claims (1)

  1. 201225238 VII. Patent Application Range: 1. A package (138) for loading at least one semiconductor device (28), comprising: a lead frame comprising a conductive substrate and having opposite first sides and second The first side of the leadframe has a flat first side surface (丨2丨) and an array of one of the platforms (14). One of the surfaces of the platforms includes a portion of the first side surface The platforms are adapted to be coupled to an external circuit and configured in a first pattern, and the second side of the s-wire leadframe has a flat second side surface (丨22) and a wafer attachment site ( 124) An array of one of the wafer attachment sites comprising a portion of the first side surface, the wafer attachment sites being configured in a second pattern and interconnected by an interconnect (3) Directly electrically interconnected to the input/output pads on the at least one semiconductor device (28), the wafer attachment sites being disposed opposite the input/output pads, and a plurality of electrically isolated routing circuits ( 26), each of the routing circuits (26) having the inclusion a surface of a portion of the second side surface and coplanar with the wafer attachment sites (124), each of the routing circuits (26) electrically interconnecting the array of substrates (14) to the wafer An individual combination of the array of sites (124); a first molding compound (18) disposed between the first side of the leadframe and the chip of the platform (14), a surface having a portion including the first side surface (121); and a second molding compound (36) encapsulating the at least one semiconductor device 157702.doc 201225238 (28), wafer attachment site (124) The array and the routing circuits (26), wherein the platforms and the wafer attachment sites are formed from a single conductive structure; and the array of platforms (14) has greater than or equal to the wafer attachment A lateral extent of the lateral extent of the array of sites (124). 2. The package (138) of claim 1, wherein the lead frame and the routing circuit (26) are components of a single conductive substrate (1). 3. The package (138) of claim 2, wherein the single conductive substrate (10) is a copper or copper based alloy. 4. The package (138) of claim 2, wherein one of the first perimeters defined by the array of platforms (10) does not exceed one of the second perimeters defined by the at least one semiconductor device (28). 5. The package (138) of claim 4, which is a wafer scale package. 6. The package (10)) of claim 2, further comprising a heat sink (42), the heat sink (42) being a single conductive substrate having the lead frame and coplanar with the array of platforms (14). 7. The package (138) of claim 2, further comprising a die pad (44) for bonding to the at least one semiconductor device (28), the die pad (44) and the leadframe Monomer. 8. The package (138) of claim 2, further comprising a binding site for incorporation of a passive device (52), the bonding sites being monolithic with the leadframe. 157702.doc -2- 201225238 9. The package (138) of claim 2, wherein a distance (32) between the at least one semiconductor device (28) and the routing circuits (26) is at least 25 microns, and One of the spaces defined by the distance (32) is filled with the second molding compound (36). 1. The package (138) of claim 1, wherein at least one of the arrays of platforms (14) comprises at least one of: solder paste, Sn, Ag, Au, and NiAu 〇ιι· a package (i38) for loading at least one semiconductor device (28), comprising: a lead frame comprising a conductive substrate and having opposite first and second sides; the first of the lead frames The side has an array of a flat first side surface (121) and a platform (14), one of the surfaces of the platform comprising a portion of the first side surface, the platforms being adapted to be bonded to the exterior The circuitry is configured in a first pattern, and the second side of the leadframe has an array of flat second side surfaces 22) and wafer attachment sites (124), the wafer attachment sites Each of the second side surfaces includes a portion of the second side surface, the wafer attachment sites being configured in a second pattern and electrically interconnected directly to the at least one semiconductor device by interconnects (3) (28) an input/output pad on which the wafer attachment sites are placed An input/output pad opposite, and a plurality of electrically isolated routing circuits (26), each of the routing circuits (26) having a portion including the second side surface and attachment sites (124) to the wafers a coplanar surface, an individual combination of the array of 157702.doc 201225238 electrical interconnection platforms (14) and the array of wafer attachment sites (丨24) in the routing circuit (26); a molding compound (18) disposed between the first side of the lead frame and the individual platform of the platform (14) having a recess relative to the first side surface (121) - a surface; and a second molding compound (36) encapsulating the at least one semiconductor device (28), the array of wafer attachment sites (124), and the routing circuits (26), wherein the platforms and The wafer attachment sites are formed from a single conductive structure; and the array of platforms 04) has a lateral extent greater than or equal to the lateral extent of the array of wafer attachment sites (124). 12. The package (138)' in the package of claim n (the) lead frame and the routing circuit (26) are components of a single conductive substrate (1). The package (138) of claim 12, wherein the single-conducting substrate (10) is a copper or copper-based alloy. From the package (138) of claim 12, wherein the array-detailed by the array of platforms (10) does not exceed one of the second perimeters defined by the at least one semiconductor device (28). 15. The package (138) of claim 14 which is a wafer scale package. 16. The package (138) of claim 12, further comprising a heat sink (42), the heat sink (42) being a single conductive substrate having the lead frame and coplanar with the array of platforms (14). 157702.doc -4- 201225238 201225238 17. The package (138) of claim 12, further comprising: a die 塾 (44) for bonding the at least-semiconductor device (28) t, the die The crucible (44) is monolithic with the lead frame. 18. The package (138) of claim 12, further comprising a binding site for incorporating a passive device (52), the bonding sites being monolithic with the leadframe. 19. 19. The package of claim 12. (138), wherein a distance (32) between the at least one semiconductor device (28) and the routing circuits (26) is at least micrometers, and the space defined by the distance (32) is filled with the first The second molding compound (36). 13 20. The closure (138) of claim η, wherein at least one of the arrays of platforms (14) comprises at least one of: solder paste, I, Ag, Au, and NiAu. 21. A package (Μ) for mounting at least a semiconductor device (28), comprising: - a leadframe comprising: a conductive substrate and having opposite first and second sides; The first side has an array of flat first side surfaces and a platform (10), each of the platforms including a portion of the first side surface, the platforms being adapted to be coupled to an external circuit and Arranged in a first pattern, and the second side of the leadframe has an array of a flat second side surface and a wafer attachment site (24), each of the wafer attachment sites The second side surface is protruded, and the wafer attachment sites are configured according to a pattern of 157702.doc 201225238 and are directly electrically interconnected to the at least one semiconductor device (28) by an interconnect (3) On the input/output pads, the wafer attachment sites are disposed opposite the input/output pads, and a plurality of electrically isolated routing circuits (26), each of the routing circuits (26) having a surface including a portion of the second side surface and electrically interconnecting the platform (1) 4) an individual combination of the array and the array of wafer attachment sites (24); a first molding compound (18) disposed on the first side surface and in the array of platforms (14) Between the individual platforms, having a surface including a portion of the first side surface; and a second molding compound (36) encapsulating the at least one semiconductor device (28), the wafer attachment site (24) The array and the routing circuits (26), wherein the platforms and the wafer attachment sites are formed from a single conductive structure; and the array of platforms (14) has greater than or equal to the wafer attachment sites (24) A lateral extent of the lateral extent of the array. 22. The package (38) of claim 21, wherein the leadframe and the routing circuitry (26) are components of a single electrically conductive substrate (1). 23. The package (38) of claim 22, wherein the single conductive substrate (1 turns) is a steel or a copper based alloy. 24. The package (38) of claim 22, wherein one of the first perimeters defined by the array of platforms (14) does not exceed one of the second perimeters defined by the at least one semiconductor device (28). 157702.doc 201225238 25. The package (38) of claim 24, which is a wafer scale package. 26. The package (38) of claim 22, further comprising a heat sink (42) having a single conductive substrate having the lead frame and the array of the platform (14); . 27. The package (38) of claim 22, further comprising a die pad (44) for bonding to the at least one semiconductor device (28), the die pad (44) The lead frame is made into a single body. 28. The package (38) of claim 22, further comprising a binding site for bonding to a passive device (52), the bonding sites being monolithic with the leadframe. 29. The package (38) of claim 22, wherein a distance (32) between the at least one semiconductor device (28) and the routing circuits (26) is at least 25 microns, and by the distance (32) One of the spaces defined is filled with the second molding compound (36). 30. The package (38) of claim 22, wherein a distance (32) between the at least one semiconductor device (28) and the routing circuit (26) is at least 75 microns, and by the distance (32) One of the spaces defined is filled with the second molding compound (36). 31. The package (38) of claim 30, wherein the distance (32) is from about 1 micron to about 150 microns. 32. The package (38) of claim 21, wherein at least one of the arrays of platforms (14) comprises at least one of: solder paste, Sn, Ag, Au, and NiAu. 33. A package (38) for mounting at least one semiconductor device (28), the package 157702.doc 201225238 comprising: a leadframe comprising a conductive substrate and having opposite first and second sides The first side of the leadframe has an array of flat first side surfaces and a platform (14), one of the surfaces of the platforms including a portion of the first side surface, the platforms being adapted To be coupled to an external circuit and configured in a first pattern, and the second side of the leadframe has an array of flat second side surfaces and wafer attachment sites (24) attached to the wafer Each of the sites is protruded from the second side surface, the wafer attachment sites being configured in a second pattern and electrically interconnected directly to the via by interconnects (30); a semiconductor Input/output pads on the device (28), the wafer attachment sites are disposed opposite the input/output pads, and a plurality of electrically isolated routing circuits (26) in the routing circuit (26) Each having a surface including a portion of the second side surface Each of the circuits (26) electrically interconnects the platform (14) with an individual combination of the array of wafer attachment sites (24); a first molding compound (18) 'positioned in the Between one of the surfaces of the array of the platform (14) and the surface of the platform (14) having a recess relative to the first side surface; and a second molding compound (36) encapsulating the at least one The semiconductor device (28), the array of wafer attachment sites (24), and the routing circuits (26), wherein the platforms and the wafer attachment sites are from a single conductive structure and 157702.doc - 8 - 201225238 is formed; and the array of platforms (I4) has a lateral extent greater than or equal to the lateral extent of the array of wafer attachment sites (24). 34. 35. 36. 37. 38. 39. 40. 41. The package (38) of claim 33, wherein the lead frame and the routing circuit (26) are elements of a single conductive substrate (10). The package (38) of claim 34, wherein the single conductive substrate (1 turns) is a copper or copper based alloy. The package (38) of claim 34, wherein one of the first perimeters defined by the array of platforms (14) does not exceed one of the second perimeters defined by the at least one semiconductor device (28). The package (38) of claim 36 is a wafer scale package. The package (38) of claim 34, further comprising a heat sink (42) having a single conductive substrate having the lead frame and coplanar with the array of platforms (14). The package (38) of claim 34, further comprising a die pad (44) for bonding to the at least one semiconductor device (28), the die pad (44) being singulated with the lead frame body. The package (10) of claim 34, further comprising a binding site for incorporation of a passive device (52) and the bonding sites are monolithic with the leadframe. The package (38) of claim 34 is wherein the distance between the at least one semiconductor device (10) and the routing circuit (26) is (the distance defined by the distance (10) is at least 25 microns, and the space is filled with the first The second molding compound (36). 157702.doc 201225238 42. The package (38) of claim 34, wherein the distance (32) between the at least one semiconductor device (28) and the routing circuit (26) The space is at least 75 microns, and the space defined by the distance (32) is filled with the second molding compound (36). 43. The package (38) of claim 44, wherein the distance (32) is from From about 1 micron to about 150 microns. 44. The enclosure (38) of claim 33, wherein at least one of the arrays of the platform (10) comprises at least one of: solder paste, sn, Ag , Au and NiAu. A package (238, 248) for mounting at least one semiconductor device (228), comprising: a lead frame comprising a conductive substrate and having opposite first sides and second The first side of the lead frame has an array of a flat first side surface (221) and a platform (14), One of the surfaces of each of the platforms includes one of the first side surfaces, the platforms being adapted to be coupled to an external circuit and configured in a first pattern, and the second of the lead frames The side has an array of a flat second side surface (222) and a wire bonding site (224), each of the wire bonding sites comprising a portion of the second side surface, the wire bonding sites being pressed a second pattern configured and electrically interconnected to the input/output pads on the at least one semiconductor device (228); and a plurality of electrically isolated routing circuits (226), each of the routing circuits (226) Having a surface comprising a portion of the second side surface and coplanar with the isoelectric 157702.doc •10·201225238 line, the rendezvous (224), each of the routing circuits (226) being electrically interconnected An individual combination of the array of the platform (14) and the wire bonding site (10); a first molding compound (18) disposed at the first side of the leadframe and the platform (14) Between individual platforms in the array; and a second molding compound (36), Encapsulating the at least one semiconductor device (228), the array of wire bonding sites (224), and the routing circuits (226), wherein the platforms and the wire bonding sites are formed from a single conductive structure And the array of platforms (14) has a lateral extent greater than or equal to the lateral extent of the array of wire bonding sites (224). 46. The package (238, 248) of claim 45, wherein the leadframe and the routing circuitry (226) are components of a single electrically conductive substrate. 47_ The package (238, 248) of claim 46 wherein the single conductive substrate (10) is a copper or copper based alloy. 48. The package (238, 248) of claim 46, wherein one of the first perimeters defined by the array of platforms (14) does not exceed a second perimeter defined by the at least one semiconductor device (22 8). 49. The package (238, 248) of claim 45, wherein the first molding compound has a surface comprising a portion of the first side surface (221). 50. The package (238, 248) of claim 45, wherein the first molding compound has a surface that is recessed relative to the first side surface (221). 157702.doc • 11-201225238 51. The package (238) of claim 46, further comprising a heat sink (42) having the array of the leadframe and the platform (I*) One of the coplanar single conductive substrates. 52. The package (238) of claim 46, further comprising a die pad (225) for bonding one of the at least one semiconductor device (228), the die pad (225) and the leadframe Monomer. 53. The package (238) of claim 52, wherein the die pad (225) is coplanar with the routing circuitry (226) and has a surface including a portion of the second side surface (222). 54. The package (248) of claim 46, further comprising a non-conductive layer (230) disposed on at least a portion of the second side surface (222) such that the wires are bonded The site (224) is not covered by the non-conductive layer, and at least one of the routing circuits (226) extends below the non-conductive layer. 55. The package (248) of claim 54, wherein the at least one semiconductor device (228) is disposed on the non-conductive layer (23A). 56. The package (248) of claim 55, wherein at least one of the platforms (14) in the first pattern is on the first side surface corresponding to the second side surface by the semiconductor device ( 228) a portion of a portion of the cover is on the first side surface such that at least one electrical conductor extends from the first side surface to the second side surface under the semiconductor device and is electrically connected to extend below the non-conductive layer The routing circuit. 57. The package (238, 248) of claim 45, wherein in the array of platforms (14), a platform comprises at least one of: solder paste, 157702.doc _ 201225238 Sn, Ag , Au and NiAu. 5. The package (238, 248) of claim 45, wherein at least one of the wire bonding sites (224) comprises at least one of: Ag, NiPdAu, and NiAu. -13- 157702.doc
TW100125855A 2003-06-25 2011-07-21 Lead frame routed chip pads for semiconductor packages TW201225238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/843,183 US8304864B2 (en) 2003-06-25 2010-07-26 Lead frame routed chip pads for semiconductor packages

Publications (1)

Publication Number Publication Date
TW201225238A true TW201225238A (en) 2012-06-16

Family

ID=45914226

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100125855A TW201225238A (en) 2003-06-25 2011-07-21 Lead frame routed chip pads for semiconductor packages

Country Status (2)

Country Link
CN (2) CN107579054A (en)
TW (1) TW201225238A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154658A (en) * 1997-07-30 1999-02-26 Hitachi Hokkai Semiconductor Ltd Semiconductor device, manufacture thereof and frame structure
JP2001267473A (en) * 2000-03-17 2001-09-28 Hitachi Ltd Semiconductor device and its manufacturing method
EP1207555A1 (en) * 2000-11-16 2002-05-22 Texas Instruments Incorporated Flip-chip on film assembly for ball grid array packages
JP2007521656A (en) * 2003-06-25 2007-08-02 アドバンスド インターコネクト テクノロジーズ リミテッド Lead frame routed chip pads for semiconductor packages

Also Published As

Publication number Publication date
CN102412224A (en) 2012-04-11
CN107579054A (en) 2018-01-12

Similar Documents

Publication Publication Date Title
US6987031B2 (en) Multiple chip semiconductor package and method of fabricating same
US5608262A (en) Packaging multi-chip modules without wire-bond interconnection
US9502390B2 (en) BVA interposer
US7049692B2 (en) Stacked semiconductor device
US6232666B1 (en) Interconnect for packaging semiconductor dice and fabricating BGA packages
US7075816B2 (en) Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
US9117684B1 (en) Semiconductor package having a plurality of input/output members
US6489676B2 (en) Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6589810B1 (en) BGA package and method of fabrication
US7344917B2 (en) Method for packaging a semiconductor device
US6825553B2 (en) Multichip wafer level packages and computing systems incorporating same
US6191487B1 (en) Semiconductor and flip chip packages and method having a back-side connection
US5858815A (en) Semiconductor package and method for fabricating the same
US7417299B2 (en) Direct connection multi-chip semiconductor element structure
US6803254B2 (en) Wire bonding method for a semiconductor package
US6759737B2 (en) Semiconductor package including stacked chips with aligned input/output pads
US6084308A (en) Chip-on-chip integrated circuit package and method for making the same
US5578525A (en) Semiconductor device and a fabrication process thereof
KR101056245B1 (en) Embedded die package and process using pre-molded carrier
US6534391B1 (en) Semiconductor package having substrate with laser-formed aperture through solder mask layer
JP4895506B2 (en) Image sensor device
US8399776B2 (en) Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US7902648B2 (en) Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods
US6380048B1 (en) Die paddle enhancement for exposed pad in semiconductor packaging
US7087461B2 (en) Process and lead frame for making leadless semiconductor packages