201225238 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種用於囊封-或多個半導體器件之類型 之模製塑膠封裝的導線架。更特…，該導線架係藉由 -循序金屬移除製程而自單_導電基板形成，該製程選擇 性地圖案化外部導線端、路由電路及内部導線端。 【先前技術】 用以裝入半導體器件的一種類型之封裝為模製塑膠封 裝。將半導體器件裝入提供環境保護之聚合物樹脂塊中。 藉由諸多不同導電結構而在半導體器件與外部電路（諸如 印刷電路板（「PCB」）之間傳輸電信號。在導線式封裝 中，-導電導線架具有内部導線端及對置之外部導線端。 通常藉由化學钱刻來形成、兮遵加 术Φ成該導線架組態。内部導線端的間 距出於钱刻考慮而被限制至約導線架 終止於距半導體器件-距離處且藉由小直徑電線=電導= 連至半導體器件上之輸入/輸出塾。導線自内部導線端向 外延伸以終止於經焊接至外部電路上之接觸墊的外部導線 端處。此類型之導線式封裝所佔用的佔據面積（印刷電路 板或其他外部結構上之表面積）顯著大於半導雜器件之佔 據面積。 在半導體封裝業中需要最小化半導體封裝之佔據面積來 達，獲得晶片尺度封裝（其中封裝之佔據面積不大於半導 體器件之佔據面積）的目標。在導線式封裝中，在内部導 線處之結合㈣距與在用於電路板附接之封裝外部的平台 157702.doc 201225238 間距之間始終存在相當大的差異。結合墊間距趨向於達成 較精細之幾何形狀以最大化對矽面積之使用，而電路板級 間距保持較寬地隔開以用於PCB路由及焊接。自晶片結合 墊間距至外部平台間距之導線架扇出導致封裝佔用比半導 體器件大得多的佔據面積。此與晶片尺度封裝（「csp」） 之概念及需求相恃。 朝著CSP之趨勢已驅使發展具有以合適之電路板附接間 距配置成柵格陣列之外部平台的「陣列」封裝。此栅格陣 列被約束於晶片之佔據面積内。然而，此封裝需要藉由使 用界面（常稱為插入物）將半導體器件結合墊路由至所要之 平台位置。如美國專利第6,477,034號中所揭示，插入物為 多層（通常為薄的2層或3層）可撓性或類似之基板，其賦能 間距扇出及路由。美國專利第6,477 〇34號以全文引用之方 式併入本文中。插入物並非較佳的。除主要之成本添加 外’在封裝組裝期間亦需要額外處理步驟。 球狀柵格陣列（「BGA」）封裝將印刷電路板基板用於電 路路由且用於支援在應用限制内之平台重定位，亦即，折 衷處理路由特徵/能力方面的技術限制與板附接焊接限 制。為賦能密集封裝及平台之定位，許多BGA基板利用具 有通孔之多層組態。然而，此等BGA基板之使用及通孔之 添加顯著增加成本及處理步驟。 一種用以製造用於四邊扁平無導線（「QFN」）封裝之導 線架的方法揭示於頒予McLeUan等人之美國專利第 6,498,099號中，肖案以全文引用之方式併入本文中。部分 157702.doc 201225238 地蝕刻一導電基板之第一側以界定墊附接件及内部導線 端。將一半導體器件結合至該經部分地界定之墊附接件且 藉由電線結合件或其類似者而將該半導體器件電互連至經 部分地界定之内部導線端。接著將半導體器件、經部分地 界定之墊附接件、經部分地界定之内部導線及電線結合件 囊封於聚合物模製樹脂中。接著蝕刻導電基板之對置之第 一側以使墊附接件與内部導線端電隔離並界定外部導線 端〇 用於製造QFN封裝之另一種方法揭示於共同擁有之美國 專利第6,812,552號中，且該專利之全文以引用之方式併入 本文中。頒佈為美國專利第6,812 552號之申請案於2〇〇3年 1〇月30日公開為美國專利申請公開案us A1 〇 然而’仍需要—種用於製造具有準確定位之内部導線端 及外部導線端與不需要複雜之製造步驟或不包括補充性插 入物電路的路由電路之晶片尺度封裝及其他半導體封裝之 方法。此外，仍需要藉由此方法所製造之封裝。 、 【發明内容】 根據本發明之第—實施例，提供—種用於裝人至少 導體器件之封劈 的… 包括具有對置之第一側及第二側 平… _之第-側具有-平坦第-側表面及一 ° 4 ’該等平台中之每一者之*而勺入楚 一 = 耆之表面包含第一側表面之 :刀，該等平台經調適以待結合至外部電路且 ”亥導線架之第二側具有一平坦第二側表面及 157702.doc 201225238 -晶片附接位點陣列。該等晶片附接位點中之每一者包含 第二側表面之一部分。該等晶片附接位點係按第二圖案而 配置且直接電互連至半導體器件上之輸入/輸出墊。複數 • ㈣隔離之路由電路位於導線架之第二側上。該等路由電 料之每-者具有包含第二側表面之—部分且與晶片附接 ㈣共面之表面，該等路由電路中之每_者電互連平台陣 列與晶片附接位點陣列之個別組合。該等平台及該等:片 附接位點係自單體導電結構形成。安置於導線架之第一側 處及個別平台之間的第一模製化合物具有包含第一側表面 之一部分的表面。第二模製化合物囊封半導體器件、晶片 附接位點陣列及路由電路。 根據本發明之另一實施例，一種用於裝入至少一半導體 器件之封裝具有如上文所描述的—導線架、晶片附接位點 及路由電路，但第一模製化合物之表面相對於平坦第一側 表面而凹陷。平台因此具備封裝與外部印刷電路板之間的 避開（stand-off)距離。 根據本發明之額外實施例’ 一種用於裝入至少一半導體 器件之封裝具有如關於第一實施例所描述的一導線架、晶 片附接位點及路由電路’只是該等晶片附接位點不與路由 電路共面而改為自第二側表面突出。半導體器件與路由電 路之間的增加的間隔促進第二模製化合物在器件之下側流 動。 根據本發明之另一實施例，一種用於裝入至少一半導體 器件之封裝具有如上文關於第一實施例所描述的一導線 157702.doc 201225238 架、晶片附接位點及路由電路，只是第一模製化合物之表 面相對於平坦第—側表面而凹陷以使得平台具備避開距 離’且晶片附接位點不與路由電路共面而改為自第二側表 面突出。 根據本發明之又-實施例，提供—種封裝，其包括具有 對置之第-侧及第二側之導線架。該導線架之第一側具有 一平坦第-側表面及-平㈣列，該等平台中之每一者之 表面包含第-側表面之一部分；該等平台經調適以待結合 至外部電路且係按第一圖案而配置。該導線架之第二側具 有-平坦第二側表面（具有晶粒墊）及一電線結合位點陣 列。該等電線結合位點中之每一者可包含第二側表面之一 部分。該等電線結合位點係按第二圖案而配置，且直接電 互連至半導體器件上之輸人/輸出墊。與晶粒塾共面之複 數個電隔離之路由電路位於導線架之第二側上。該等路由 電路中之每一者具有句令签-也丨主工 彳具有匕3第一側表面之-部分且與電線結 口位點共面的表面’該等路由電路中之每一者電互連平台 陣列與電線結合位點陣列之個別組合。該等平台及該等^ 線結合位點係自單體導電結構形成。安置於導線架之第一 側處及個別平台之間的第一模製化合物具有包含第一側表 面之一部分的表面。第二模製化合物囊封半導體器件、晶 粒墊、電線結合位點陣列及路由電路。 根據本發明之額外實施例，一種封裝包括如上文剛描述 的-導線架及電線結合位點’但在導線架之第二側上具有 -非導電層而非晶粒塾。一半導體器件安置於該非導電層 157702.doc 201225238 上，且形成至該器件之電線結合連接。路由電路中之至少 -者在非導電層下方延伸，且平台中之至少__者在其__部 分(對應於第二側表面之由半導體器件所覆蓋的一部分)中 位於第-側表面上，使得至少一電導體在半導體器件下方 自第-側表面延伸至第二側表面且電連接至在非導電層下 方延伸之路由電路。 根據此等實施例’容易提供晶片尺度封裝及用以囊封多 個器件之封裝。另外’導線架可自單體導電結構形成且藉 由第-模製化合物來支撐。此導致導線架係穩固的且心 與共面性之損失有關的極少問題。 在下文之隨附圖式及描述中陳述本發明之各種實施例之 細節。本發明之其他特徵、目標及優點將自該描述及該等 圖式以及申請專利範圍而顯而易見。 【實施方式】 各圖式中之相同參考數字及名稱係指示相同元件。 圖1以橫截面表示來說明-導電基板1〇，其將被圖案化 為用以在用於裝入至少-半導體器件之半導體封裝中路由 電信號的導線架。導電基板10可自任何合適之導電材料形 =，且較佳自銅或銅基合金形成。就鋼基合金而言，其意 謂導電基板ίο含有大於50%(以重量計）之銅。導電基板 具有自（MG mm至0.25職（〇._时至GG㈣）之^佳厚 度，且通常係以-卷經單-化（通常作為製造過程中之 後步驟）之部分附接之基板的形式來表示。 具有晶片附接柱之覆晶封裝 157702.doc -9- 201225238 參看圖2B，導電基板10之第一側12經部分圖案化以形成 藉由通道16分離之平台14之陣列。位於第一側以上之平台 14中之每一者的表面包含導線架之平坦第一側表面之一部 分。 可藉由任何受控之減式製程（諸如化學蝕刻或雷射剝蝕） 來形成通道。舉例而言，第一表面之意欲形成平台Μ的部 分可塗佈有化學抗蝕劑，且使第一表面曝露至合適之蝕刻 劑歷時有效地形成通道16的時間。通常，通道16將具有為 導電基板厚度之40%至99%的深度，且較佳地，通道深度 將為導電基板厚度之45°/。至65%。 如圖2A中所示，平台14係以經調適以待結合至外部電路 (諸如匹配外部印刷電路板上之結合墊陣列）之陣列圖案而 形成。為促進藉由焊接而與外部電路板的附接，平台14可 經表面修整或鍍有各種可焊接材料（諸如焊錫膏、Sn、 Ag、Au、NiAu等）。 接著將第一模製化合物安置於通道16内。如圖3B中所 示’第一聚合物模製樹脂18較佳齊平地填充通道16，使得 平台14之第一側變成經調適用於結合至外部電路之無導線 平台。在此實施例中，平台14之表面與模製化合物18之表 面共面’且該等表面包含導線架之平坦第一側表面。或 者’可將第一聚合物模製樹脂添加至稍小於通道之深度 的深度，使得模製化合物之表面相對於第一側表面而凹 陷’且平台具備封裝與外部印刷電路板之間的避開距離。 較佳地’第一模製樹脂18為非導電的，且較佳為具有在 157702.doc •10· 201225238 250°C至300°C之範圍中之流動溫度的聚合物模製樹脂（諸 如環氧樹脂）。或者，第一模製樹脂可為低溫耐熱玻璃複 合物（諸如用以將導線架附接至CERPAK或CERDIP封裝中 之陶瓷基底的低溫耐熱玻璃複合物 可由導線架供應商將此總成（如圖3A中所說明之導線架 前驅物20)供應至封裝組裝廠以供進一步處理，或導線架 製造者可繼續該處理。 如圖4中所示，接著圖案化導電基板1〇之對置之第二側 22以形成晶片附接位點24，該等晶片附接位點以形成為有 效地直接電互連至半導體器件上之輸入/輸出塾的陣列。 可使用任何合適之方法來圖案化晶片附接位點24，諸如化 學蝕刻或雷射剝蝕。較佳地，將抗化學腐蝕材料塗覆於陣 列之圖案中，且接著使第二側曝露至蝕刻溶液歷時有效地 移除足夠材料以界定晶片附接位點24的時間。 如圖5A及圖5B中所說明，進一步圖案化第二側22以形 成使晶片附接位點24與平台14電互連的路由電路26。移除 路由電路之間的金屬以使晶片附接位點·路由電路-平台之 個別組合電隔離。路由電路26各自具有包含平坦第二側表 面之一部分的表面，且電互連平台14之陣列與晶片附接位 點24之陣列的個別組合。在此實施例中，晶片附接位點24 中之每一者自導線架之第二側表面突出。 半導體器件28在晶片附接位點24處直接附接及電互連至 導線架，如圖6A及圖6B中所示。所謂「直接」，其意謂互 連係藉由覆晶方法而不使用介入之電線結合件或捲帶式自 157702.doc 201225238 動結合（TAB)帶。晶片附接位點24安置成與器件28之輸入/ 輸出塾相對’且藉由互連件30而互連。合適之互連件3〇包 括具有選自由金、錫及船組成之群之主要組份的焊料（具 有在1 80°C與240°C之間的範圍中之熔化溫度）。在此實施 例中’晶片附接柱34自路由電路26向上延伸；器件28之下 側因此位於距路由電路26之表面上方一距離32處。選擇半 導體器件28與路由電路26之間的間隔32以促進第二模製化 合物之流動，如下文所詳述。此間隔通常為至少25微米； 在此實施例中’間隔為至少75微米。在其他實施例中，間 隔可在約100微米至約150微米之範圍中。較佳地，間隔32 之50%至75%(高度）係歸因於晶片附接柱34，且間隔之 50%-25°/〇(高度）係歸因於互連件3〇。 參看圖7 ’第二模製化合物36接著囊封半導體器件28、 晶片附接位點24及路由電路26以完成用於裝入至少一半導 體器件之封裝38。與第一模製化合物μ一樣，第二模製化 合物36為非導電的，且較佳為具有在250。(：至300。(：之範圍 中之流動溫度的聚合物模製樹脂（諸如環氧樹脂）。或者， 第二模製化合物亦可為低溫耐熱玻璃複合物（諸如用以將 導線架附接至CERPAK或CERDIP封裝中之陶瓷基底的低溫 对熱玻璃複合物）。 將晶片附接位點24、晶片附接柱34、路由電路26及平台 14之組合稱為「再分配導線架」或RDLF。RDLFs自作為 單體結構之單一導電基板形成。在圖7中所示之封裝實施 例中，平台14之陣列佔用比晶片附接位點24之陣列大的面 157702.doc •12· 201225238 積。此類型之封裝為QFN(四邊扁平無導線）覆晶封裝。本 發明之封裝38優於先前QFN覆晶封裝的優點有： a. 路由電路被扁平地支撐於第一模製化合物上，而不同 於與被黏住或堵塞之電路跡線相關聯的爲平性問題； b. 被支撐時，導線指形部共面性問題消失； C.覆Ba互連向度穩固，且適用於所有封裝尺寸及格式； d. 在封裝下面不存在曝露之電路跡線或路由電路（在經 蝕刻之無導線覆晶封裝中存在曝露之電路跡線或路由 電路）； e. 適應任何晶片墊位置及間距； f. 接近100%良率及品質一致性； g. 消除對插入物之需要’且適合現有之晶片設計； h. 封裝區域可聚集混合之互連件（電線結合件、鋁超音 波結合件、覆晶附接件等）； i. 適合於囊封多個晶片及表面黏著式被動電子組件； j. 無電路跡線或路由電路被曝露於封裝底部，僅存在具 有或不具有所要之避開距離的無導線平台； k. 封裝可非常薄，此係因為不需要單獨之插入物；及 封裝可提供曝露於封裝底部之耐熱墊，如可連接至接 地或晶片上之耐熱凸塊的晶粒墊。 額外RDLF封裝組態 圖8說明在晶片尺度封裝40中的本發明之RDLF(再分配 導線架封裝）。在此實施例中，最外列之平台14，定位於半 導體器件28之佔據面積下面，且隨後列之平台if，定位於 157702.doc •13- 201225238 由最外列之平台14，所界定的周邊内。csp 半導體器件40相同量的面積。 ^ 圖9至圖U說明在多器件封裝内的本發明之實施例。伸 所說明之RDLP組態巾之任—者可同等地詩單—器 裝中》 圖9以底部平面圖說明根據本發明之用於多器件封裝之 平台陣列。除用於電互連至外部電路之平台14外，亦可將 導電基板之第一侧圖案化為用於熱互連至外部熱耗散器之 散熱片42。 圖10以頂部平面圖說明藉由路由電路26而互連至圖9之 平台14的晶片附接位點24之陣列。在第二側中被圖案化之 其他特徵包括熱互連至散熱片42之晶粒墊44及用於被動式 器件（諸如電阻器或電容器）之結合位點46。結合位點46之 部分可塗佈有可焊接金屬（諸如金），以促進被動式器件之 附接。 圖11說明藉由本發明之RDLP所達成之一些靈活性。將 第一半導體器件28覆晶結合至晶片附接位點。將第二半導 體器件28'附接至晶粒墊44，且將電線結合件48附接至電線 結合墊50。被動式器件52焊接至結合位點46，且電互連54 至第二半導體晶粒28’。接著將圖11中所說明之特徵及器件 囊封於第二模製樹脂（圖中未展示）中以完成多器件封裝。 具有與路由電路共面之晶片附接位點的覆晶封裝 圖12至圖15說明根據本發明之另一實施例之半導體封裝 的形成。如在第一實施例中，將導電基板10圖案化為用以 157702.doc -14· 201225238 =裝入至少一半導體器件之半導體封褒中路由電信號 的導線架。導電基板1〇(自任何合適之導電材料形成較 佳為銅或銅基合金）具有第一側，該第一側經部分圖案化 以形成藉由通道分離之平台14之陣列。位於第—側上之平 台14中之每一者的表面包含導線架之第-側表面121之— 部分。可藉由任何受控之減式製程（諸如化學姓刻或雷射 剝钱）來形成通道。舉例而言，第一表面之意欲形成平么 Η的部分可塗佈有化學抗姓劑，且使第一表面曝露至合： 之餘刻劑歷時有效地形成通道的時間。通常，通道將具有 為導電基板厚度之4〇%至99%的深度，且較佳地通道深 度將為導電基板厚度之45%至65%。平台14係以經調適以 待結合至外部電路（諸如匹配外部印刷電路板上之社人墊 陣列）之陣列圖案而形力。如上文所指丨，為促進藉由焊 接而與外部電路板的附接，平台14可經表面修整或鍵有各 種可焊接材料（諸如焊錫膏、Sn、Ag、au、NiAu等）。 二如圖12中所示，接著將第一模製化合物18安置於分離平 台14之通道内。第一模製化合物（通常為聚合物模製樹脂） 較佳齊平地填充通道，使得位於第一側12上之平台14變成 經調適用於結合至外部電路之無導線平台。在此實施例 中，平台14之表面與模製化合物18之表面共面，且該等表 面包含導線架之平坦第一側表面121。或者，可將聚合物 模製樹脂添加至稍小於通道之深度的深度，使得模製化合 物之表面相對於第一側表面而凹陷，且平台具備封裝與外 部印刷電路板之間的避開距離。 157702.doc -15· 201225238 較佳地，第一模製化合物18為非導電的且較佳為具有 在250eC至30(TC之範圍中之流動溫度的聚合物模製樹脂 (諸如環氧樹脂）。或者，第一模製化合物可為低溫耐熱玻 璃複合物（諸如用以將導線架附接至CERpAK或cerdip封 裝中之陶瓷基底的低溫耐熱玻璃複合物）。 可由導線架供應商將此總成供應至封裝組裝廠以供進一 步處理’或導線架製造者可繼續該處理。 如圖12中所示，導電基板10具有與第一侧12對置之第二 側22。圖案化侧22以形成路由電路26，如圖13八及圖i3B 中所示。可使用任何合適之方法來圖案化導電材料諸如 化學蝕刻或雷射剝蝕。較佳地，將抗化學腐蝕材料塗覆於 電路之圖案中，且接著使第二側22曝露至蝕刻溶液歷時有 效地移除足夠之導電材料以界定路由電路26的時間。如圖 13A及圖13B中所示，在路由電路26之間的區域中移除足 夠材料以曝露模製化合物18之表面120，而路由電路係與 導電材料之表面122共面。如圖13B中最佳地展示，此實施 例中之導線架因此分別具有平坦第一側表面丨21及平坦第 二側表面122。 在圖13B及其他橫截面圖中，位於導線架之第二側上的 導電區域可呈現為彼此接觸。然而’與相應之平面圖（例 如，圖13A)的比較可明白，此僅為在邊緣上檢視彼等區域 之效果’呈現為接觸的區域實際上被分離且位於距檢視者 之不同距離處。 如圖13A中最佳地展示’晶片附接位點124之陣列形成於 157702.doc •16· 201225238 導線架之第二側上。路由電路26電互連晶片附接位點124 與平台14。移除路由電路之間的金屬以使晶片附接位點_ 路由電路-平台之個別組合電隔離。在此實施例中，晶片 附接位點124係與路由電路26共面；未形成晶片附接柱（比 較圖5Β及圖6Β與圖13Β及圖14Β)。晶片附接位點124形成 為有效地直接電互連至半導體器件上之輸入/輸出墊的陣 列。 半導體器件28直接附接及電互連至晶片附接位點124， 如圖14Α及圖14Β中所示。所謂r直接」，其意謂互連係藉 由覆晶方法而不使用介入之電線結合件或捲帶式自動結合 (TAB)帶。晶片附接位點124安置成與器件28之輸入/輸出 墊相對，且藉由互連件30而互連。合適之互連件3〇包括具 有選自由金、錫及錯組成之群之主要組份的焊料（具有在 180°C與240°C之範圍中之熔化溫度）β半導體器件28與路 由電路26之間的間隔足以允許第二模製化合物刊在器件28 上方與下方兩者處流動》在此實施例中，間隔為至少25微 米。 參看圖15,第二模製化合物36接著囊封半導體器件28、 晶片附接位點124及路由電路26以完成用於裝入至少一半 導體器件之封裝138。與第一模製化合物18一樣，第二模 製化合物36為非導電的，且較佳為具有在25〇亡至3〇〇<^之 範圍中之流動溫度的聚合物模製樹脂（諸如環氧樹脂）。或 者，第二模製化合物亦可為低溫耐熱玻璃複合物（諸如用 以將導線架附接至CERPAK或CERDIP封裝中之陶究基底的 157702.doc 17 201225238 低溫耐熱玻璃複合物）》 半導體器件28與路由電路26之間的距離為至少約25微 米；由彼距離界定之空間填充有第二模製化合物36。 根據此實施例’將晶片附接位點124、路由電路26及平 台14之組合稱為「再分配導線架」或rDlf。RDLF係自作 為單體結構之單一導電基板而形成。在此實施例之封裝 138中’平台14之陣列具有大於晶片附接位點ι24之陣列之 橫向廣度L2的橫向廣度L!(見圖13 A)。此類型之封裝為 QFN(四邊扁平無導線）覆晶封裝。 QFN封裝138具有與上文參考封裝38所論述之優點相同 的優點，且另外具有進一步減小之高度及較少之處理步驟 的優點。 將瞭解’類似於上文所論述及圖8至圖η中所展示之封 裝38，封裝138之RDLF亦可用於再分配導線架封裝（rdlp) 中。舉例而言’具有封裝138之RDLP可用於晶片尺度封裝 (見圖8)中’其中器件28、晶片位點124之陣列及平台14之 陣列的橫向廣度皆實質上相等。 具有晶粒墊之電線結合式晶片封裝 圖16 A至圖18說明根據本發明之另一實施例之半導體封 裝的形成。如在上文所描述之實施例中，將導電基板1〇圖 案化為用以在用於裝入至少一半導體器件之半導體封裝中 路由電彳§说的導線架。導電基板1〇(自任何合適之導電材 料而形成’較佳為銅或銅基合金）具有第一側，該第一側 經部分圖案化以形成藉由通道分離之平台14之陣列。位於 157702.doc •18· 201225238 第一侧上之平台14中之每一者的表面包含導線架之第一側 表面121之一部分（見圖12)。可藉由任何受控之減式製程 (諸如化學蝕刻或雷射剝蝕）來形成通道。舉例而言，第一 表面之意欲形成平台14的部分可塗佈有化學抗蝕劑，且使 第一表面曝露至合適之蝕刻劑歷時有效地形成通道的時 間。通常，通道將具有為導電基板厚度之4〇%至99%的深 度，且較佳地，通道深度將為導電基板厚度之45%至 65%。平台14係以經調適以待結合至外部電路（諸如匹配外 部印刷電路板上之結合墊陣列）之陣列圖案而形成。如上 文所指出，為促進藉由焊接而與外部電路板的附接，平台 14可經表面修整或鍍有各種可焊接材料（諸如焊錫膏、 Sn、Ag、Au、NiAu等）。 接著將第一模製化合物18安置於分離平台14之通道内。 第一模製化合物（通常為聚合物模製樹脂）較佳齊平地填充 通道，使得位於第一側上之平台14變成經調適用於結合至 外。P電路之無導線平台。在此實施例中，平台丨4之表面與 模製化合物18之表面共面，且該等表面包含導線架之平坦 第一側表面22卜或者，可將聚合物模製樹脂添加至翁小 於通道之深度的深度，使得模製化合物之表面相對於第一 側表面而凹，且平台具備封裝與外部印刷電路板之間的 避開距離》 較佳地，第一模製化合物i 8為非導電的，且較佳為具有 在250°C至300°c之範圍中之流動溫度的聚合物模製樹脂 (諸如環氧樹脂）。或者，第一模製化合物可為低溫耐熱玻 157702.doc •19· 201225238 璃複合物（諸如用以將導線架附接至CERPAK或CERDIP封 裝中之陶瓷基底的低溫耐熱玻璃複合物）。 可由導線架供應商將此總成供應至封裝組裝廠以供進一 步處理’或導線架製造者可繼續該處理。 如在上文所描述之實施例中，導電基板丨〇具有與第一側 對置之第二側。圖案化該第二側以形成晶粒墊225及路由 電路226，如圖16A及圖16B中所示。可使用任何合適之方 法來圖案化導電材料’諸如化學姓刻或雷射剝姓。較佳 地，將抗化學腐蝕材料塗覆於電路之圖案中，且接著使第 二側曝露至蝕刻溶液歷時有效地移除足夠之導電材料以界 疋βθ粒塾225及路由電路226的時間。如圖16 A及圖16B中 所示，在晶粒墊與路由電路之間及在路由電路之間的區域 中移除足夠材料以曝露模製化合物18之表面22〇，而晶粒 墊與路由電路係與導電材料之表面222共面。如圖16B中最 佳展示’此實施例中之導線架因此分別具有平坦第一側表 面221及平坦第二側表面222。 如圖16A中最佳展示，電線結合位點224之陣列形成於導 線架之第二側上，其與晶粒墊225隔開且圍繞晶粒墊225。 路由電路226電互連電線結合位點224與平台14。移除路由 電路之間的金屬以使電線結合位點-路由電路_平台之個別 組合電隔離。在此實施例中，電線結合位點224與路由電 路226共面。電線結合位點224經配置用於電連接至半導體 器件上之輸入/輸出墊。詳言之，電線結合位點224可有利 地經表面修整或鍍有用以促進電線結合之材料（例如， 157702.doc •20· 201225238201225238 VI. Description of the Invention: [Technical Field] The present invention relates to a lead frame for a molded plastic package of the type used for encapsulation or a plurality of semiconductor devices. More specifically, the lead frame is formed from a single-conducting substrate by a sequential metal removal process that selectively patterns the outer wire ends, routing circuitry, and internal wire ends. [Prior Art] One type of package for mounting a semiconductor device is a molded plastic package. The semiconductor device is loaded into a polymer resin block that provides environmental protection. Electrical signals are transmitted between the semiconductor device and an external circuit, such as a printed circuit board ("PCB"), by a plurality of different conductive structures. In a wire package, the conductive lead frame has an inner wire end and an opposite outer wire end Usually, the lead frame configuration is formed by chemical money engraving, and the spacing of the inner wire ends is limited to the consideration of the cost to the lead frame at a distance from the semiconductor device and by a small distance. Diameter wire = conductance = input/output port connected to the semiconductor device. The wire extends outward from the inner wire end to terminate at the outer wire end of the contact pad soldered to the external circuit. This type of wire package occupies The footprint (the surface area on printed circuit boards or other external structures) is significantly larger than the footprint of semiconductor devices. In the semiconductor packaging industry, it is necessary to minimize the footprint of the semiconductor package to obtain a wafer-scale package (where the package occupies) The target is no larger than the area occupied by the semiconductor device. In the wire package, the bonding at the inner wire (four) There is always a considerable difference from the spacing of the platform 157702.doc 201225238 outside the package for board attachment. The bond pad spacing tends to achieve finer geometry to maximize the use of the area, while the board The step spacing remains widely spaced for PCB routing and soldering. The lead frame fanout from the wafer bond pad pitch to the external platform pitch results in a much larger footprint than the semiconductor device. This is a wafer scale package (" The concept of csp") is inconsistent with the demand. The trend towards CSP has driven the development of "array" packages with external platforms configured as grid arrays with appropriate board attachment pitches. This grid array is constrained to the wafer. The package is required to be routed to the desired platform position by using an interface (often referred to as an interposer). As disclosed in U.S. Patent No. 6,477,034, the insert is multi-layered (usually thin). 2 or 3 layers of flexible or similar substrate with energized pitch fanout and routing. U.S. Patent No. 6,477, No. 34 The manner is incorporated herein. Inserts are not preferred. In addition to the major cost additions, additional processing steps are required during package assembly. Ball Grid Array ("BGA") packages use printed circuit board substrates for circuit routing It is also used to support platform relocation within application limits, that is, to compromise the technical limitations of routing features/capabilities and board attachment soldering limitations. Many BGA substrates utilize through-holes for enabling dense package and platform positioning. Multi-layer configuration. However, the use of such BGA substrates and the addition of vias add significant cost and processing steps. A method for fabricating leadframes for quad flat no-wire ("QFN") packages is disclosed in In U.S. Patent No. 6,498,099 to McLeUan et al. A semiconductor device is bonded to the partially defined pad attachment and the semiconductor device is electrically interconnected to the partially defined inner wire end by a wire bond or the like. The semiconductor device, the partially defined pad attachment, the partially defined inner conductor, and the wire bond are then encapsulated in a polymeric molding resin. The etched first side of the conductive substrate to electrically isolate the pad attachment from the inner wire end and define the outer wire end. Another method for making a QFN package is disclosed in commonly-owned U.S. Patent No. 6,812,552. And the entire disclosure of this patent is incorporated herein by reference. The application issued as US Patent No. 6,812,552 is disclosed as US Patent Application Publication No. A1 on January 30, 2003. However, it is still required to manufacture internal wire ends and external parts with accurate positioning. Wire ends and methods of wafer scale packaging and other semiconductor packages that do not require complicated manufacturing steps or routing circuits that do not include complementary interposer circuits. In addition, there is still a need for a package manufactured by this method. SUMMARY OF THE INVENTION According to a first embodiment of the present invention, there is provided a package for loading at least a conductor device, including a first side and a second side having opposite sides. Flattening the first side surface and each of the 4's of the platforms; and the surface of the crucible includes a first side surface: a knife that is adapted to be coupled to an external circuit and The second side of the LED lead frame has a flat second side surface and a 157702.doc 201225238 - wafer attachment site array. Each of the wafer attachment sites includes a portion of the second side surface. The wafer attachment sites are configured in a second pattern and are directly electrically interconnected to the input/output pads on the semiconductor device. The plurality (4) isolated routing circuitry is located on the second side of the leadframe. - having a surface comprising a portion of the second side surface and coplanar with the wafer attachment (four), each of the routing circuits having an individual combination of an array of electrical interconnection platforms and an array of wafer attachment sites. And these: the attachment point of the sheet is from the single conductive junction Forming. The first molding compound disposed between the first side of the lead frame and the individual platforms has a surface including a portion of the first side surface. The second molding compound encapsulates the semiconductor device, the array of wafer attachment sites, and Routing circuit. According to another embodiment of the present invention, a package for mounting at least one semiconductor device has a leadframe, a wafer attachment site, and a routing circuit as described above, but the surface of the first molding compound The recess is recessed relative to the flat first side surface. The platform thus has a stand-off distance between the package and the external printed circuit board. According to an additional embodiment of the present invention, a package for mounting at least one semiconductor device There is a leadframe, a wafer attachment site, and a routing circuit as described with respect to the first embodiment, except that the wafer attachment sites are not coplanar with the routing circuitry and instead protrude from the second side surface. The increased spacing between the routing circuits facilitates the flow of the second molding compound on the underside of the device. According to another embodiment of the invention, a loading The package of at least one semiconductor device has a wire 157702.doc 201225238 shelf, a wafer attachment site, and a routing circuit as described above with respect to the first embodiment, except that the surface of the first molding compound is opposite to the flat first side surface The recesses are such that the platform has a avoidance distance' and the wafer attachment sites are not coplanar with the routing circuitry and instead protrude from the second side surface. According to yet another embodiment of the present invention, a package is provided that includes opposing a lead frame on the first side and the second side. The first side of the lead frame has a flat first side surface and a flat (four) column, and a surface of each of the platforms includes a portion of the first side surface; The platforms are adapted to be coupled to an external circuit and configured in a first pattern. The second side of the leadframe has a flat second side surface (having a die pad) and an array of wire bonding sites. Each of the wire bonding sites can include a portion of the second side surface. The wire bonding sites are configured in a second pattern and are directly electrically interconnected to the input/output pads on the semiconductor device. A plurality of electrically isolated routing circuits coplanar with the die are located on the second side of the leadframe. Each of the routing circuits has a linguistic sign - also a surface having a portion of the first side surface of the 匕 3 and coplanar with the wire junction site 'each of the routing circuits Individual combinations of electrical interconnect platform arrays and wire bond site arrays. The platforms and the bonding sites are formed from a single conductive structure. The first molding compound disposed between the first side of the lead frame and the individual platforms has a surface including a portion of the first side surface. The second molding compound encapsulates the semiconductor device, the crystal pad, the wire bonding site array, and the routing circuit. In accordance with an additional embodiment of the present invention, a package includes a leadframe and wire bond site as just described above but with a non-conductive layer on the second side of the leadframe rather than a die. A semiconductor device is disposed on the non-conductive layer 157702.doc 201225238 and forms a wire bond connection to the device. At least one of the routing circuits extends below the non-conductive layer, and at least one of the platforms is located on the first side surface of the __ portion thereof (corresponding to a portion of the second side surface covered by the semiconductor device) The at least one electrical conductor extends from the first side surface to the second side surface under the semiconductor device and is electrically connected to a routing circuit extending below the non-conductive layer. According to these embodiments, it is easy to provide a wafer scale package and a package for encapsulating a plurality of devices. In addition, the lead frame can be formed from a single conductive structure and supported by a first molding compound. This results in very few problems with the lead frame being stable and the loss of heart and coplanarity. The details of various embodiments of the invention are set forth in the drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and appended claims. The same reference numerals and names in the various drawings indicate the same elements. Figure 1 illustrates, in cross-section, a conductive substrate 1 that will be patterned into a leadframe for routing electrical signals in a semiconductor package for mounting at least a semiconductor device. Conductive substrate 10 can be formed from any suitable electrically conductive material, and is preferably formed from a copper or copper based alloy. In the case of a steel-based alloy, it means that the conductive substrate ίο contains more than 50% by weight of copper. The conductive substrate has a thickness from (MG mm to 0.25 Å to GG (four)), and is usually in the form of a substrate attached by a single-pass (usually a step after the manufacturing process) Representation of flip chip package with wafer attachment posts 157702.doc -9-201225238 Referring to Figure 2B, the first side 12 of the conductive substrate 10 is partially patterned to form an array of platforms 14 separated by channels 16. The surface of each of the platforms 14 above one side includes a portion of the flat first side surface of the leadframe. The channels can be formed by any controlled subtractive process such as chemical etching or laser ablation. The portion of the first surface that is intended to form the land can be coated with a chemical resist and expose the first surface to a suitable etchant for a time effective to form the channel 16. Typically, the channel 16 will have a conductive substrate. a depth of 40% to 99% of the thickness, and preferably, the channel depth will be 45°/. to 65% of the thickness of the conductive substrate. As shown in FIG. 2A, the platform 14 is adapted to be bonded to an external circuit. (such as matching external printing Formed by an array pattern of bond pads on the circuit board. To facilitate attachment to an external circuit board by soldering, the platform 14 can be surface trimmed or plated with various solderable materials (such as solder paste, Sn, Ag, Au, NiAu, etc.) The first molding compound is then placed in the channel 16. As shown in Figure 3B, the first polymer molding resin 18 preferably fills the channel 16 flush such that the first side of the platform 14 becomes Adapted to a wireless platform bonded to an external circuit. In this embodiment, the surface of the platform 14 is coplanar with the surface of the molding compound 18 and the surfaces comprise a flat first side surface of the leadframe. The first polymer molding resin is added to a depth slightly smaller than the depth of the channel such that the surface of the molding compound is recessed with respect to the first side surface and the platform has a avoidance distance between the package and the external printed circuit board. Preferably, the first molding resin 18 is non-conductive, and is preferably a polymer molding resin (such as epoxy) having a flow temperature in the range of 157702.doc •10·201225238 250° C. to 300° C. Resin Alternatively, the first molding resin can be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite used to attach the leadframe to a ceramic substrate in a CERPAK or CERDIP package, which can be assembled by a leadframe supplier (eg, The leadframe precursor 20) illustrated in Figure 3A is supplied to a package assembly factory for further processing, or the leadframe manufacturer can continue the process. As shown in Figure 4, the patterned conductive substrate 1 is then opposed. The second side 22 is formed to form wafer attachment sites 24 that are formed to be effectively electrically interconnected directly to an array of input/output ports on the semiconductor device. Patterning can be performed using any suitable method Wafer attachment sites 24, such as chemical etching or laser ablation. Preferably, the chemical resistant material is applied to the pattern of the array and then the second side is exposed to the etching solution to effectively remove sufficient material to define the time of wafer attachment site 24. As illustrated in Figures 5A and 5B, the second side 22 is further patterned to form routing circuitry 26 that electrically interconnects the wafer attachment sites 24 with the platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wafer attachment sites, routing circuits, and platforms. The routing circuits 26 each have a surface comprising a portion of the flat second side surface and an individual combination of an array of electrically interconnected platforms 14 and an array of wafer attachment locations 24. In this embodiment, each of the wafer attachment sites 24 protrudes from the second side surface of the leadframe. Semiconductor device 28 is directly attached and electrically interconnected to the leadframe at wafer attachment site 24, as shown in Figures 6A and 6B. By "direct," it is meant that the interconnection is by flip chip method without the use of an intervening wire bond or tape-and-tape type (TAB) tape. The wafer attachment sites 24 are disposed opposite the input/output ports of the device 28 and are interconnected by interconnects 30. Suitable interconnects 3 include solder having a primary component selected from the group consisting of gold, tin, and marine (having a melting temperature in the range between 180 ° C and 240 ° C). In this embodiment the wafer attachment post 34 extends upwardly from the routing circuit 26; the lower side of the device 28 is thus located a distance 32 above the surface of the routing circuit 26. The spacing 32 between the semiconductor device 28 and the routing circuitry 26 is selected to promote flow of the second molding compound, as described in more detail below. This spacing is typically at least 25 microns; in this embodiment the 'interval is at least 75 microns. In other embodiments, the spacing can range from about 100 microns to about 150 microns. Preferably, 50% to 75% (height) of the spacing 32 is due to the wafer attachment post 34, and 50%-25°/〇 (height) of the spacing is due to the interconnect 3〇. Referring to Figure 7, a second molding compound 36 then encapsulates the semiconductor device 28, the wafer attachment site 24, and the routing circuitry 26 to complete the package 38 for loading at least half of the conductor device. Like the first molding compound μ, the second molding compound 36 is non-conductive and preferably has 250. (: to a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 300. Or, the second molding compound may also be a low-temperature heat-resistant glass composite (such as for attaching a lead frame) A low temperature pair of hot glass composites to a ceramic substrate in a CERPAK or CERDIP package. The combination of wafer attachment sites 24, wafer attachment posts 34, routing circuitry 26, and platform 14 is referred to as a "redistribution leadframe" or RDLF. The RDLFs are formed from a single conductive substrate that is a unitary structure. In the package embodiment shown in Figure 7, the array of platforms 14 occupies a larger surface than the array of wafer attachment sites 24 157702.doc • 12· 201225238 product This type of package is a QFN (Four Flat Flat Wireless) flip chip package. The advantages of the package 38 of the present invention over the prior QFN flip chip package are: a. The routing circuit is supported flat on the first molding compound, and Different from the flatness problem associated with the circuit traces that are stuck or blocked; b. The coplanarity problem of the wire fingers disappears when supported; C. The Ba interconnection is stable and suitable for all Package size and format; d. There are no exposed circuit traces or routing circuitry under the package (exposed circuit traces or routing circuitry in the etched wireless flip chip package); e. Adapt to any wafer pad location and spacing; f. Close to 100% good Rate and quality consistency; g. Eliminate the need for inserts' and adapt to existing wafer designs; h. Package areas can be gathered and mixed interconnects (wire bonds, aluminum ultrasonic joints, flip chip attachments, etc.) i. is suitable for encapsulating multiple wafers and surface-adhesive passive electronic components; j. no circuit traces or routing circuits are exposed at the bottom of the package, only the non-wireless platform with or without the desired avoidance distance; k. The package can be very thin because it does not require a separate insert; and the package provides a heat resistant pad that is exposed to the bottom of the package, such as a die pad that can be attached to a ground or heat resistant bump on the wafer. Additional RDLF package Figure 8 illustrates the RDLF (Redistribution Lead Frame Package) of the present invention in a wafer scale package 40. In this embodiment, the outermost platform 14 is positioned at the footprint of the semiconductor device 28. The face, and then the platform if, is located at 157702.doc •13- 201225238 by the outermost platform 14, defined by the perimeter. csp semiconductor device 40 has the same amount of area. ^ Figure 9 to Figure U illustrates more Embodiments of the invention within a device package. Any of the illustrated RDLP configuration wipers can be equally poised-in-package. Figure 9 is a bottom plan view of a platform array for multi-device packages in accordance with the present invention. In addition to the platform 14 for electrical interconnection to an external circuit, the first side of the conductive substrate can also be patterned into a heat sink 42 for thermal interconnection to an external heat dissipator. Figure 10 is illustrated in a top plan view An array of wafer attachment sites 24 interconnected by routing circuitry 26 to platform 14 of FIG. Other features that are patterned in the second side include die pad 44 thermally interconnected to heat sink 42 and bonding sites 46 for passive devices such as resistors or capacitors. Portions of the bonding sites 46 may be coated with a weldable metal such as gold to facilitate attachment of the passive device. Figure 11 illustrates some of the flexibility achieved by the RDLP of the present invention. The first semiconductor device 28 is flip-chip bonded to the wafer attachment site. The second semiconductor device 28' is attached to the die pad 44 and the wire bond 48 is attached to the wire bond pad 50. Passive device 52 is soldered to bonding site 46 and electrically interconnected 54 to second semiconductor die 28'. The features and devices illustrated in Figure 11 are then encapsulated in a second molding resin (not shown) to complete the multi-device package. A flip chip package having a wafer attachment site coplanar with a routing circuit. Figures 12 through 15 illustrate the formation of a semiconductor package in accordance with another embodiment of the present invention. As in the first embodiment, the conductive substrate 10 is patterned into a lead frame for routing electrical signals in a semiconductor package in which at least one semiconductor device is mounted, 157702.doc -14 201225238. The conductive substrate 1 (formed preferably from any suitable conductive material to a copper or copper based alloy) has a first side that is partially patterned to form an array of platforms 14 separated by channels. The surface of each of the stages 14 on the first side includes a portion of the first side surface 121 of the lead frame. Channels can be formed by any controlled subtractive process (such as chemical surrogate or laser stripping). For example, the portion of the first surface that is intended to form a flat surface may be coated with a chemical anti-surname agent and expose the first surface to a time that the remaining agent is effective to form the channel over time. Typically, the channel will have a depth of from 4% to 99% of the thickness of the conductive substrate, and preferably the channel depth will be from 45% to 65% of the thickness of the conductive substrate. The platform 14 is shaped by an array pattern adapted to be coupled to an external circuit, such as a matching array of social pads on an external printed circuit board. As indicated above, to facilitate attachment to an external circuit board by soldering, the platform 14 may be surface trimmed or otherwise bonded with various solderable materials (such as solder paste, Sn, Ag, au, NiAu, etc.). As shown in Fig. 12, the first molding compound 18 is then placed in the passage of the separation platform 14. The first molding compound (typically a polymer molding resin) preferably fills the channels flush such that the platform 14 on the first side 12 becomes a wireless platform adapted for bonding to an external circuit. In this embodiment, the surface of the platform 14 is coplanar with the surface of the molding compound 18, and the surfaces include the flat first side surface 121 of the leadframe. Alternatively, the polymeric molding resin can be added to a depth slightly less than the depth of the channel such that the surface of the molded compound is recessed relative to the first side surface and the platform is provided with a avoidance distance between the package and the external printed circuit board. 157702.doc -15· 201225238 Preferably, the first molding compound 18 is non-conductive and preferably has a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 eC to 30 (TC). Alternatively, the first molding compound can be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a leadframe to a ceramic substrate in a CERpAK or cerdip package. This assembly can be supplied by a leadframe supplier. Supply to the package assembly plant for further processing' or the lead frame manufacturer can continue the process. As shown in Figure 12, the conductive substrate 10 has a second side 22 opposite the first side 12. The patterned side 22 is formed Routing circuit 26, as shown in Figure 13 and Figure i3B. Any suitable method can be used to pattern the conductive material such as chemical etching or laser ablation. Preferably, the chemically resistant material is applied to the pattern of the circuit. And then exposing the second side 22 to the etching solution to effectively remove sufficient conductive material to define the time of the routing circuit 26. As shown in Figures 13A and 13B, removed in the area between the routing circuits 26 foot The material is sufficient to expose the surface 120 of the molding compound 18, and the routing circuitry is coplanar with the surface 122 of the electrically conductive material. As best shown in Figure 13B, the leadframes in this embodiment thus have flat first side surfaces, respectively. 21 and a flat second side surface 122. In Figure 13B and other cross-sectional views, the conductive regions on the second side of the leadframe may appear to be in contact with each other. However, 'comparison with a corresponding plan view (e.g., Figure 13A) It will be appreciated that this is only an effect of viewing the regions on the edges. The regions that appear to be in contact are actually separated and located at different distances from the viewer. The wafer attachment site 124 is best shown in Figure 13A. The array is formed on the second side of the lead frame 157702.doc •16·201225238. The routing circuit 26 electrically interconnects the wafer attachment site 124 with the platform 14. The metal between the routing circuits is removed to attach the wafer to the site _ Routing Circuit - The individual combination of the platform is electrically isolated. In this embodiment, the wafer attachment site 124 is coplanar with the routing circuit 26; the wafer attachment post is not formed (compare Figure 5A and Figure 6 with Figure 13 and Figure 14) Chip The junction 124 is formed as an array that is effectively electrically interconnected directly to the input/output pads on the semiconductor device. The semiconductor device 28 is directly attached and electrically interconnected to the wafer attachment site 124, as shown in Figures 14A and 14B. By r direct, it is meant that the interconnect is by flip chip method without the use of an intervening wire bond or tape automated bonding (TAB) tape. The wafer attachment site 124 is placed in contact with the device 28 / The output pads are opposite and interconnected by interconnects 30. Suitable interconnects 3A include solder having a primary component selected from the group consisting of gold, tin, and mis (having 180 ° C and 240 ° C) The melting temperature in the range) the spacing between the beta semiconductor device 28 and the routing circuitry 26 is sufficient to allow the second molding compound to flow at both the top and bottom of the device 28. In this embodiment, the spacing is at least 25 microns. Referring to Figure 15, the second molding compound 36 then encapsulates the semiconductor device 28, the wafer attachment site 124, and the routing circuitry 26 to complete the package 138 for loading at least half of the conductor devices. Like the first molding compound 18, the second molding compound 36 is non-conductive, and is preferably a polymer molding resin having a flow temperature in the range of 25 Torr to 3 Torr. Epoxy resin). Alternatively, the second molding compound may also be a low temperature heat resistant glass composite (such as 157702.doc 17 201225238 low temperature heat resistant glass composite for attaching the lead frame to a ceramic substrate in a CERPAK or CERDIP package). The distance from the routing circuit 26 is at least about 25 microns; the space defined by the distance is filled with the second molding compound 36. The combination of the wafer attachment site 124, the routing circuit 26, and the platform 14 is referred to as a "redistribution lead frame" or rDlf in accordance with this embodiment. RDLF is formed from a single conductive substrate having a monomer structure. In the package 138 of this embodiment, the array of 'platforms 14' has a lateral extent L! greater than the lateral extent L2 of the array of wafer attachment sites ι 24 (see Figure 13 A). This type of package is a QFN (Four Flat Flat Wireless) flip chip package. The QFN package 138 has the same advantages as discussed above with reference to package 38, and additionally has the advantage of further reduced height and fewer processing steps. It will be appreciated that the RDLF of package 138 can also be used in a redistribution leadframe package (rdlp), similar to package 38 as discussed above and illustrated in Figures 8 through η. For example, an RDLP having a package 138 can be used in a wafer scale package (see Figure 8) where the lateral extents of the device 28, the array of wafer sites 124, and the array of platforms 14 are all substantially equal. Wire Bonded Wafer Package with Die Pad FIG. 16A through 18 illustrate the formation of a semiconductor package in accordance with another embodiment of the present invention. As in the embodiments described above, the conductive substrate is patterned into a lead frame for routing electrical wiring in a semiconductor package for mounting at least one semiconductor device. The conductive substrate 1 (formed from any suitable electrically conductive material, preferably copper or copper based alloy) has a first side that is partially patterned to form an array of platforms 14 separated by channels. The surface of each of the platforms 14 on the first side of 157702.doc •18·201225238 includes a portion of the first side surface 121 of the leadframe (see Figure 12). The channels can be formed by any controlled subtractive process such as chemical etching or laser ablation. For example, the portion of the first surface that is intended to form the platform 14 can be coated with a chemical resist and exposed to the appropriate surface for a suitable period of time to effectively form the channel. Typically, the channel will have a depth of from 4% to 99% of the thickness of the conductive substrate, and preferably, the channel depth will be from 45% to 65% of the thickness of the conductive substrate. The platform 14 is formed with an array pattern that is adapted to be bonded to an external circuit, such as an array of bond pads that match the external printed circuit board. As noted above, to facilitate attachment to an external circuit board by soldering, the platform 14 can be surface trimmed or plated with various solderable materials (such as solder paste, Sn, Ag, Au, NiAu, etc.). The first molding compound 18 is then placed in the passage of the separation platform 14. The first molding compound (typically a polymeric molding resin) preferably fills the channels flush so that the platform 14 on the first side becomes adapted for bonding. A non-wired platform for P circuits. In this embodiment, the surface of the platform crucible 4 is coplanar with the surface of the molding compound 18, and the surfaces include the flat first side surface 22 of the lead frame or the polymer molding resin can be added to the channel. The depth of the depth is such that the surface of the molding compound is concave with respect to the first side surface, and the platform has a distance between the package and the external printed circuit board. Preferably, the first molding compound i 8 is non-conductive. And preferably a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 ° C to 300 ° C. Alternatively, the first molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAK or CERDIP package. This assembly can be supplied by the leadframe supplier to the package assembly plant for further processing' or the lead frame manufacturer can continue the process. As in the embodiments described above, the conductive substrate 丨〇 has a second side opposite the first side. The second side is patterned to form a die pad 225 and routing circuitry 226, as shown in Figures 16A and 16B. The conductive material can be patterned using any suitable method, such as chemical surrogate or laser stripping. Preferably, the chemical resistant material is applied to the pattern of the circuit and then the second side is exposed to the etching solution to effectively remove sufficient conductive material to define the time of the beta θ 塾 225 and routing circuit 226. As shown in Figures 16A and 16B, sufficient material is removed between the die pad and the routing circuitry and between the routing circuitry to expose the surface 22 of the molding compound 18, while the die pad and routing The circuitry is coplanar with the surface 222 of the electrically conductive material. The lead frame in this embodiment as shown in Fig. 16B thus has a flat first side surface 221 and a flat second side surface 222, respectively. As best shown in Figure 16A, an array of wire bonding sites 224 is formed on the second side of the wireframe that is spaced from the die pad 225 and surrounds the die pad 225. Routing circuit 226 electrically interconnects wire bonding sites 224 and platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wire bonding sites - routing circuits - platforms. In this embodiment, the wire bonding site 224 is coplanar with the routing circuit 226. Wire bond site 224 is configured for electrical connection to an input/output pad on a semiconductor device. In particular, the wire bonding sites 224 can advantageously be surface trimmed or plated with materials useful to facilitate wire bonding (e.g., 157702.doc • 20·201225238)
Ag、NiPdAu、NiAu等）。 在此實施例中，晶粒墊佔用第二側表面之中心部分，且 平台與電線結合位點兩者配置於晶粒墊之周邊周圍。晶粒 墊女置於基板之無平台的中心部分。圖丨6C為此實施例中 之導線架之仰視圖；基板之對應於晶粒墊位置的部分具有 曝露之底表面214 ’且由平台14包圍（比較圖3A)。 半導體器件228直接附接至晶粒墊225，且藉由電線223 而電連接至電線結合位點224，如圖17A及圖17B中所示。 路由電路226可遵循多種不同路徑；此允許配置電線結合 位點224以便改良佈線佈局。 參看圖18，第二模製化合物36接著囊封半導體器件 228、電線結合位點224及路由電路226以完成用於裝入至 少一半導體器件之封裝238。與第一模製化合物18一樣， 第二模製化合物36為非導電的，且較佳為具有在25〇c>c至 3 00 C之範圍中之流動溫度的聚合物模製樹脂（諸如環氧樹 脂）。或者，第二模製化合物亦可為低溫耐熱玻璃複合物 (諸如用以將導線架附接至CERPAK或CERDIP封裝中之陶 瓷基底的低溫耐熱玻璃複合物 此實施例中之導線架係自作為單體結構之單一導電基板 所形成的再分配導線架（RDLF)。在此實施例之封裳238 中’平台14之陣列具有大於電線結合位點224之陣列之橫 向廣度L22的橫向廣度L2i(見圖16A)。此類型之封事為 QFN(四邊扁平無導線）封裝》 類似於上文所論述及圖9至圖11中所展示之封裝，封穿 157702.doc -21- 201225238 238之RDLF亦可用於再分配導線架封裝（RDLp)*。 具有額外電線結合位點之電線結合式晶片封裝 圖19 Α至圓21說明根據本發明之又一實施例之半導體封 裝的形成。如在上文所描述之實施例中，將導電基板1〇圖 案化為用以在用於裝入至少一半導體器件之半導體封裝中 路由電信號的導線架。導電基板1〇(自任何合適之導電材 料形成，較佳為銅或銅基合金）具有第一側，該第一側經 部刀圖案化以形成藉由通道分離之平台14之陣列。位於第 一側上之平台14中之每一者的表面包含導線架之第一側表 面121之一部分（見圖12)。可藉由任何受控之減式製程（諸 如化學蝕刻或雷射剝蝕）來形成通道。舉例而言，第一表 面之意欲形成平台14的部分可塗佈有化學抗蝕劑，且使第 一表面曝露至合適之蝕刻劑歷時有效地形成通道的時間。 通常’通道將具有為導電基板厚度之4〇%至99%的深度， 且較佳地’通道深度將為導電基板厚度之45%至65%。平 台14係以經調適以待結合至外部電路（諸如匹配外部印刷 電路板上之結合墊陣列）之陣列圖案而形成。如上文所指 出’為促進藉由焊接而與外部電路板的附接，平台14可經 表面修整或鍍有各種可焊接材料（諸如焊錫膏、Sll、Ag、 Au、NiAu等）。 接著將第一模製化合物18安置於分離平台14之通道内。 第一模製化合物（通常為聚合物模製樹脂）較佳齊平地填充 通道’使得位於第一側上之平台14變成經調適用於結合至 外。P電路之無導線平台。在此實施例中，平台丨4之表面與 157702.doc •22- 201225238 模製化合物18之表面共面，且該等表面包含導線架之平坦 第一側表面221。或者，可將聚合物模製樹脂添加至稍小 於通道之深度的深度，使得模製化合物之表面相對於第一 側表面而凹陷，且平台具備封裝與外部印刷電路板之間的 避開距離。 較佳地，第一模製化合物18為非導電的，且較佳為具有 在250°C至300°C之範圍中之流動溫度的聚合物模製樹脂 (諸如環氧樹脂）。或者，第一模製化合物可為低溫耐熱玻 璃複合物（諸如用以將導線架附接至CERPAk或CERDIP封 裝中之陶瓷基底的低溫耐熱玻璃複合物）。 成供 供進一 步處理’或導線架製造者可繼續該處理。 如在上文所描述之實施例中，導電基板1〇具有與第一側 對置之第二側。圖案化該第二側以形成包括電線結合位點 224之路由電路226 ’如圖19A及圖19B中所示。可使用任 何合適之方法來圖案化導電材料，諸如化學蝕刻或雷射剝 蝕。較佳地，將抗化學腐蝕材料塗覆於電路之圖案中，且 接著使第二側曝露至蝕刻溶液歷時有效地移除足夠之導電 材料以界定路由電路226的時間。如圖19A及圖19B中所 示如在先則所描述之實施例中，在晶粒塾與路由電路之 間及在路由電路之間的區域中移除足夠材料以曝露模製化 合物18之表面220,而晶粒墊與路由電路係與導電材料之 表面共面。如圖19β中最佳地展示，此實施例中之導線架 因此具有平坦第一側表面及平坦第二側表面。 157702.doc •23- 201225238 如圖19A中最佳地展示’電線結合位點224之陣列形成於 導線架之第二側上 路由電路226電互連電線結合位點224 與平台14。移除路由電路之間的金屬以使電線結合位點_ 路由電路-平台之個別組合電隔離。在此實施例中，電線 結合位點224與路由電路226共面》電線結合位點224經配 置用於電連接至半導體器件上之輸入/輸出墊。詳言之， 電線結合位點224可有利地經表面修整或鍍有用以促進電 線結合之材料（例如’ Ag、NiPdAu、NiAu等）。 在此實施例中，第二側表面聚集有產生至平台14之電連 接的電線結合位點224，其中該等平台係以規則陣列而配 置於第一側表面上（見圖19C)。相應地，一些路由電路在 第二侧表面之中心部分中具有曝露之金屬表面。非導電層 230覆蓋此等金屬表面，如圖2〇a中所示。層230可為非導 電環氧樹脂或非導電膏》電線結合位點224配置於由層23〇 覆蓋之區域的周邊周圍。 半導體器件228安置於層230上’且藉由電線223而電連 接至電線結合位點224，如圖20A及圖20B中所示。用於層 230之非導電材料可施配於第二側表面上，或替代地可在 附接器件之前將該非導電材料塗覆至器件之背側。 路由電路中之至少一者引導下面之器件228及層23〇與在 導線架之中心部分中的平台連接（比較圖19A及圖20A)。相 應地’此路由電路連接至位於器件下面之電導體（「主動 柱」），該電導體自導線架之第一側延伸至第二側。此配 置提供比先前實施例中之數目大的數目個電線結合位點 157702.doc •24· 201225238 (比較圖17A及圖20A)。相應地，此實施例之導線架提供較 大之I/O能力。 參看圖21 ’第二模製化合物36接著囊封半導體器件 228、電線結合位點224及路由電路226以完成用於裴入至 少一半導體器件之封裝248。與第一模製化合物18一樣， 第二模製化合物36為非導電的’且較佳為具有在25〇它至 3 00°C之範圍中之流動溫度的聚合物模製樹脂（諸如環氧樹 脂）。或者，第二模製化合物亦可為低溫耐熱玻璃複合物 (諸如用以將導線架附接至CERPAK或CERDIP封裝中之陶 瓷基底的低溫耐熱玻璃複合物）。 如在其他實施例中，此實施例中之導線架係自作為單體 結構之單一導電基板所形成的再分配導線架（rdlf)。在此 實施例之封裝248中，平台14之陣列具有大於或等於電線 結合位點224之陣列之橫向廣度的橫向廣度。此類型之封 裝為QFN(四邊扁平無導線）封裝。 類似於上文所論述及圖9至圖丨丨中所展示之封裝，封裝 248之RDLF亦可用於再分配導線架封裝（RDLp)中。 已描述本發明之若干實施例。儘管如此，將理解，可在 不脫離本發明之精神及範_的冑況下作出各種修改。因 此，其他實施例係在以下申請專利範圍之範疇内。 【圖式簡單說明】 圖1以橫截面表示來說明在圖案化為導線架之前的導電 基板。 圖2A以頂部平面圖說明且圖⑸以橫截面表示來說明在 157702.doc •25- 201225238 第一側上經部分地圖案化之導線架。 圖3 A以頂部平面圖說明且圖3 圃川以橫截面表示來說明具 有嵌入於聚合物模製樹脂中之料掛沾a 架 部分®案化之導線 圖4以橫截面表示來說 二側中形成導線柱。 明在經部分 圖案化之導線架之第 圖5A以頂部平面圖說明且圖⑼以橫截面表示來說明在 經部分圖案化之導線架之第二側中形成路由導線架特徵。 圖“以頂部平面圖說明且_以橫截面表示來說明半 導體器件至導線柱之附接。 圖7以橫截面表示來說明根據本發明之第一實施例之導 線架路由半導體封裝。 圖8以橫截面表示來說明根據本發明之晶片尺度封裝。 圖9以底部平面圖說明根據本發明之用於多器件封裝之 平台陣列。 圖10以頂部平面圖說明用於圖9之多器件封裝的晶片附 接位點陣列。 圖11以頂部平面圖說明具有附接之多個器件的圖9之晶 片附接位點陣列。 圖12以橫截面表示來說明根據另一實施例之包括如圖2Β 中所示之導電基板的導線架，其中平台及晶片附接位點位 於導線架之對置之第一側及第二側上。 圖13Α以頂部平面圖說明且圖13Β以橫截面表示來說明 根據本發明之一實施例的在圖〗2之經部分圖案化之導線架 157702.doc -26- 201225238 的第二側上形成路由導線架特徵，該等路由導線架特徵包 括路由電路及晶片附接位點。 圖14A以頂部平面圖說明且圖14B以橫截面表示來說明 半導體器件至圖13A及圖13B之導線架之晶片附接位點的 - 附接》 圖1 5以橫戴面表示來說明根據一實施例之導線架路由半 導體封裝，其中一模製化合物囊封圖丨4A及圖丨4B之半導 體器件、晶片附接位點及路由電路。 圖16A以頂部平面圖說明且圖16B以橫截面表示來說明 根據本發明之另一實施例的在經部分圖案化之導線架的第 一側上形成路由導線架特徵’該等路由導線架特徵包括路 由電路及晶粒墊。 圖16C以底部透視圖說明圖16A及圖16B之導線架。 圖17A以頂部平面圖說明且圖17B以橫截面表示來說明 半導體器件至圖16A及圖16B之晶粒塾及導線架的附接。 圖18以橫截面表示來說明根據一實施例之導線架路由半 導體封裝’其中一模製化合物囊封圖1 7A及圖17B之半導 體器件、晶粒墊及路由電路。 圖19A以頂部平面圖說明且圖19B以橫截面表示來說明 根據本發明之另一實施例的在經部分圖案化之導線架的第 二侧上形成路由導線架特徵，該等路由導線架特徵包括路 由電路。 圖19C以底部透視圖說明圖19A及圖19B之導線架。 圖20A以頂部平面圖說明且圖2〇b以橫截面表示來說明 157702.doc -27- 201225238 半導體器件至圖19A及圖19B之導線架的附接。 圖21以橫截面表示來說明根據一實施例之導線架路由半 導體封裝，其中一模製化合物囊封圖20A及圖20B之半導 體器件及路由電路。 【主要元件符號說明】 10 導電基板 12 導電基板之第一側 14 平台 14' 平台 14" 平台 16 通道 18 第一聚合物模製樹脂 20 導線架前驅物 22 導電基板之第二側 24 晶片附接位點 26 路由電路 28 半導體器件 28' 第二半導體器件 30 互連件 32 距離 34 晶片附接柱 36 第二模製化合物 38 封裝 40 晶片尺度封裝 157702.doc -28- 201225238 42 散熱片 44 晶粒塾 46 結合位點 48 電線結合件 50 電線結合墊 52 被動式器件 54 電互連 120 模製化合物之表面 121 導線架之平坦第一側表面 122 導線架之平坦第二側表面/導電材料之表面 124 晶片附接位點 138 封裝 214 底表面 220 模製化合物之表面 221 導線架之平坦第一側表面 222 導線架之平坦第二側表面/導電材料之表面 223 電線 224 電線結合位點 225 晶粒塾 226 路由電路 228 半導體器件 230 非導電層 s 238 封裝 248 封裝 157702.doc •29- 201225238 L, 橫向廣度 l2 橫向廣度 L21 橫向廣度 L22 橫向廣度 157702.docAg, NiPdAu, NiAu, etc.). In this embodiment, the die pad occupies a central portion of the second side surface, and both the platform and the wire bonding site are disposed around the periphery of the die pad. The die pad is placed in the centerless portion of the substrate. Figure 6C is a bottom plan view of the leadframe in this embodiment; the portion of the substrate corresponding to the location of the die pad has an exposed bottom surface 214' and is surrounded by the platform 14 (compare Figure 3A). The semiconductor device 228 is directly attached to the die pad 225 and is electrically connected to the wire bonding site 224 by wires 223, as shown in Figures 17A and 17B. Routing circuit 226 can follow a variety of different paths; this allows the wire to be coupled to site 224 to improve the routing layout. Referring to Figure 18, a second molding compound 36 then encapsulates semiconductor device 228, wire bonding sites 224, and routing circuitry 226 to complete package 238 for mounting at least one semiconductor device. Like the first molding compound 18, the second molding compound 36 is non-conductive, and is preferably a polymer molding resin (such as a ring having a flow temperature in the range of 25 ° C > c to 300 C) Oxygen resin). Alternatively, the second molding compound may also be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching the lead frame to a ceramic substrate in a CERPAK or CERDIP package. A redistribution lead frame (RDLF) formed by a single conductive substrate of the bulk structure. In the cover 238 of this embodiment, the array of 'platforms 14 has a lateral extent L2i greater than the lateral extent L22 of the array of wire bonding sites 224 (see Figure 16A). This type of package is a QFN (Four-Sided Flat Wireless Package) similar to the package described above and shown in Figures 9 through 11, which is also enclosed by RD 157702.doc -21 - 201225238 238 Can be used for redistribution leadframe package (RDLp)*. Wire bonded chip package with additional wire bonding sites. Figure 19 to circle 21 illustrate the formation of a semiconductor package in accordance with yet another embodiment of the present invention. In the depicted embodiment, the conductive substrate 1 is patterned into a leadframe for routing electrical signals in a semiconductor package for mounting at least one semiconductor device. Conductive substrate 1 (from any suitable guide The material is formed, preferably a copper or copper based alloy, having a first side patterned to form an array of platforms 14 separated by channels. Each of the platforms 14 on the first side The surface of the person includes a portion of the first side surface 121 of the lead frame (see Figure 12). The channel can be formed by any controlled subtractive process such as chemical etching or laser ablation. For example, the first surface The portion of the platform 14 that is intended to be formed may be coated with a chemical resist and expose the first surface to a suitable etchant for a time effective to form the channel. Typically the channel will have a thickness of 4% to 99 for the thickness of the conductive substrate. The depth of %, and preferably the 'channel depth will be 45% to 65% of the thickness of the conductive substrate. The platform 14 is an array that is adapted to be bonded to an external circuit, such as an array of bond pads that match an external printed circuit board. Formed as a pattern. As indicated above, 'to facilitate the attachment to an external circuit board by soldering, the platform 14 may be surface-finished or plated with various solderable materials (such as solder paste, Sll, Ag, Au, NiAu, etc.) Connect The first molding compound 18 is disposed within the passage of the separation platform 14. The first molding compound (typically a polymer molding resin) preferably fills the channel flush so that the platform 14 on the first side becomes adapted In the embodiment, the surface of the platform 丨4 is coplanar with the surface of the 157702.doc •22-201225238 molding compound 18, and the surfaces include the flattening of the lead frame One side surface 221. Alternatively, the polymer molding resin may be added to a depth slightly smaller than the depth of the channel such that the surface of the molding compound is recessed relative to the first side surface, and the platform is provided between the package and the external printed circuit board Avoid the distance. Preferably, the first molding compound 18 is non-conductive, and is preferably a polymer molding resin (such as an epoxy resin) having a flow temperature in the range of 250 °C to 300 °C. Alternatively, the first molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAk or CERDIP package. The supply is supplied for further processing' or the lead frame manufacturer can continue the process. As in the embodiments described above, the conductive substrate 1 has a second side opposite the first side. The second side is patterned to form routing circuitry 226' including wire bonding sites 224 as shown in Figures 19A and 19B. The conductive material can be patterned using any suitable method, such as chemical etching or laser ablation. Preferably, the chemical resistant material is applied to the pattern of circuitry and then the second side is exposed to the etching solution to effectively remove sufficient conductive material to define the routing circuit 226. As shown in the prior embodiments as shown in Figures 19A and 19B, sufficient material is removed in the region between the die and the routing circuitry and between the routing circuitry to expose the surface of the molding compound 18. 220, and the die pad and routing circuitry are coplanar with the surface of the conductive material. As best shown in Fig. 19, the lead frame in this embodiment thus has a flat first side surface and a flat second side surface. 157702.doc • 23- 201225238 As shown in FIG. 19A, an array of 'wire bonding sites 224' is formed on the second side of the leadframe. Routing circuitry 226 electrically interconnects the wire bonding sites 224 and the platform 14. The metal between the routing circuits is removed to electrically isolate the individual combinations of wire bonding sites _ routing circuits - platforms. In this embodiment, the wire bonding site 224 is coplanar with the routing circuit 226. The wire bonding site 224 is configured for electrical connection to an input/output pad on the semiconductor device. In particular, the wire bonding sites 224 can advantageously be surface trimmed or plated with materials useful to facilitate wire bonding (e.g., 'Ag, NiPdAu, NiAu, etc.). In this embodiment, the second side surface is gathered with wire bonding sites 224 that create electrical connections to the platform 14, wherein the platforms are disposed on the first side surface in a regular array (see Figure 19C). Accordingly, some routing circuits have exposed metal surfaces in a central portion of the second side surface. A non-conductive layer 230 covers the metal surfaces as shown in Figure 2A. Layer 230 can be a non-conductive epoxy or non-conductive paste. Wire bond sites 224 are disposed around the perimeter of the area covered by layer 23A. Semiconductor device 228 is disposed on layer 230 and is electrically coupled to wire bonding site 224 by wire 223, as shown in Figures 20A and 20B. The non-conductive material for layer 230 can be applied to the second side surface, or alternatively the non-conductive material can be applied to the back side of the device prior to attaching the device. At least one of the routing circuits directs the underlying device 228 and layer 23 to the platform in the central portion of the leadframe (compare Figures 19A and 20A). Correspondingly, the routing circuit is coupled to an electrical conductor ("active pillar") located beneath the device, the electrical conductor extending from the first side to the second side of the leadframe. This configuration provides a number of wire bonding sites 157702.doc • 24· 201225238 (compare Figures 17A and 20A) that are larger than the number in the previous embodiment. Accordingly, the lead frame of this embodiment provides greater I/O capability. Referring to Figure 21, a second molding compound 36 then encapsulates semiconductor device 228, wire bonding sites 224, and routing circuitry 226 to complete package 248 for intrusion into at least one semiconductor device. Like the first molding compound 18, the second molding compound 36 is non-conductive 'and preferably a polymer molding resin having a flow temperature in the range of 25 Torr to 300 ° C (such as epoxy) Resin). Alternatively, the second molding compound may be a low temperature heat resistant glass composite such as a low temperature heat resistant glass composite for attaching a lead frame to a ceramic substrate in a CERPAK or CERDIP package. As in other embodiments, the leadframe in this embodiment is a redistribution leadframe (rdlf) formed from a single conductive substrate that is a unitary structure. In package 248 of this embodiment, the array of platforms 14 has a lateral extent greater than or equal to the lateral extent of the array of wire bonding sites 224. This type of package is a QFN (four-sided flat no-wire) package. Similar to the package discussed above and illustrated in Figures 9 through ,, the RDLF of package 248 can also be used in a redistribution leadframe package (RDLp). Several embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conductive substrate before being patterned into a lead frame. Figure 2A is illustrated in a top plan view and Figure (5) is shown in cross-section to illustrate a partially patterned lead frame on the first side of 157702.doc • 25-201225238. Figure 3A is illustrated in a top plan view and Figure 3 is a cross-sectional view showing a wire having a material embedded in a polymer molding resin. Figure 4 is shown in cross section in two sides. Form a wire post. Figure 5A is illustrated in a top plan view and Figure (9) is shown in cross-section to illustrate the formation of routing leadframe features in the second side of the partially patterned leadframe. The figure is illustrated in a top plan view and is shown in cross-section to illustrate the attachment of a semiconductor device to a conductor post. Figure 7 is a cross-sectional view showing a lead frame routing semiconductor package in accordance with a first embodiment of the present invention. A cross-sectional representation is used to illustrate a wafer-scale package in accordance with the present invention. Figure 9 illustrates a platform array for a multi-device package in accordance with the present invention in a bottom plan view. Figure 10 illustrates a wafer attachment location for the multi-device package of Figure 9 in a top plan view. Point array. Figure 11 illustrates a wafer attachment site array of Figure 9 with a plurality of attached devices in a top plan view. Figure 12 is a cross-sectional view illustrating the inclusion of a conductive material as shown in Figure 2A, in accordance with another embodiment. a lead frame of a substrate, wherein the platform and the wafer attachment site are located on opposite first and second sides of the lead frame. Figure 13 is a top plan view and Figure 13 is a cross-sectional view illustrating one implementation in accordance with the present invention. Example of forming a routing leadframe feature on the second side of the partially patterned lead frame 157702.doc -26-201225238 of Figure 2, the routing leadframe features including the road The device and the wafer are attached to the site. Figure 14A is illustrated in a top plan view and Figure 14B is shown in cross-section to illustrate the attachment of the semiconductor device to the die attach site of the leadframe of Figures 13A and 13B. Figure 15 The cross-hatched representation is illustrative of a leadframe routing semiconductor package in accordance with an embodiment in which a molding compound encapsulates the semiconductor device, wafer attachment sites, and routing circuitry of Figures 4A and 4B. Figure 16A is illustrated in a top plan view 16B is a cross-sectional view illustrating the formation of a routing leadframe feature on a first side of a partially patterned leadframe in accordance with another embodiment of the present invention. The routing leadframe features include routing circuitry and die pads. Figure 16C illustrates the lead frame of Figures 16A and 16B in a bottom perspective view. Figure 17A is illustrated in a top plan view and Figure 17B is shown in cross-section to illustrate the attachment of the semiconductor device to the die and lead frame of Figures 16A and 16B. Figure 18 is a cross-sectional view showing a lead frame routing semiconductor package according to an embodiment in which a molding compound encapsulates the semiconductor device, die pad and routing circuit of Figures 17A and 17B 19A is illustrated in a top plan view and FIG. 19B is a cross-sectional view illustrating the formation of routing leadframe features on a second side of a partially patterned leadframe in accordance with another embodiment of the present invention, the routing leadframe features Figure 19C illustrates the leadframe of Figures 19A and 19B in a bottom perspective view. Figure 20A is illustrated in a top plan view and Figure 2B is illustrated in cross-section to illustrate 157702.doc -27-201225238 semiconductor device to Figure 19A and Figure 19B is a cross-sectional view illustrating a leadframe routing semiconductor package in accordance with an embodiment in which a molding compound encapsulates the semiconductor device and routing circuitry of Figures 20A and 20B. [Main component symbol description] 10 Conductive substrate 12 First side of conductive substrate 14 Platform 14' Platform 14" Platform 16 Channel 18 First polymer molding resin 20 Lead frame precursor 22 Second side of conductive substrate 24 Wafer attachment Site 26 Routing Circuit 28 Semiconductor Device 28' Second Semiconductor Device 30 Interconnect 32 Distance 34 Wafer Attachment Post 36 Second Molding Compound 38 Package 40 Wafer Scale Package 157702.doc -28- 201225238 42 Heat Sink 44 Grain塾46 bonding site 48 wire bond 50 wire bond pad 52 passive device 54 electrical interconnect 120 surface of molded compound 121 flat first side surface of lead frame 122 flat second side surface of lead frame / surface 124 of conductive material Wafer attachment site 138 package 214 bottom surface 220 surface of molding compound 221 flat first side surface of lead frame 222 flat second side surface of lead frame / surface 223 of conductive material wire 224 wire bonding site 225 grain 塾226 routing circuit 228 semiconductor device 230 non-conductive layer s 238 package 248 package 157702. Doc •29- 201225238 L, lateral breadth l2 lateral breadth L21 lateral breadth L22 lateral breadth 157702.doc