CN110112106A - 芯片封装模块及包含该芯片封装模块的电路板结构 - Google Patents

芯片封装模块及包含该芯片封装模块的电路板结构 Download PDF

Info

Publication number
CN110112106A
CN110112106A CN201810228369.6A CN201810228369A CN110112106A CN 110112106 A CN110112106 A CN 110112106A CN 201810228369 A CN201810228369 A CN 201810228369A CN 110112106 A CN110112106 A CN 110112106A
Authority
CN
China
Prior art keywords
chip
encapsulation module
layer
circuit
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810228369.6A
Other languages
English (en)
Inventor
黄馨仪
林育民
张道智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Publication of CN110112106A publication Critical patent/CN110112106A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4688Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13149Manganese [Mn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13157Cobalt [Co] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73259Bump and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1811Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开一种芯片封装模块及包含该芯片封装模块的电路板结构,该芯片封装模块包括模封层、芯片、基板以及多个盲孔电极。模封层具有第一表面及相对于第一表面的第二表面。芯片具有一第三表面及相对于第三表面的第四表面。芯片的第三表面设有金属凸块,其中芯片自模封层的第一表面埋入模封层并暴露金属凸块于第一表面。基板包括金属层,其中基板的金属层通过金属凸块与芯片接合。多个盲孔电极穿入模封层的第二表面与基板的金属层电连接。

Description

芯片封装模块及包含该芯片封装模块的电路板结构
技术领域
本发明涉及一种芯片封装模块及包含该芯片封装模块的电路板结构。
背景技术
在一般功率半导体的封装结构中,先将功率芯片通过焊锡材料组装至导线架上,再进行打线接合。然而,此打线接合方式并无助于元件散热,且可靠度不佳。目前,有业者将功率芯片以倒装方式通过焊锡材料组装至基板上。虽此方式可改善封装结构的电导性与热导性,然而,当有较大电流通过焊锡材料时,此不耐高电流作用的焊锡材料会于材料结构中产生孔洞状缺陷,而造成产品长期使用后或是可靠度测试过程中,焊锡材料所连接上、下元件间的断路。
因此,开发一种具有良好散热效能及耐高电流的封装结构是众所期待的。
发明内容
为解决现有技术的上述问题,本发明提供一种芯片封装模块,包括模封层、芯片、基板以及多个盲孔电极。模封层具有第一表面及相对于第一表面的第二表面。芯片具有一第三表面及相对于第三表面的第四表面。芯片的第三表面设有金属凸块,其中芯片自模封层的第一表面埋入模封层并暴露金属凸块于第一表面。基板包括金属层,其中基板的金属层通过金属凸块与芯片接合。多个盲孔电极穿入模封层的第二表面与基板的金属层电连接。
本发明还提供一种电路板结构,包括电路板以及如上所述的芯片封装模块。电路板具有一电路分布层,其中电路分布层至少设置在电路板的表面。如上所述的芯片封装模块,嵌于电路板中,其中芯片封装模块的多个盲孔电极的至少之一与电路板的电路分布层电连接。
本发明又提供一种芯片封装模块,包括模封层、芯片、基板以及多个穿孔电极。模封层具有第一表面及相对于第一表面的第二表面。芯片具有第三表面及相对于第三表面的第四表面。芯片的第三表面设有金属凸块,其中芯片自模封层的第一表面埋入模封层并暴露金属凸块于第一表面。基板包括金属层,其中基板的金属层通过金属凸块与芯片接合。多个穿孔电极穿过模封层与基板,并与基板的金属层电连接。
本发明再提供一种电路板结构,包括电路板以及如前段所述的芯片封装模块。电路板具有电路分布层,其中电路分布层至少设置在电路板的表面。如上所述的芯片封装模块,嵌于电路板中,其中芯片封装模块的多个穿孔电极的至少之一与电路板的电路分布层电连接。
基于上述,本发明以倒装(flip-chip)方式通过金属-金属接合将功率芯片组装至基板上,省去需要高精度对位的制作工艺步骤,且使整体电路设计更具弹性。本发明芯片封装结构中的基板是由高散热绝缘材料层与位于其上、下两侧的导热及/或导电金属层相互堆叠而成,且在芯片晶背处设置有专司(专门司职)散热功能的金属电极,将芯片产生的热随即传至外部。因此,本发明封装结构具有双面散热效能(分别自晶背与基板路径散热)。本发明一实施例的芯片与基板间的金属-金属接合材料可不含有焊锡成分,当有较大电流通过接合处时,由于接合结构中并不易产生如导致元件断路的孔洞状缺陷,相当有助于元件电性的稳定,具有耐高电流、高导电率、以及低阻抗的特性。本发明一实施例的电路板封装结构适用于大面积的异质整合量产。再者,本发明一实施例是将体积较小的芯片封装模块通过电路分布层的整合嵌入例如印刷电路板(PCB)的系统板中,遂使得整体封装结构的体积更加微缩,达到体积减薄的效果。
为让本发明更明显易懂,下文特举实施例,并配合所附的附图作详细说明如下。
附图说明
图1至图4为本发明的第一实施例的一种芯片封装模块的剖面示意图;
图5至图6为本发明的第一实施例的一种电路板结构的剖面示意图;
图7至图10为本发明的第二实施例的一种芯片封装模块的剖面示意图;
图11至图12为本发明的第二实施例的一种电路板结构的剖面示意图;
图13至图16为本发明的第三实施例的一种芯片封装模块的剖面示意图;
图17至图18为本发明的第三实施例的一种电路板结构的剖面示意图。
符号说明
10:芯片封装模块;
12:基板;
14:芯片;
15:底胶;
16:模封层;
18、122:盲孔电极;
20、24、28’、44、118:金属层;
22、30、34:金属凸块;
26:绝缘层;
28、104:电路分布层;
36、46:穿孔电极;
38:凹槽;
42、120、121:导热柱;
48:导热块;
100:电路板结构;
102:电路板;
106、116:散热装置;
108:耐压绝缘材;
110:散热片;
112:功能性芯片;
S1:第一表面;
S2:第二表面;
S3:第三表面;
S4:第四表面;
S5、S6:表面。
具体实施方式
有关本发明实施例的前述及其他技术内容,在以下配合参考附图的各实施例的详细说明中,将可清楚的呈现。以下实施例中所提到的方向用语,例如:「上」、「下」、「前」、「后」、「左」、「右」等,仅是参考附加附图的方向。因此,使用的方向用语是用来说明,而并非用来限制本发明。并且,在下列各实施例中,相同或相似的元件将采用相同或相似的标号。
图1至图4是本发明的第一实施例的一种芯片封装模块的剖面示意图。
请参照图1,在本实施例中,芯片封装模块10包括模封层16、芯片14以及基板12。模封层16具有第一表面S1以及相对于第一表面S1的第二表面S2。芯片14具有第三表面S3以及相对于第三表面S3的第四表面S4,且芯片14的第三表面S3设置至少一个金属凸块22,其中芯片14自模封层16的第一表面S1埋入模封层16并暴露金属凸块22于第一表面S1。基板12还包括金属层20,其中基板12的金属层20通过金属凸块22与芯片14接合。在部分实施例中,金属层20可为图案化金属层。芯片封装模块10还包括多个盲孔电极18位于该芯片14的周围的至少一侧,并穿入模封层16的第二表面S2与基板12的金属层20电连接。
在部分实施例中,芯片封装模块10的基板12可为覆铜陶瓷基板、电镀铜陶瓷基板、印刷电路板或铝基板,但本发明不以此为限。在本实施例中,基板12还包括金属层24与绝缘层26。金属层24相对于金属层20设置,绝缘层26设置于金属层20与金属层24之间。在部分实施例中,金属层20与金属层24可包括铜或铝或其他金属。在部分实施例中,绝缘层26可包括高散热绝缘材料,例如陶瓷材料的无机绝缘材料,或高分子材料混入高散热无机颗粒的有机绝缘材料。
在部分实施例中,芯片封装模块10的芯片14的金属凸块22的成分包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金。但在部分实施例中,金属凸块22不含焊锡成分。在本实施例中,芯片14可通过金属凸块22(例如:铜凸块)与基板12的金属层20(例如:铜金属层)接合,形成金属-金属(例如:铜-铜)结合,但本发明不限于此。
在部分实施例中,芯片封装模块10的芯片14为功率芯片,例如为应用于650伏特以上的功率芯片,但本发明不以此为限。在一些实施例中,芯片封装模块10的芯片14上设置的功率元件可为绝缘栅双极晶体管、氮化镓晶体管或金属氧化物半导体场效晶体管。
在部分实施例中,模封层16可包括绝缘材料。在本实施例中,在芯片14与基板12之间填入底胶15。在部分实施例中,底胶15可包括绝缘材料。底胶15与模封层16可为相同或不同材料。
在本实施例中,芯片封装模块10还包括电路分布层28,形成于模封层16与盲孔电极18上。在部分实施例中,盲孔电极18可包括例如铜或其他导电金属。芯片14通过基板12的金属层20经由盲孔电极18与电路分布层28电连接。
图2是本发明的第一实施例的一种芯片封装模块的剖面示意图。请参考图1与图2,本实施例的芯片封装模块10与图1的芯片封装模块10的差异在于:本实施例的芯片封装模块10以穿孔电极36置换图1的盲孔电极18。穿孔电极36贯穿模封层16与基板12。其中芯片14与基板12的金属层20的连接方式可包括如后述图3或图4的连接方式。在部分实施例中,穿孔电极36可包括例如铜或其他导电金属。芯片14通过基板12的金属层20经由穿孔电极36与芯片封装模块10的电路分布层28电连接。
图3是本发明的第一实施例的一种芯片封装模块的剖面示意图。请参照图1与图3,本实施例的芯片封装模块10与图1的芯片封装模块10的差异在于:本实施例的芯片封装模块10的芯片14与基板12的金属层20之间,还包括一金属凸块30,设置在基板12的金属层20与金属凸块22之间。芯片14可通过金属凸块22、金属凸块30与基板12的金属层20接合,其中金属凸块30的材料可包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金,但本发明不限于此。在部分实施例中,金属凸块30不含焊锡成分。
图4是本发明的第一实施例的一种芯片封装模块的剖面示意图。请参考图3与图4,本实施例的芯片封装模块10与图3的芯片封装模块10的差异在于:本实施例的芯片封装模块10的芯片14与基板12的金属层20之间,还包括一金属凸块34,设置在金属凸块30与金属凸块22之间。芯片14可通过金属凸块22、金属凸块34、金属凸块30与基板12的金属层20接合,其中金属凸块22与金属凸块30可为同质金属(例如:铜)。其中金属凸块34的材料可包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金,但本发明不限于此。在部分实施例中,金属凸块34不含焊锡成分。
本发明一实施例以倒装(flip-chip)方式通过金属-金属接合将功率芯片组装至基板上,省去需要高精度对位的制作工艺步骤,且使整体电路设计更具弹性。此外,本发明一实施例的芯片封装结构中位于芯片周围的盲孔(blind-hole)电极(或穿孔电极)也可用来制作成测试电路,以测试制作工艺中栅极与源极/漏极是否持续保持电性效能。
图5至图6是本发明的第一实施例的一种电路板结构的剖面示意图。
请参照图5,在本实施例中,电路板结构100可包括电路板102以及如图1、图2、图3或图4的芯片封装模块10,嵌于电路板102中,本实施例是以图1的芯片封装模块10为例。基板12的金属层24露出于电路板102。电路板102具有电路分布层104,设置在电路板102的表面S5上。芯片封装模块10的电路分布层28通过盲孔电极122与电路板102的电路分布层104电连接。在部分实施例中,盲孔电极122可包括例如铜或其他导电金属。在本实施例中,电路板结构100的电路分布层104设置在电路板102的表面S5,但本发明不以此为限。在其他实施例中,若以图2的芯片封装模块10为例,通过穿孔电极36的双向导电特性,电路分布层104可以设置在电路板102的表面S5与表面S6。
电路板结构100,还包括散热装置106,设置于基板12露出的金属层24上。散热装置106通过基板12露出的金属层24与芯片封装模块10热导通。在本实施例中,散热装置106由耐压绝缘材108与散热片110所构成。
在本实施例中,在电路板结构100的内部或外部可以进一步利用例如打线或其他电连接方式组装其他功能性芯片112,如图5所示。
图6是本发明的第一实施例的一种电路板结构的剖面示意图。请参照图5与图6,本实施例的电路板结构100与图5的电路板结构100的差异在于:本实施例的基板12的金属层24未露出于电路板102。亦即本实施例电路板结构100中的芯片封装模块10内埋于电路板102。金属层118设置于散热装置106与电路板102之间,金属层118利用导热柱120连接芯片封装模块10中的基板12的金属层24与散热装置106。在部分实施例中,导热柱120可包括例如铜、其他导热金属或其他导热材料。
图7至图10是本发明的第二实施例的一种芯片封装模块的剖面示意图。
请同时参照图1与图7,本实施例的芯片封装模块10与图1的芯片封装模块10的差异在于:本实施例的芯片封装模块10的芯片14的第四表面S4包括金属层44,芯片封装模块10还包括至少一凹槽38,凹槽38自模封层16的第二表面S2穿入。其中,至少一凹槽38中填充导热材料例如金属,以形成导热柱42。导热柱42连接芯片14的第四表面S4的金属层44与金属层28’。在本实施例中,芯片14产生的热可经由导热柱42上传至模封层16的第二表面S2并通过第二表面S2的金属层28’侧向传导。在部分实施例中,导热柱42可包括例如铜、其他导热金属或其他导热材料。在本实施例中,导热柱42由多个凹槽38所构成。在一实施例中,导热柱42也可为电性导通柱,金属层28’可为电路分布层。
在另一实施例中(图未绘示),芯片封装模块10可为如图7、图8、图9或图10的芯片封装模块10。其中,芯片封装模块10的芯片14的第四表面S4还包括一导电衬垫,芯片封装模块10包括至少一凹槽38。凹槽38中填充导电材料,自模封层16的第二表面S2穿入并电连接芯片14的导电衬垫与金属层28’。
图8是本发明的第二实施例的一种芯片封装模块的剖面示意图。请同时参照图7与图8,本实施例的芯片封装模块10与图7的芯片封装模块10的差异在于:本实施例的芯片封装模块10以穿孔电极36置换图7的盲孔电极18。穿孔电极36贯穿模封层16与基板12。其中芯片14与基板12的金属层20的连接方式可包括如后述图9或图10的连接方式。在部分实施例中,穿孔电极36可包括例如铜或其他导电金属。芯片14通过基板12的金属层20经由穿孔电极36与芯片封装模块10的金属层28’电连接。
图9是本发明的第二实施例的一种芯片封装模块的剖面示意图。请同时参照图7与图9,本实施例的芯片封装模块10与图7的芯片封装模块10的差异在于:本实施例的芯片封装模块10的芯片14与基板12的金属层20之间,还包括一金属凸块30,设置在基板12的金属层20与金属凸块22之间。芯片14可通过金属凸块22、金属凸块30与基板12的金属层20接合,其中金属凸块30的材料可包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金,但本发明不限于此。在部分实施例中,金属凸块30不含焊锡成分。
图10是本发明的第二实施例的一种芯片封装模块的剖面示意图。请同时参照图9与图10,本实施例的芯片封装模块10与图9的芯片封装模块10的差异在于:本实施例的芯片封装模块10的芯片14与基板12的金属层20之间,还包括一金属凸块34,设置在金属凸块30与金属凸块22之间。芯片14可通过金属凸块22、金属凸块34、金属凸块30与基板12的金属层20接合,其中金属凸块22与金属凸块30可为同质金属(例如:铜)。其中金属凸块34的材料可包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金,但本发明不限于此。在部分实施例中,金属凸块34不含焊锡成分。
图11至图12是本发明的第二实施例的一种电路板结构的剖面示意图。
请参照图11,在本实施例中,电路板结构100可包括电路板102以及如图7、图8、图9或图10所示的芯片封装模块10,嵌于电路板102中,本实施例是以图7的芯片封装模块10为例,并请同时参照图5与图11,本实施例的电路板结构100与图5的电路板结构100的差异在于:本实施例的电路板结构100还包括散热装置116相对于散热装置106,设置于电路板102的表面S5。芯片封装模块10还包括至少一凹槽38自芯片封装模块10的模封层16的第二表面S2穿入,其中凹槽38中填充导热材料以形成导热柱42。导热柱42连接芯片14的第四表面S4的金属层44与金属层28’。电路板结构100的电路分布层104,设置电路板102的表面S5,其中局部电路分布层104位于散热装置116与电路板102之间。散热装置116依序通过电路分布层104、导热柱121、金属层28’、导热柱42与芯片14的第四表面S4连接,可以将芯片14的热从晶背导出。在部分实施例中,导热柱121可包括例如铜、其他导热金属或其他导热材料。散热装置106与散热装置116由耐压绝缘材108与散热片110所构成。
图12是本发明的第二实施例的一种电路板结构的剖面示意图。请参照图11与图12,本实施例的电路板结构100与图11的电路板结构100的差异在于:本实施例的基板12的金属层24未露出于电路板102。亦即本实施例电路板结构100中的芯片封装模块10内埋于电路板102。金属层118设置于散热装置106与电路板102之间,金属层118利用导热柱120连接芯片封装模块10中的基板12的金属层24与散热装置106。
本发明第二实施例的电路板结构中的基板是由高散热绝缘材料层与位于其上、下两侧的导热及/或导电金属层相互堆叠而成,且于芯片的晶背处设置有专司散热功能的金属层,将芯片产生的热随即传至外部。因此,本发明一实施例的芯片封装结构具有双面散热效能(分别自晶背与基板双向散热)。
图13至图16是本发明的第三实施例的一种芯片封装模块的剖面示意图。
请同时参照图7与图13,本实施例的芯片封装模块10与图7的芯片封装模块10的差异在于:本实施例的芯片封装模块10的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
图14是本发明的第三实施例的一种芯片封装模块的剖面示意图。请同时参照图8与图14,本实施例的芯片封装模块10与图8的芯片封装模块10的差异在于:本实施例的芯片封装模块10的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
图15是本发明的第三实施例的一种芯片封装模块的剖面示意图。请同时参照图9与图15,本实施例的芯片封装模块10与图9的芯片封装模块10的差异在于:本实施例的芯片封装模块10的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
图16是本发明的第三实施例的一种芯片封装模块的剖面示意图。请同时参照图10与图16,本实施例的芯片封装模块10与图10的芯片封装模块10的差异在于:本实施例的芯片封装模块10的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
图17至图18是本发明的第三实施例的一种电路板结构的剖面示意图。
请参照图17,在本实施例中,电路板结构100可包括电路板102以及可为如图13、图14、图15或图16所示的芯片封装模块10,嵌于电路板102中,本实施例是以图13的芯片封装模块10为例,并请同时参照图11与图17,本实施例的电路板结构100与图11的电路板结构100的差异在于:本实施例的电路板结构100的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
图18是本发明的第三实施例的一种电路板结构的剖面示意图。请同时参照图12与图18,本实施例的电路板结构100与图12的电路板结构100的差异在于:本实施例的电路板结构100的凹槽38数量为一个。单一凹槽38内可填充包括例如铜、其他导热金属或其他导热材料以形成导热块48。
由于本发明一实施例的芯片与基板间的金属-金属接合材料可不含有焊锡成分,因此,即便有较大电流通过接合处时,在此材料结构中并不易产生导致元件断路的孔洞状缺陷,相当有助于元件电性的稳定,具有耐高电流、高导电率、以及低阻抗的特性。本发明一实施例的电路板封装结构适用于大面积的异质整合量产。再者,由于本发明是将体积较小的芯片封装模块通过电路分布层的整合嵌入例如印刷电路板(PCB)的系统板中,遂使得整体封装结构的体积更加微缩,达到体积减薄的效果。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (13)

1.一种芯片封装模块,其特征在于,包括:
模封层,具有第一表面及相对于该第一表面的第二表面;
芯片,具有第三表面及相对于该第三表面的第四表面,该芯片的该第三表面设有金属凸块,其中该芯片自该模封层的该第一表面埋入该模封层并暴露该金属凸块于该第一表面;
基板,包括金属层,其中该基板的该金属层通过该金属凸块与该芯片接合;以及
多个盲孔电极,穿入该模封层的该第二表面与该基板的该金属层电连接。
2.如权利要求1所述的芯片封装模块,其中该基板的该金属层包括铜、铝或其他金属。
3.如权利要求1所述的芯片封装模块,其中该芯片的该金属凸块包括焊锡合金、铜、银、铟、金、钯、钛、锰、钴或其合金。
4.如权利要求1所述的芯片封装模块,其中该芯片为功率芯片。
5.如权利要求4所述的芯片封装模块,其中该金属凸块不含焊锡成分。
6.如权利要求1所述的芯片封装模块,其中该芯片的第四表面包括金属层,该芯片封装模块还包括至少一凹槽,该凹槽自该模封层的该第二表面穿入,其中该至少一凹槽中填充导热材料并接触该芯片的该金属层。
7.如权利要求1所述的芯片封装模块,其中该芯片的第四表面还包括导电衬垫,该芯片封装模块还包括至少一凹槽,自该模封层的该第二表面穿入并电连接该芯片的该导电衬垫。
8.如权利要求1所述的芯片封装模块,其中该多个盲孔电极位于该芯片的周围的至少一侧。
9.一种电路板结构,其特征在于,包括:
电路板,具有电路分布层,其中该电路分布层至少设置在该电路板的一表面;以及
如权利要求1所述的芯片封装模块,嵌于该电路板中,其中该芯片封装模块的该多个盲孔电极的至少之一与该电路板的该电路分布层电连接。
10.如权利要求9所述的电路板结构,还包括:
散热装置,设置于该电路板的一表面,
其中,该芯片封装模块还包括至少一凹槽,自该芯片封装模块的该模封层的该第二表面穿入,该至少一凹槽中填充导热材料并接触该芯片的该第四表面,
其中,该散热装置热导通于该至少一凹槽。
11.如权利要求9所述的电路板结构,还包括:
散热装置,设置于该电路板的一表面,
其中,该散热装置位于该芯片封装模块的该模封层的该第一表面侧并与该芯片封装模块热导通。
12.一种芯片封装模块,其特征在于,包括:
模封层,具有第一表面及相对于该第一表面的第二表面;
芯片,具有第三表面及相对于该第三表面的第四表面,该芯片的该第三表面设有金属凸块,其中该芯片自该模封层的该第一表面埋入该模封层并暴露该金属凸块于该第一表面;
基板,包括金属层,其中该基板的该金属层通过该金属凸块与该芯片接合;以及
多个穿孔电极,穿过该模封层与该基板,并与该基板的该金属层电连接。
13.一种电路板结构,其特征在于,包括:
电路板,具有电路分布层,其中该电路分布层至少设置在该电路板的一表面;
如权利要求12所述的芯片封装模块,嵌于该电路板中,其中该芯片封装模块的该多个穿孔电极的至少之一与该电路板的该电路分布层电连接。
CN201810228369.6A 2018-02-01 2018-03-20 芯片封装模块及包含该芯片封装模块的电路板结构 Pending CN110112106A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107103628 2018-02-01
TW107103628A TWI658547B (zh) 2018-02-01 2018-02-01 晶片封裝模組及包含其之電路板結構

Publications (1)

Publication Number Publication Date
CN110112106A true CN110112106A (zh) 2019-08-09

Family

ID=67348091

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810228369.6A Pending CN110112106A (zh) 2018-02-01 2018-03-20 芯片封装模块及包含该芯片封装模块的电路板结构

Country Status (3)

Country Link
US (1) US10490473B2 (zh)
CN (1) CN110112106A (zh)
TW (1) TWI658547B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883431A (zh) * 2020-06-15 2020-11-03 珠海越亚半导体股份有限公司 一种具有高效散热结构的封装基板及其制造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102566772B1 (ko) * 2018-11-09 2023-08-14 삼성전자주식회사 반도체 패키지
TWI752398B (zh) * 2020-01-02 2022-01-11 財團法人工業技術研究院 功率模組
DE102020206769B3 (de) 2020-05-29 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Mikroelektronische anordnung und verfahren zur herstellung derselben
DE102020119849A1 (de) * 2020-07-28 2022-02-03 Infineon Technologies Ag Halbleitergehäuse und verfahren zur herstellung eines halbleitergehäuses
US11326836B1 (en) * 2020-10-22 2022-05-10 Asia Vital Components Co., Ltd. Vapor/liquid condensation system
DE102021105529A1 (de) * 2021-03-08 2022-09-08 Rogers Germany Gmbh Leiterplatte, Metall-Keramik-Substrat als Einsatz und Verfahren zur Herstellung eines solchen Einsatzes
US11862688B2 (en) * 2021-07-28 2024-01-02 Apple Inc. Integrated GaN power module
CN114530390B (zh) * 2022-04-22 2022-07-19 广东气派科技有限公司 改善双面散热器件应力问题的集成电路封装及制造方法
CN115799196B (zh) * 2023-02-07 2023-05-02 季华实验室 一种芯片封装结构、方法以及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649119A (zh) * 2004-01-27 2005-08-03 卡西欧计算机株式会社 半导体器件
CN101241868A (zh) * 2008-03-17 2008-08-13 日月光半导体制造股份有限公司 内埋半导体组件的封装工艺及封装结构
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
CN102456636A (zh) * 2010-10-19 2012-05-16 矽品精密工业股份有限公司 嵌入式芯片的封装件及其制造方法
CN104900634A (zh) * 2014-03-05 2015-09-09 台达电子国际(新加坡)私人有限公司 封装结构及其所适用的堆栈式封装模块
CN106653730A (zh) * 2015-10-28 2017-05-10 蔡亲佳 基于半导体芯片封装体的嵌入式封装结构及其封装方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI302732B (en) 2006-08-03 2008-11-01 Unimicron Technology Corp Embedded chip package process and circuit board with embedded chip
WO2009118925A1 (ja) * 2008-03-27 2009-10-01 イビデン株式会社 電子部品内蔵配線板及びその製造方法
US7935570B2 (en) 2008-12-10 2011-05-03 Stats Chippac, Ltd. Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US9059160B1 (en) 2010-12-23 2015-06-16 Marvell International Ltd. Semiconductor package assembly
US9385009B2 (en) * 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
CN103052281A (zh) * 2011-10-14 2013-04-17 富葵精密组件(深圳)有限公司 嵌入式多层电路板及其制作方法
KR101867489B1 (ko) 2012-06-20 2018-06-14 삼성전자주식회사 웨이퍼 레벨 패키지 형성방법
TWI508255B (zh) 2013-07-01 2015-11-11 Powertech Technology Inc 散熱型覆晶封裝構造
US9418877B2 (en) * 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US20160011833A1 (en) * 2014-07-08 2016-01-14 Panasonic Intellectual Property Corporation Of America Method and apparatus for controlling wireless print command
US9941207B2 (en) 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US9601472B2 (en) 2015-04-24 2017-03-21 Qualcomm Incorporated Package on package (POP) device comprising solder connections between integrated circuit device packages
TWI657552B (zh) * 2016-07-12 2019-04-21 財團法人工業技術研究院 晶片封裝以及複合型系統板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649119A (zh) * 2004-01-27 2005-08-03 卡西欧计算机株式会社 半导体器件
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
CN101241868A (zh) * 2008-03-17 2008-08-13 日月光半导体制造股份有限公司 内埋半导体组件的封装工艺及封装结构
CN102456636A (zh) * 2010-10-19 2012-05-16 矽品精密工业股份有限公司 嵌入式芯片的封装件及其制造方法
CN104900634A (zh) * 2014-03-05 2015-09-09 台达电子国际(新加坡)私人有限公司 封装结构及其所适用的堆栈式封装模块
CN106653730A (zh) * 2015-10-28 2017-05-10 蔡亲佳 基于半导体芯片封装体的嵌入式封装结构及其封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883431A (zh) * 2020-06-15 2020-11-03 珠海越亚半导体股份有限公司 一种具有高效散热结构的封装基板及其制造方法
CN111883431B (zh) * 2020-06-15 2021-09-21 珠海越亚半导体股份有限公司 一种具有高效散热结构的封装基板及其制造方法

Also Published As

Publication number Publication date
TWI658547B (zh) 2019-05-01
US10490473B2 (en) 2019-11-26
US20190237373A1 (en) 2019-08-01
TW201935632A (zh) 2019-09-01

Similar Documents

Publication Publication Date Title
CN110112106A (zh) 芯片封装模块及包含该芯片封装模块的电路板结构
US10128214B2 (en) Substrate and the method to fabricate thereof
TWI313504B (en) Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
CN1848308B (zh) 具有pptc层之间的有源元件的表面安装多层电路保护装置
KR101546081B1 (ko) 고전압, 고전력 어플리케이션들을 위한 격리된 히트 싱크를 가지는 리드없는 전력 쿼드 플랫 반도체 다이 패키지들, 그를 사용한 시스템들, 및 그 제조방법
DE10351934B4 (de) Leuchtdioden-Anordnung mit wärmeabführender Platine
CN101447442B (zh) 包括在基底上放置半导体芯片的制造装置的方法
CN104377172B (zh) 具有嵌入式无源部件的芯片封装件
US20190198424A1 (en) Power module with built-in power device and double-sided heat dissipation and manufacturing method thereof
US20220375833A1 (en) Substrate structures and methods of manufacture
TWI586004B (zh) 用於發光組件之電路及其製造方法
CN107204300A (zh) 用于制造芯片复合结构的方法
US20130062656A1 (en) Thermally enhanced optical package
JP2015005681A (ja) 半導体装置及びその製造方法
CN105321900A (zh) 用于集成电路封装的暴露的、可焊接的散热器
US20210143103A1 (en) Power module and method for manufacturing power module
CN105655304A (zh) 电子封装件及其制法
TW201907532A (zh) 半導體封裝結構及其製作方法
JP6809294B2 (ja) パワーモジュール
JP2016163024A (ja) パワーモジュール
TW201246581A (en) Integrated semiconductor solar cell package
JP2017123360A (ja) 半導体モジュール
CN204130525U (zh) 陶瓷基板和散热衬底的大功率led集成封装结构
CN105321901A (zh) 用于倒装芯片封装的暴露的、可焊接的散热器
CN111446230B (zh) 半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190809