TWI658547B - 晶片封裝模組及包含其之電路板結構 - Google Patents

晶片封裝模組及包含其之電路板結構 Download PDF

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Publication number
TWI658547B
TWI658547B TW107103628A TW107103628A TWI658547B TW I658547 B TWI658547 B TW I658547B TW 107103628 A TW107103628 A TW 107103628A TW 107103628 A TW107103628 A TW 107103628A TW I658547 B TWI658547 B TW I658547B
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Taiwan
Prior art keywords
circuit board
layer
chip
wafer
chip package
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TW107103628A
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English (en)
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TW201935632A (zh
Inventor
黃馨儀
林育民
張道智
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財團法人工業技術研究院
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Priority to TW107103628A priority Critical patent/TWI658547B/zh
Priority to CN201810228369.6A priority patent/CN110112106A/zh
Priority to US15/955,527 priority patent/US10490473B2/en
Application granted granted Critical
Publication of TWI658547B publication Critical patent/TWI658547B/zh
Publication of TW201935632A publication Critical patent/TW201935632A/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一種晶片封裝模組，其包括模封層、晶片、基板以及複數個盲孔電極。模封層具有第一表面及相對於第一表面的第二表面。晶片具有一第三表面及相對於第三表面的第四表面。晶片的第三表面設有金屬凸塊，其中晶片自模封層的第一表面埋入模封層並暴露金屬凸塊於第一表面。基板包括金屬層，其中基板的金屬層透過金屬凸塊與晶片接合。複數個盲孔電極穿入模封層的第二表面與基板的金屬層電性連接。一種包括上述晶片封裝模組之電路板結構亦被提出。

Description

晶片封裝模組及包含其之電路板結構
本發明是有關於一種晶片封裝模組及包含其之電路板結構。
在一般功率半導體的封裝結構中，係先將功率晶片藉由焊錫材料組裝至導線架上，再進行打線接合。然而，此打線接合方式並無助於元件散熱，且可靠度不佳。目前，有業者將功率晶片以覆晶方式藉由焊錫材料組裝至基板上。雖此方式可改善封裝結構的電導性與熱導性，然而，當有較大電流通過焊錫材料時，此不耐高電流作用的焊錫材料會於材料結構中產生孔洞狀缺陷，而造成產品長期使用後或是可靠度測試過程中，焊錫材料所連接上、下元件間的斷路。
因此，開發一種具有良好散熱效能及耐高電流的封裝結構是眾所期待的。
本發明一實施例的一種晶片封裝模組，包括模封層、晶片、基板以及複數個盲孔電極。模封層具有第一表面及相對於第一表面的第二表面。晶片具有一第三表面及相對 於第三表面的第四表面。晶片的第三表面設有金屬凸塊，其中晶片自模封層的第一表面埋入模封層並暴露金屬凸塊於第一表面。基板包括金屬層，其中基板的金屬層透過金屬凸塊與晶片接合。複數個盲孔電極穿入模封層的第二表面與基板的金屬層電性連接。
本發明一實施例的一種電路板結構，包括電路板以及如上所述的晶片封裝模組。電路板具有一電路分佈層，其中電路分佈層至少設置在電路板的表面。如上所述的晶片封裝模組，嵌於電路板中，其中晶片封裝模組的複數個盲孔電極的至少之一與電路板的電路分佈層電性連接。
本發明一實施例的一種晶片封裝模組，包括模封層、晶片、基板以及複數個穿孔電極。模封層具有第一表面及相對於第一表面的第二表面。晶片具有第三表面及相對於第三表面的第四表面。晶片的第三表面設有金屬凸塊，其中晶片自模封層的第一表面埋入模封層並暴露金屬凸塊於第一表面。基板包括金屬層，其中基板的金屬層透過金屬凸塊與晶片接合。複數個穿孔電極穿過模封層與基板，並與基板的金屬層電性連接。
本發明一實施例的一種電路板結構，包括電路板以及如前段所述之晶片封裝模組。電路板具有電路分佈層，其中電路分佈層至少設置在電路板的表面。如上所述的晶片封裝模組，嵌於電路板中，其中晶片封裝模組的複數個穿孔 電極的至少之一與電路板的電路分佈層電性連接。
本發明之一實施例以覆晶(flip-chip)方式藉由銅-銅接合或銅-金屬層-銅接合將功率晶片組裝至基板上，省去需要高精度對位的製程步驟，且使整體電路設計更具彈性。本發明一實施例之晶片封裝結構中的基板係由高散熱絕緣材料層與位於其上、下兩側的導熱及/或導電金屬層相互堆疊而成，且於晶片晶背處設置有專司散熱功能的金屬電極，將晶片產生的熱隨即傳至外部。因此，本發明封裝結構具有雙面散熱效能(分別自晶背與基板路徑散熱)。本發明一實施例之晶片與基板間的金屬-金屬接合材料可不含有焊錫成分，當有較大電流通過接合處時，由於接合結構中並不易產生如導致元件斷路的孔洞狀缺陷，相當有助於元件電性的穩定，具有耐高電流、高導電率、以及低阻抗的特性。本發明一實施例之電路板封裝結構適用於大面積的異質整合量產。再者，本發明一實施例係將體積較小的晶片封裝模組透過電路分佈層的整合嵌入例如印刷電路板(PCB)的系統板中，遂使得整體封裝結構的體積更加微縮，達到體積減薄的效果。
為讓本發明更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧晶片封裝模組
12‧‧‧基板
14‧‧‧晶片
15‧‧‧底膠
16‧‧‧模封層
18、122‧‧‧盲孔電極
20、24、28’、44、118‧‧‧金屬層
22、30、34‧‧‧金屬凸塊
26‧‧‧絕緣層
28、104‧‧‧電路分佈層
36、46‧‧‧穿孔電極
38‧‧‧凹槽
42、120、121‧‧‧導熱柱
48‧‧‧導熱塊
100‧‧‧電路板結構
102‧‧‧電路板
106、116‧‧‧散熱裝置
108‧‧‧耐壓絕緣材
110‧‧‧散熱片
112‧‧‧功能性晶片
S1‧‧‧第一表面
S2‧‧‧第二表面
S3‧‧‧第三表面
S4‧‧‧第四表面
S5、S6‧‧‧表面
圖1至圖4是依照本發明的第一實施例的一種晶片封裝 模組的剖面示意圖。
圖5至圖6是依照本發明的第一實施例的一種電路板結構的剖面示意圖。
圖7至圖10是依照本發明的第二實施例的一種晶片封裝模組的剖面示意圖。
圖11至圖12是依照本發明的第二實施例的一種電路板結構的剖面示意圖。
圖13至圖16是依照本發明的第三實施例的一種晶片封裝模組的剖面示意圖。
圖17至圖18是依照本發明的第三實施例的一種電路板結構的剖面示意圖。
有關本揭露實施例之前述及其他技術內容，在以下配合參考圖式之各實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明，而並非用來限制本揭露。並且，在下列各實施例中，相同或相似的元件將採用相同或相似的標號。
圖1至圖4是依照本發明的第一實施例的一種晶片封裝模組的剖面示意圖。
請參照圖1，在本實施例中，晶片封裝模組10包 括模封層16、晶片14以及基板12。模封層16具有第一表面S1以及相對於第一表面S1的第二表面S2。晶片14具有第三表面S3以及相對於第三表面S3的第四表面S4，且晶片14的第三表面S3設置至少一個金屬凸塊22，其中晶片14自模封層16的第一表面S1埋入模封層16並暴露金屬凸塊22於第一表面S1。基板12還包括金屬層20，其中基板12的金屬層20透過金屬凸塊22與晶片14接合。在部分實施例中，金屬層20可為圖案化金屬層。晶片封裝模組10還包括複數個盲孔電極18位於該晶片14的周圍的至少一側，並穿入模封層16的第二表面S2與基板12的金屬層20電性連接。
在部分實施例中，晶片封裝模組10之基板12可為覆銅陶瓷基板、電鍍銅陶瓷基板、印刷電路板或鋁基板，但本發明不以此為限。在本實施例中，基板12更包括金屬層24與絕緣層26。金屬層24相對於金屬層20設置，絕緣層26設置於金屬層20與金屬層24之間。在部分實施例中，金屬層20與金屬層24可包括銅或鋁或其他金屬。在部分實施例中，絕緣層26可包括高散熱絕緣材料，例如陶瓷材料的無機絕緣材料，或高分子材料混入高散熱無機顆粒的有機絕緣材料。
在部分實施例中，晶片封裝模組10之晶片14的金屬凸塊22的成分包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金。但在部分實施例中，金屬凸塊22不含焊錫成分。在本實施例中，晶片14可藉由金屬凸塊22(例如：銅凸 塊)與基板12的金屬層20(例如：銅金屬層)接合，形成金屬-金屬(例如：銅-銅)結合，但本發明不限於此。
在部分實施例中，晶片封裝模組10之晶片14為功率晶片，例如為應用於650伏特以上的功率晶片，但本發明不以此為限。在一些實施例中，晶片封裝模組10之晶片14上設置的功率元件可為絕緣柵雙極電晶體、氮化鎵電晶體或金屬氧化物半導體場效電晶體。
在部分實施例中，模封層16可包括絕緣材料。在本實施例中，於晶片14與基板12之間填入底膠15。在部分實施例中，底膠15可包括絕緣材料。底膠15與模封層16可為相同或不同材料。
在本實施例中，晶片封裝模組10更包括電路分佈層28，形成於模封層16與盲孔電極18上。在部分實施例中，盲孔電極18可包括例如銅或其他導電金屬。晶片14透過基板12的金屬層20經由盲孔電極18與電路分佈層28電性連接。
圖2是依照本發明的第一實施例的一種晶片封裝模組的剖面示意圖。請參考圖1與圖2，本實施例的晶片封裝模組10與圖1的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10以穿孔電極36置換圖1的盲孔電極18。穿孔電極36貫穿模封層16與基板12。其中晶片14與基板12的金屬層20之連接方式可包括如後述圖3或圖4的連接方式。在部分實施例中，穿孔電極36可包括例如銅或其他導電金屬。晶片14透過 基板12的金屬層20經由穿孔電極36與晶片封裝模組10的電路分佈層28電性連接。
圖3是依照本發明的第一實施例的一種晶片封裝模組的剖面示意圖。請參照圖1與圖3，本實施例的晶片封裝模組10與圖1的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10的晶片14與基板12的金屬層20之間，更包括一金屬凸塊30，設置在基板12的金屬層20與金屬凸塊22之間。晶片14可藉由金屬凸塊22、金屬凸塊30與基板12的金屬層20接合，其中金屬凸塊30的材料可包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金，但本發明不限於此。在部分實施例中，金屬凸塊30不含焊錫成分。
圖4是依照本發明的第一實施例的一種晶片封裝模組的剖面示意圖。請參考圖3與圖4，本實施例的晶片封裝模組10與圖3的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10的晶片14與基板12的金屬層20之間，更包括一金屬凸塊34，設置在金屬凸塊30與金屬凸塊22之間。晶片14可藉由金屬凸塊22、金屬凸塊34、金屬凸塊30與基板12的金屬層20接合，其中金屬凸塊22與金屬凸塊30可為同質金屬(例如：銅)。其中金屬凸塊34的材料可包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金，但本發明不限於此。在部分實施例中，金屬凸塊34不含焊錫成分。
本發明一實施例以覆晶(flip-chip)方式藉由金屬- 金屬接合將功率晶片組裝至基板上，省去需要高精度對位的製程步驟，且使整體電路設計更具彈性。此外，本發明一實施例之晶片封裝結構中位於晶片周圍的盲孔(blind-hole)電極(或穿孔電極)亦可用來製作成測試電路，以測試製程中閘極與源極/汲極是否持續保持電性效能。
圖5至圖6是依照本發明的第一實施例的一種電路板結構的剖面示意圖。
請參照圖5，在本實施例中，電路板結構100可包括電路板102以及如圖1、圖2、圖3或圖4之晶片封裝模組10，嵌於電路板102中，本實施例是以圖1之晶片封裝模組10為例。基板12的金屬層24露出於電路板102。電路板102具有電路分佈層104，設置在電路板102的表面S5上。晶片封裝模組10的電路分佈層28透過盲孔電極122與電路板102的電路分佈層104電性連接。在部分實施例中，盲孔電極122可包括例如銅或其他導電金屬。在本實施例中，電路板結構100的電路分佈層104設置在電路板102的表面S5，但本發明不以此為限。在其他實施例中，若以圖2的晶片封裝模組10為例，藉由穿孔電極36之雙向導電特性，電路分佈層104可以設置在電路板102的表面S5與表面S6。
電路板結構100，更包括散熱裝置106，設置於基板12露出的金屬層24上。散熱裝置106透過基板12露出的金屬層24與晶片封裝模組10熱導通。在本實施例中，散熱裝置106 由耐壓絕緣材108與散熱片110所構成。
在本實施例中，於電路板結構100的內部或外部可以進一步利用例如打線或其他電性連接方式組裝其他功能性晶片112，如第5圖所示。
圖6是依照本發明的第一實施例的一種電路板結構的剖面示意圖。請參照圖5與圖6，本實施例的電路板結構100與圖5的電路板結構100的差異在於：本實施例的基板12的金屬層24未露出於電路板102。亦即本實施例電路板結構100中的晶片封裝模組10內埋於電路板102。金屬層118設置於散熱裝置106與電路板102之間，金屬層118利用導熱柱120連接晶片封裝模組10中的基板12的金屬層24與散熱裝置106。在部分實施例中，導熱柱120可包括例如銅、其他導熱金屬或其他導熱材料。
圖7至圖10是依照本發明的第二實施例的一種晶片封裝模組的剖面示意圖。
請同時參照圖1與圖7，本實施例的晶片封裝模組10與圖1的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10之晶片14的第四表面S4包括金屬層44，晶片封裝模組10更包括至少一凹槽38，凹槽38自模封層16的第二表面S2穿入。其中，至少一凹槽38中填充導熱材料例如金屬，以形成導熱柱42。導熱柱42連接晶片14的第四表面S4的金屬層44與金屬層28’。在本實施例中，晶片14產生的熱可經由導熱柱42 上傳至模封層16的第二表面S2並透過第二表面S2的金屬層28’側向傳導。在部分實施例中，導熱柱42可包括例如銅、其他導熱金屬或其他導熱材料。在本實施例中，導熱柱42由複數個凹槽38所構成。在一實施例中，導熱柱42亦可為電性導通柱，金屬層28’可為電路分佈層。
在另一實施例中(圖未繪示)，晶片封裝模組10可為如圖7、圖8、圖9或圖10之晶片封裝模組10。其中，晶片封裝模組10之晶片14的第四表面S4更包括一導電襯墊，晶片封裝模組10包括至少一凹槽38。凹槽38中填充導電材料，自模封層16的第二表面S2穿入並電性連接晶片14的導電襯墊與金屬層28’。
圖8是依照本發明的第二實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖7與圖8，本實施例的晶片封裝模組10與圖7的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10以穿孔電極36置換圖7的盲孔電極18。穿孔電極36貫穿模封層16與基板12。其中晶片14與基板12的金屬層20之連接方式可包括如後述圖9或圖10的連接方式。在部分實施例中，穿孔電極36可包括例如銅或其他導電金屬。晶片14透過基板12的金屬層20經由穿孔電極36與晶片封裝模組10的金屬層28’電性連接。
圖9是依照本發明的第二實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖7與圖9，本實施例的晶片 封裝模組10與圖7的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10的晶片14與基板12的金屬層20之間，更包括一金屬凸塊30，設置在基板12的金屬層20與金屬凸塊22之間。晶片14可藉由金屬凸塊22、金屬凸塊30與基板12的金屬層20接合，其中金屬凸塊30的材料可包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金，但本發明不限於此。在部分實施例中，金屬凸塊30不含焊錫成分。
圖10是依照本發明的第二實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖9與圖10，本實施例的晶片封裝模組10與圖9的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10的晶片14與基板12的金屬層20之間，更包括一金屬凸塊34，設置在金屬凸塊30與金屬凸塊22之間。晶片14可藉由金屬凸塊22、金屬凸塊34、金屬凸塊30與基板12的金屬層20接合，其中金屬凸塊22與金屬凸塊30可為同質金屬(例如：銅)。其中金屬凸塊34的材料可包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金，但本發明不限於此。在部分實施例中，金屬凸塊34不含焊錫成分。
圖11至圖12是依照本發明的第二實施例的一種電路板結構的剖面示意圖。
請參照圖11，在本實施例中，電路板結構100可包括電路板102以及如圖7、圖8、圖9或圖10所示的晶片封裝模組10，嵌於電路板102中，本實施例是以圖7的晶片封裝模 組10為例，並請同時參照圖5與圖11，本實施例的電路板結構100與圖5的電路板結構100的差異在於：本實施例的電路板結構100更包括散熱裝置116相對於散熱裝置106，設置於電路板102的表面S5。晶片封裝模組10更包括至少一凹槽38自晶片封裝模組10的模封層16的第二表面S2穿入，其中凹槽38中填充導熱材料以形成導熱柱42。導熱柱42連接晶片14的第四表面S4的金屬層44與金屬層28’。電路板結構100的電路分佈層104，設置電路板102的表面S5，其中局部電路分佈層104位於散熱裝置116與電路板102之間。散熱裝置116依序透過電路分佈層104、導熱柱121、金屬層28’、導熱柱42與晶片14的第四表面S4連接，可以將晶片14的熱從晶背導出。在部分實施例中，導熱柱121可包括例如銅、其他導熱金屬或其他導熱材料。散熱裝置106與散熱裝置116由耐壓絕緣材108與散熱片110所構成。
圖12是依照本發明的第二實施例的一種電路板結構的剖面示意圖。請參照圖11與圖12，本實施例的電路板結構100與圖11的電路板結構100的差異在於：本實施例的基板12的金屬層24未露出於電路板102。亦即本實施例電路板結構100中的晶片封裝模組10內埋於電路板102。金屬層118設置於散熱裝置106與電路板102之間，金屬層118利用導熱柱120連接晶片封裝模組10中的基板12的金屬層24與散熱裝置106。
本發明第二實施例之電路板結構中的基板係由 高散熱絕緣材料層與位於其上、下兩側的導熱及/或導電金屬層相互堆疊而成，且於晶片的晶背處設置有專司散熱功能的金屬層，將晶片產生的熱隨即傳至外部。因此，本發明一實施例之晶片封裝結構具有雙面散熱效能(分別自晶背與基板雙向散熱)。
圖13至圖16是依照本發明的第三實施例的一種晶片封裝模組的剖面示意圖。
請同時參照圖7與圖13，本實施例的晶片封裝模組10與圖7的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊48。
圖14是依照本發明的第三實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖8與圖14，本實施例的晶片封裝模組10與圖8的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊48。
圖15是依照本發明的第三實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖9與圖15，本實施例的晶片封裝模組10與圖9的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊 48。
圖16是依照本發明的第三實施例的一種晶片封裝模組的剖面示意圖。請同時參照圖10與圖16，本實施例的晶片封裝模組10與圖10的晶片封裝模組10的差異在於：本實施例的晶片封裝模組10之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊48。
圖17至圖18是依照本發明的第三實施例的一種電路板結構的剖面示意圖。
請參照圖17，在本實施例中，電路板結構100可包括電路板102以及可為如圖13、圖14、圖15或圖16所示的晶片封裝模組10，嵌於電路板102中，本實施例是以圖13的晶片封裝模組10為例，並請同時參照圖11與圖17，本實施例的電路板結構100與圖11的電路板結構100的差異在於：本實施例的電路板結構100之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊48。
圖18是依照本發明的第三實施例的一種電路板結構的剖面示意圖。請同時參照圖12與圖18，本實施例的電路板結構100與圖12的電路板結構100的差異在於：本實施例的電路板結構100之凹槽38數量為一個。單一凹槽38內可填充包括例如銅、其他導熱金屬或其他導熱材料以形成導熱塊48。
由於本發明一實施例之晶片與基板間的金屬-金 屬接合材料可不含有焊錫成分，因此，即便有較大電流通過接合處時，於此材料結構中並不易產生導致元件斷路的孔洞狀缺陷，相當有助於元件電性的穩定，具有耐高電流、高導電率、以及低阻抗的特性。本發明一實施例之電路板封裝結構適用於大面積的異質整合量產。再者，由於本發明係將體積較小的晶片封裝模組透過電路分佈層的整合嵌入例如印刷電路板(PCB)的系統板中，遂使得整體封裝結構的體積更加微縮，達到體積減薄的效果。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (13)

  1. 一種晶片封裝模組，包括：一模封層，具有一第一表面及相對於該第一表面的一第二表面；一晶片，具有一第三表面及相對於該第三表面的一第四表面，該晶片的該第三表面設有一金屬凸塊，其中該晶片自該模封層的該第一表面埋入該模封層並暴露該金屬凸塊與該晶片的至少部分該第三表面於該模封層的該第一表面；一基板，包括一金屬層，其中該基板的該金屬層透過該金屬凸塊與該晶片接合；以及複數個盲孔電極，穿入該模封層的該第二表面與該基板的該金屬層電性連接。
  2. 如申請專利範圍第1項所述的晶片封裝模組，其中該基板的該金屬層包括銅或鋁。
  3. 如申請專利範圍第1項所述的晶片封裝模組，其中該晶片的該金屬凸塊包括焊錫合金、銅、銀、銦、金、鈀、鈦、錳、鈷或其合金。
  4. 如申請專利範圍第1項所述的晶片封裝模組，其中該晶片為功率晶片。
  5. 如申請專利範圍第4項所述的晶片封裝模組，其中該金屬凸塊不含焊錫成分。
  6. 如申請專利範圍第1項所述的晶片封裝模組，其中該晶片的第四表面包括一金屬層，該晶片封裝模組更包括至少一凹槽，該凹槽自該模封層的該第二表面穿入，其中該至少一凹槽中填充導熱材料並接觸該晶片的該金屬層。
  7. 如申請專利範圍第1項所述的晶片封裝模組，其中該晶片的第四表面更包括一導電襯墊，該晶片封裝模組更包括至少一凹槽，自該模封層的該第二表面穿入並電性連接該晶片的該導電襯墊。
  8. 如申請專利範圍第1項所述的晶片封裝模組，其中該複數個盲孔電極位於該晶片的周圍的至少一側。
  9. 一種電路板結構，包括：一電路板，具有一電路分佈層，其中該電路分佈層至少設置在該電路板的一表面；以及一如申請專利範圍第1項所述的晶片封裝模組，嵌於該電路板中，其中該晶片封裝模組的該複數個盲孔電極的至少之一與該電路板的該電路分佈層電性連接。
  10. 如申請專利範圍第9項所述的電路板結構，更包括：一散熱裝置，設置於該電路板的一表面，其中，該晶片封裝模組更包括至少一凹槽，自該晶片封裝模組的該模封層的該第二表面穿入，該至少一凹槽中填充導熱材料並接觸該晶片的該第四表面，其中，該散熱裝置熱導通於該至少一凹槽。
  11. 如申請專利範圍第9項所述的電路板結構，更包括：一散熱裝置，設置於該電路板的一表面，其中，該散熱裝置位於該晶片封裝模組的該模封層的該第一表面側並與該晶片封裝模組熱導通。
  12. 一種晶片封裝模組，包括：一模封層，具有一第一表面及相對於該第一表面的一第二表面；一晶片，具有一第三表面及相對於該第三表面的一第四表面，該晶片的該第三表面設有一金屬凸塊，其中該晶片自該模封層的該第一表面埋入該模封層並暴露該金屬凸塊於該第一表面；一基板，包括一金屬層，其中該基板的該金屬層透過該金屬凸塊與該晶片接合；以及複數個穿孔電極，穿過該模封層與該基板，並與該基板的該金屬層電性連接。
  13. 一種電路板結構，包括：一電路板，具有一電路分佈層，其中該電路分佈層至少設置在該電路板的一表面；一如申請專利範圍第12項所述的晶片封裝模組，嵌於該電路板中，其中該晶片封裝模組的該複數個穿孔電極的至少之一與該電路板的該電路分佈層電性連接。
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