CN1310315C - 纵向静态随机存取存储器单元器件及其形成方法 - Google Patents
纵向静态随机存取存储器单元器件及其形成方法 Download PDFInfo
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Abstract
本发明涉及一种纵向SRAM单元器件的形成方法，包括下列步骤：在形成于平面绝缘体上的构图成平行岛的硅层中，形成通路栅极FET晶体管和形成具有第一共用体和第一共用源极的纵向下拉FET晶体管对；向下蚀刻穿过在交叉耦合反相器FET晶体管之间的上部扩散区，以形成平分纵向下拉FET晶体管对的上拉和下拉漏极区的上层的下拉隔离间隔壁，该隔离间隔壁向下到达共用体层；形成具有第二共用体和第二共用漏极的纵向上拉FET晶体管对。然后，连接FET晶体管以形成SRAM单元。本发明还涉及一种纵向SRAM单元器件。
Description
技术领域
本发明涉及MOSFET SRAM(金属氧化物半导体场效应晶体管静态随机存取存储器)单元，更具体地说，涉及一种制造纵向MOSFET SRAM单元的方法以及因此而提供的结构。
背景技术
对于高性能运用，纵向沟道MOSFETs的使用能精确控制沟道的长度。
Noble的美国专利No.6,477,080关于“Circuits and Methods for a StaticRandom Access Memory Using Vertical Transistors”描述了一种在SRAM电路中具有FET器件的浮置体的纵向SRAM器件。该专利还陈述如下：
“存储单元的n沟道和p沟道晶体管......分别地具有由n+和p+多晶硅形成的栅极。反相器中的多晶硅栅极与由难熔金属形成的栅极接触(gatecontact)耦合在一起，以便提供用于在反相器中的每个晶体管中所希望的表面沟道特性的双工作功能特性。值得注意地是，在存储器单元中晶体管的器件体...是彼此隔离的并与衬底隔离，使得晶体管表现出绝缘体基外延半导体特性(semiconductor-on-insulator characteristics)。从而，可以充分耗尽晶体管，浮置体器件用于隔离而不需要CMOS阱用于隔离。”
“然而，使用美国申请No.08/889,396，的技术能包括体接触(bodycontact)...”，(现在Forbes等人的美国专利No.5,909,618题为“Memory Cellwith Vertical Transistor and Buried Word and Body Lines”)。
我们认为具有独立浮置体器件(即SRAM电路中的交叉耦合反相器的元件)的结构存在问题。这个问题是具有独立的浮置体器件，该器件存在Vt失配，这意味着由于体充电，匹配的上拉晶体管对和匹配的下拉晶体管对的值将浮动到发散的Vt值。除了由高度发散的Vt值引起的错误导致数据可能丢失之外，在Vt失配不太严重的情况中，结果将是损害单元的灵敏度。当匹配的晶体管对的Vt值发散时，有数据丢失的重大危险。从而，外部连接至FET器件体的设想是一种选择方案，将可以克服Vt失配的问题。
提供外部体接触的选择是不合乎要求的，因为将需要SRAM结构的有用表面区域以设置接触(contact)。因此，认为有必要找到由Noble提出建议的任何一个的替代方法。
而Noble的专利认识到FET器件的浮置体是一关注重点。该申请描述了至体的接触使得它们能保持在一定的电势，该申请的引用将不得不付出额外单元面积和工艺复杂性的代价。我们认识到通过把下拉的体缚在一起，以及把上拉的体缚在一起，可获得Vt匹配。
工业的主要方向是积极地标度最小的光刻尺寸F(这是一种用光刻工艺能印刷的)。目前，典型的集成电路(IC)具有0.18μm(1800)的F，而高性能电路具有0.13μm(1300)的切割边缘F，而0.1μm(1000)F技术的工艺和结构正处于发展过程中。半导体工业中的另一个主要趋势是减小各种存储器单元的相关面积，即在0.18μm技术中测量的平面SRAM单元是120-140F2，而在0.13μm技术中测量的平面SRAM单元是较小的100-120F2。非常期望地是，具有能用F＜0.1μm的技术标度的存储器单元而不会实质损失相关面积。
Noble的优选实施例给出F＝0.3μm(5段，15行)。在具有亚光刻尺寸的结构中可存在某些特征。淀积和蚀刻技术使得产生这样的亚光刻特征。例如，在极端的情况中，淀积和蚀刻都能被控制为具有一个原子单层(依靠具体的化学键大约是1-5)的精确度。在实践中，这些特征的控制在目标淀积和/或去除的10％以内。也就是，一种具有能常规地和可靠地产生/除去10-50厚的层的有效淀积和蚀刻技术。这种淀积技术的结合能用于产生更精确的亚光刻结构。例如，通过形成在窄光刻定义的1F宽度沟槽的壁上的两个(或更多)亚光刻间隔壁来定义无边界接触(borderless contact)。间隔壁间的材料被选择性地蚀刻至间隔壁的材料处，从而提供具有1F减去2x间隔壁厚度的宽度的开口。
在Noble的专利中，间隔壁的厚度是1/4F以及开口厚度是1/2F。通常，为了制作例如无边界接触的精细亚光刻结构，不得不使用材料和工艺步骤的非明显组合，将把淀积和蚀刻技术的精确度转化成有用的三维结构。通常，材料和工艺步骤的非明显组合可以导致缺陷和/或与其它结构的不相容。
Noble的专利公开了在导体之间的无边界(亚光刻)结构，该结构利用下列步骤产生用于导体的间隔壁。
(a)形成亚光刻悬垂SiN间隔壁；
(b)借助光刻掩模除去间隔壁之一；
(c)产生一侧亚光刻沟槽；
(d)用本征多晶硅填充沟槽；
(e)选择性蚀刻氧化物帽到本征多晶硅。
值得注意的是用本征多晶硅的亚光刻(～1/4F)层使导体分开。然后部分地除去层中的本征硅并且留下在电路的其它部分如530中的本征硅。本征多晶硅不是好的绝缘体材料。为了有效地隔离导体，它应该是非常厚的。甚至在F＝0.3μm时，由于残余掺杂和从重掺杂源极/漏极向外扩散的掺杂剂，750的多晶硅层几乎不能隔离金属导体。在F＝0.1μm时，多晶硅间隔壁变成仅250并且确实地产生短路的结构。
在我们的例子中，由于向外扩散的掺杂剂和/或剩余掺杂水平，本结构不具有任何局限性。实际上，即使在F＝0.03μm的技术节点处，各种导体层将被隔离。在0.3μm和0.03μm之间是两个(2)数量级。
Forbes等人的美国专利No.5,909,618的题为“Memory Cell with VerticalTransistor and Buried Word and Body Lines”描述和示出(它的附图4)了一种DRAM器件，其具有与一对体区(214)并列排置的体线(208)，形成非常复杂的体接触结构。体线(208)提供至体区(130)的垂直侧壁(223)的机械和电气体接触，体线(208)形成在表现为隐埋绝缘层(400)的顶部上。只是为了制造至两个邻近器件的体区(214)的接触，Forbes形成一沿着绝缘层(400)的凹陷间隔壁(218)，以提供体线(208)与源极区(212)的隔离，以及然后形成体线(208)。Forbes的另一个复杂性是体线(208)是凹陷的以致它不能接触漏极层(216)。
Flaker等人的美国专利No.6,133,608关于“SOI-Body Selective LinkMethod and Apparatus”，没有涉及纵向晶体管，描述了一种平面型FETSRAM绝缘体基外延硅(SOI)结构及其制作方法，该结构包括具有形成在绝缘氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个SOI场效应晶体管(PFETs)的至少两个P型体。在硅层中也形成至少两个SOI场效应晶体管(NFETs)的至少两个n型体。导电体连接被形成在氧化硅绝缘层上方的SOI晶片的硅层中，用于选择性地连接p型SOI FETs或n型SOI FETs的所希望的体以及用于使被连接的体浮置。
Flaker等人的专利陈述如下：“对于SOI器件，由于所有的体是浮置的，最初的体电势可在从接近接地到接近Vdd的范围内变化(当同时考虑NFETs和PFETs时，它们的源极不一定接地或连接至Vdd)。”这里参考上面所述的，这样产生大的Vt失配。这种失配能减慢读出(也就是，需要较慢的设定脉冲)或导致在适当的方向上设定锁存的彻底失败。Flaker等人的专利还陈述如下：“通过连接成对的器件的体，维持了SOI相对于体CMOS的许多性能优点(例如，动态Vt降低)。另一方面，如果所有的体缚在一起，任何一个器件的充电状态将不会严重影响体电势。此外，在如果所有的体缚在一起的情况下，性能将会达到体器件的性能(除了降低的结电容)。”Flaker等人的专利的问题是它涉及平面型SRAM器件，而不是纵向SRAM器件，并且它没有提出用于形成这种器件的工艺。此外，Flaker等人的专利不能提供任何关于在纵向SRAM器件的制造中使用的工艺种类或纵向SRAM器件结构的指导。
存在一种问题，提供纵向SRAM器件而没有在Vt失配中浮置体变化的问题，由于一方面它们能毁坏数据，或者占据器件的表面面积以提供至FET器件的体的接触以便克服Vt失配的问题，该纵向SRAM器件是不可靠的。
对于DRAM的运用，由Forbes等人公开的专利在其12段58-62行描述了必须维持充分高的Vt以便避免亚阈值漏电流。负字线(WL)低不是预期的。在Forbes等人的专利中用于体接触的方案中存在问题。首先，有必要将体接触与沟道精确纵向对准，以避免源极/漏极扩散区和体接触之间的漏电。其次，由于将使晶体管工作负担重要泄露电流的界面缺陷，存在极其接近栅极沟道和扩散区的体接触可以引起极高的载流子复合速度。
发明内容
根据本发明一个优点是与接触的体布图相比没有面积损失。
而且根据成对的纵向MOSFET’S的这种共用体(common body)被连接在一起以取得Vt匹配。
另一目的是使体层互相连接而没有形成体线的复杂化，因为本发明的工艺需要仅仅使漏极区凹陷直到它下降到体层以下。没有Forbes等人的隐埋绝缘层和隐埋凹陷间隔壁，本工艺是简单明了的。
根据本发明的通路栅极(pass gate)或转移器件取代了常规的单个面的栅极，具有提供由于三维(3D)沟道体积耗尽导致的更高的跨导、更好的操作灵活性和效率的围绕的栅极。结果，SRAM单元将经受较少的干扰或更好的单元稳定性。
根据本发明，以纵向MOSFETs形式存在的对向交叉耦合CMOS反相器的体互相连接，而不需要实际形成接触(通过使用单晶硅的邻接区)。目的是获得Vt匹配而不涉及Vt的绝对值。由于被连接晶体管的至少一对将在任何给定时间处于体充电模式的事实，Vt的值总保持相当低。从而，体充电分享给单元中的交叉耦合CMOS反相器。这样，对于根据本发明的SRAM单元的交叉耦合CMOS反相器，低Vt的值不是关键考虑因素。
通过本发明提供的结构彻底避免了任何考虑将体接触与沟道精确地纵向对准以避免存在于Forbes等人的实施例中的源极/漏极扩散区与体接触之间的漏电。通过本发明提供的结构还彻底地避免了任何考虑存在Forbes等人的实施例中的极其接近栅极沟道和扩散区的体接触(由于将使晶体管工作负担重要泄露电流的界面缺陷，其有可能引入极高的载流子复合速度)。上述担忧被克服了，由于通过不受干扰的单晶硅桥形成用于那些MOSFET器件的共用体，从而形成对向纵向MOSFET器件之间的互相连接。
根据本发明，提供一种形成纵向静态随机存取存储器单元器件的方法，包括下列步骤：形成通路栅极FET晶体管；形成具有第一共用体和第一共用源极区的纵向下拉FET晶体管对；形成具有第二共用体和第二共用源极区的纵向上拉FET晶体管对；以及连接在静态随机存取存储器单元器件的静态随机存取存储器单元电路中的所述FET晶体管。
根据本发明，通过下列步骤形成纵向静态随机存取存储器(SRAM)单元器件。在形成于平面型绝缘体上的构图成平行岛的硅层中，形成通路栅极FET晶体管和形成具有第一共用体和第一共用源极的纵向下拉FET晶体管对。
优选地，形成具有第一共用源极、第一共用体和第一共用漏极的上拉FET晶体管，然后用第一介质隔离区平分第一共用漏极。
形成具有第二共用源极、第二共用体和第二共用漏极的下拉FET晶体管，然后用第二介质隔离区平分第二共用漏极。从由平面型和纵向晶体管构成的组中选择通路栅极FET晶体管。
优选地，SRAM器件包括两对通路栅极FET晶体管；FET晶体管形成有在非平面型晶体管的上扩散区和零位(M0)金属化层之间的亚光刻无边界接触(borderless contact)结构；FET晶体管与形成在非平面型晶体管的栅极电极和零位(M0)金属化层之间的亚光刻无边界接触结构连接。
优选地，FET晶体管与形成在非平面型晶体管的栅极电极和第二金属化层之间的亚光刻无边界接触结构连接；共用栅极电极使下拉和上拉纵向FETs互相连接；栅极电极由从Si、SiGe、SiGeC构成的组中选择的重掺杂多晶半导体材料形成。
优选地，器件是通过下列步骤形成的绝缘体基外延硅器件：
在平面型绝缘体上形成硅层；
把硅层构图成平行的岛；
在平行岛的第一部分中形成具有掺杂纵向上拉层的上拉岛，包括上拉上层、上拉体层和上拉下层，上拉上层和上拉下层具有与上拉体层相反类型的掺杂剂；
在平行岛的第二部分中形成具有掺杂纵向下拉层的下拉岛，包括下拉上层、下拉体层和下拉下层，下拉上层和下拉下层具有与下拉体层相反类型的掺杂剂。
优选地，向下蚀刻穿过在交叉耦合反向器FET晶体管之间的上扩散区，以形成平分纵向下拉FET晶体管对的上拉和下拉漏极区的上层的下拉隔离间隔壁，该隔离间隔壁向下到达该共用体层。形成具有第二共用体和第二共用漏极的纵向上拉FET晶体管对。然后，连接FET晶体管以形成SRAM单元。
优选地，向下蚀刻穿过在交叉耦合反向器FET晶体管之间的上扩散区，以形成平分纵向下拉FET晶体管对的上拉和下拉漏极区的上层的下拉隔离间隔壁，该隔离间隔壁向下到达该共用体层。形成具有第二共用体和第二共用漏极的纵向上拉FET晶体管对。蚀刻以形成平分下拉上层的下拉隔离间隔壁，以形成纵向下拉FET晶体管对的下拉漏极区，该下拉隔离间隔壁向下到达下拉体层；蚀刻以形成平分上拉上层的上拉隔离间隔壁，以形成纵向上拉FET晶体管对的上拉漏极区，该上拉隔离间隔壁向下到达上拉体层。用绝缘介质填充下拉隔离间隔壁和上拉隔离间隔壁。
形成用于FET的最上扩散的共用扩散区，然后蚀刻扩散区以形成凹陷，从而在共用体上方形成隔离扩散区。包括下列步骤：形成用于FET的最上扩散的共用扩散区；蚀刻共用扩散区以在第一共用体和第二共用体的每个上方形成凹陷，从而在第一共用体和第二共用体的每个上方形成隔离扩散区；以及用介质材料填充每个凹陷。形成使交叉耦合下拉和上拉纵向FET晶体管互相连接的共用栅极电极。栅极电极由从Si、SiGe、SiGeC构成的组中选择的重掺杂多晶半导体材料形成；栅极电极是全部的或部分的由金属导体形成的；栅极电极形成为完全地或部分地围绕通路栅极晶体管的晶体管体。形成使下拉和上拉纵向FET互相连接的共用栅极电极。
而且根据本发明，提供一种纵向静态随机存取存储器(SRAM)单元器件。SRAM包括：通路栅极纵向FET晶体管对；具有第一共用体和第一共用源极的纵向下拉FET晶体管对；具有第二共用体和第二共用源极的纵向上拉FET晶体管对；以及在SRAM单元电路中所述FET晶体管之间的连接。
附图说明
下面参考附图解释和描述本发明的上述和其它MOSFET SRAM方面和优点，在附图中：
图1A示例了一种依据本发明的方法制作的结构，该结构包括含有交叉耦合锁存器件的SRAM单元，交叉耦合锁存器件独立地包括具有带共用体的上拉反相器和带共用体的下拉反相器的纵向沟道MOSFETs(Metal OxideSemiconductor Field Effect transistors，金属氧化物半导体场效应晶体管)；
图1B示出了图1A的器件的电路图；
图2A-2C至图13A-13C示例了根据本发明的方法用于形成纵向SRAM器件的依据本发明的工艺步骤。
具体实施方式
图1A示例了一种依据本发明的方法制作的结构，该结构包括含有交叉耦合锁存器件的SRAM单元电路10，该交叉耦合锁存器件独立地包括纵向沟道MOSFETs(Metal Oxide Semiconductor Field Effect Transistors，金属氧化物半导体场效应晶体管)。整个单元电路10包括通路栅极晶体管PG1/PG2和由四个MOSFET晶体管PD1、PD2、PU1和PU2形成的交叉耦合反相器，占用112F2的面积(包括绝缘区)。通过对于栅极导体是无边界的下层(lowerlevel)布线M0和柱(stud)，提供SRAM电路中的交叉耦合MOSFET晶体管对PD1、PD2、PU1和PU2的漏极D2/D5和D3/D4的互相连接。对于下层布线M0是无边界的另一层布线M1，用于交叉耦合反相器PD1、PD2、PU1和PU2以及用于使它们的输出连接到SRAM单元电路10的通路栅极MOSFETs PG1和PG2上。
然而，如果使用亚光刻技术制造纵向栅极，例如形成侧壁间隔壁栅极，那么SRAM器件的尺寸能降低到低于100F2。
此外，根据本发明，交叉耦合反相器的纵向MOSFETs是在对向面设立栅极，还产生比单面栅极器件更大的导通电流。
因为通路栅极电极围绕通路栅极MOSFETs的源极、漏极和沟道的栅极电极结构，所以本发明的通路栅极MOSFETs这里指“围绕的栅极器件”。
本发明的SRAM单元的主要优点是，由于纵向器件结构和围绕的栅极结构，本发明的SRAM能比常规的SRAM单元工作在更低的电压，产生低电源。
如图1A所看到地，通过隐埋扩散线形成位线导体BL/BL′，该隐埋扩散线可以周期性地搭接被覆金属层或被覆硅化物层以降低电阻。类似地，Vdd和Vss线包括隐埋扩散线。均能使用无边界接触以取得面积的减少。
图1A是根据本发明的单元排列的示意图，包括独立地由纵向MOSFETs形成的SRAM单元电路10，SOI(Silicon On Insulator，绝缘体基外延硅)SRAM结构10包括形成在背面氧化物层BOX的外表面上的一系列六个纵向沟道FETs，背面氧化物层BOX(Back Oxide layer)可以由氧化硅形成。这里使用术语“BOX”(常常用于指示背面氧化物层，也是公知的隐埋氧化物层)作为方便的参考标记，以识别附图中的背面氧化物层。
形成于背面氧化物层BOX上方的六个FETs包括两个通路栅极晶体管PG1/PG2、两个上拉晶体管PU1/PU2以及两个下拉晶体管PD1/PD2。通过图6A和后续附图所示的共用栅极电极结构G2和G3，如上所述，使上拉晶体管PU1/PU2和下拉晶体管PD1/PD2交叉耦合。
共用栅极结构G2被下拉晶体管PD1和上拉晶体管PU1共享，其分别包括栅极电极G2″和栅极电极G2′。图1A所示的共用栅极电极结构G2的部分作为下拉晶体管PD1的栅极电极G2″和上拉晶体管PU1的栅极电极G2′。
相似的共用栅极结构G3被下拉晶体管PD2和上拉晶体管PU2共享，其分别包括栅极电极G3″和栅极电极G3′。图1A所示的共用栅极电极结构G3的部分作为下拉晶体管PD2的栅极电极G3″和上拉晶体管PU2的栅极电极G3′。
两个通路栅极晶体管PG1/PG2各包括N+/P/N+掺杂区的纵向叠层，纵向叠层包括位于各叠层顶部的N+掺杂漏极区D1/D6和位于各叠层低部的源极区S1/S4以及位于其间的P掺杂沟道区。另外，通路栅极PG1/PG2具有栅极导体G1/G4横向地围绕纵向叠层ST1/ST4的构造(如图8A等所示)，提供与P掺杂沟道和N+掺杂源极和漏极区并置的更多的栅极电极表面积。
通路栅极晶体管PG1包括具有示出在其左侧和右侧上的栅极电极部分G1′和G1″的栅极电极G1，并且具有FET的纵向有源区，P掺杂的中心沟道区夹在其上和其下的N+掺杂漏极/源极区D1/S1之间。实际上如图10A/10C以及相似的平面图中所看到地，栅极G1的栅极电极部分G1′/G1″围绕着通路栅极晶体管PG1的纵向有源区。类似地，如图10A/10C以及相似的平面图中所看到地，栅极电极G4的栅极电极部分G4′和G4″围绕着通路栅极晶体管PG2的纵向有源区。
通路栅极晶体管PG2包括具有示出在其左侧和右侧上的栅极电极部分G4′和G4″的栅极电极G4，并且具有FET的纵向叠层有源区，P掺杂的中心沟道区夹在其上和其下的N+掺杂漏极/源极区D6/S4之间。实际上如图10A/10C以及相似的平面图中所看到地，栅极电极G4′/G4″围绕着通路栅极晶体管PG2的纵向有源区。
根据本发明的两个上拉晶体管PU1/PU2共享共用体区CBP并因此提供相同的Vt值。两个上拉晶体管PU1/PU2形成为具有在共用N+掺杂源极区S3上方的共用P掺杂沟道体区CBP，在两个上拉晶体管PU1/PU2的沟道体区CBP的上方是通过其间的介质区STI分开的分离N+掺杂漏极区D1/D2，介质区STI优选地是浅沟槽隔离区。从而两个上拉晶体管PU1/PU2具有相同Vt值和共用体CBP，并且共用源极S3位于由介质区STI分隔的分离漏极D4/D5的下方。
类似地，根据本发明的两个下拉晶体管PD2/PD1共享共用体区CBN从而具有相同的Vt值。两个下拉晶体管PD1/PD2形成为具有在共用P+掺杂源极区S2上方的共用N掺杂沟道体区CBN。两个下拉晶体管PD1/PD2的P+掺杂漏极区D2/D3由其间的介质区STI分隔，介质区STI优选地包括浅沟槽隔离区。从而两个下拉晶体管PD1/PD2具有相同Vt值和共用体CBN，并且共用源极S2位于由介质区STI分隔的分离漏极D2/D3的下方。
图1B示出了图1A的器件的电路图，通路栅极晶体管PG1的栅极G1通过节点N5连接到字线WL上和通路栅极晶体管PG2的栅极G4通过节点N6连接到字线WL上。
通路栅极晶体管PG1的源极S1通过节点N3连接到位线BL上，以及通路栅极晶体管PG1的漏极D1通过节点N2连接到晶体管PU1和PD1的漏极D2/D5上以及晶体管PU2和PD2的栅极电极。
通路栅极晶体管PG2的源极S4通过节点N4连接到位线BL′上，以及通路栅极晶体管PG2的漏极D6通过节点N1连接到晶体管PU2和PD2的漏极D3/D4上以及晶体管PU1和PD1的栅极电极。
下拉晶体管PD1/PD2具有夹在P+掺杂源极/漏极区之间的N掺杂沟道区并且还分别地具有栅极电极G2″/G3″。位于背面氧化物层BOX的表面上的下拉晶体管PD1/PD2的共用源极S2通过节点N8连接到电压Vss上。如上所述，下拉晶体管PD1的漏极D2连接到节点N2上以及下拉晶体管PD2的漏极D3连接到节点N1上。
上拉晶体管PU1/PU2具有夹在N+掺杂源极/漏极区之间的P掺杂沟道区并且还分别地具有栅极电极G2′/G3′。位于背面氧化物层BOX的表面上的上拉晶体管PU1/PU2的共用源极S3通过节点N7连接到电压源Vdd上。如上所述，上拉晶体管PU1的漏极D5连接到节点N2上以及上拉晶体管PU2的漏极D4连接到节点N1上。
值得注意地是，下点状线CBN指示下拉晶体管PD1/PD2的沟道被包含在共用体CBN内以及另一点状线CBP指示上拉晶体管PU1/PU2的沟道被包含在共用体CBP内。
节点N1通过互连线I1交叉连接至下拉晶体管PD1的栅极电极G2″和至上拉晶体管PU1的栅极电极G2′。
节点N2通过互连线I2交叉连接至下拉晶体管PD2的栅极电极G3″和至上拉晶体管PU2的栅极电极G3′。
实际的物理结构(将通过下面的附图示出)折叠交叉耦合的成对的NFETs PD1/PD2和PFETs PU1/PU2，使得每对共用栅极G2(G2′/G2″)和G3(G3′/G3″)是共面的。
工艺步骤
通过图2A-2C至图13A-13C示例了根据本发明形成图1A和图13A-13C的结构的方法。
SOI器件的硅岛的形成
参考图2A-2C示出了本发明具体实施例的制造中的早期阶段。开始的材料是标准的绝缘体基外延硅(SOI)晶片10，晶片10包括覆盖有已经被覆氮化硅(衬垫层SN)的硅层的背面氧化物层BOX(由氧化硅形成)，衬垫层(pad layer)SN覆盖有用于形成平行的岛L1-L4(也能看作水平的、平行的条)的光刻胶掩模PR，岛L1-L4由硅组成并且由绝缘间隔壁IS(也能看作水平的、平行的沟槽，如图2A和2C所示)分隔。
图2A示出了图1A/1B的SRAM器件10的单个单元的平面图，其中在晶片的表面上形成了由硅组成的平行岛L1-L4的图案。岛L1-L4通过沟槽例如在背面氧化物层BOX上方的其间的绝缘间隔壁IS被分隔。如上所述，绝缘间隔壁IS水平延伸，即在图中从左向右。
图2B是沿截取线Y-Y′截取的图2A的器件10的纵向正面图，线Y-Y′平分岛L2，背面氧化物层BOX(在图的底部)支持硅层SI，在硅层SI上形成有薄氮化硅，即衬垫层SN。衬垫层SN覆盖有光刻胶层，该光刻胶层已经被构图并用于形成光刻胶掩模PR。该掩模已经被用于蚀刻(优选地用RIE(Reactive Ion Etching，反应离子蚀刻)工艺)以除去衬垫层SN和硅层SI的不需要的部分，从而形成岛L1-L4。
图2C是沿图2A的线X-X′截取的左视图，示出通过光刻胶掩模PR、氮化硅即衬垫层SN和硅层Si，岛L1-L4之间的绝缘间隔壁IS已经被蚀刻至背面氧化物层BOX的外表面上。
如上所述，使用蚀刻工艺以蚀刻穿过SOI器件的硅层Si，以在背面氧化物层BOX的表面上形成一系列岛L1-L4。根据常规光刻技术的标准构图技术，例如淀积衬垫层SN、淀积光刻胶层PR以及构图光刻胶层PR，可用于构图岛L1-L4。在使用图案化的光刻胶PR作为掩模来构图衬垫层SN以把衬垫层SN转变成中间掩模层之后，通过RIE反应类方法蚀刻硅，该RIE反应类方法是选择性的以保护掩模材料，和选择背面氧化物BOX的氧化硅而去除通过光刻胶掩模PR暴露的氮化硅SN和硅。RIE蚀刻工艺继续穿过硅层Si，直到到达背面氧化物BOX的外(顶)表面，此时蚀刻工艺停止，这是本领域技术人员所能理解的。
离子注入具有纵向源极/漏极和沟道区的岛
图3A-3C示出了在使用阻挡掩模(未示出)进行掩蔽离子注入之后的图2A-2C的结构。岛L1-L4的侧壁临时地涂敷有牺牲氧化硅层SO的薄层。在用N和P型掺杂剂的离子注入步骤中，示出选择性地垂直注入平行的硅岛L1-L4。
在岛L3的情况下，如本领域技术人员所公知的，一系列的离子注入步骤产生P+/N/P+掺杂硅区的纵向叠层，其将被用在图4A-4C至图13A-13C显示的后续工艺步骤中以形成下拉晶体管PD1/PD2的源极、沟道和漏极区。
在岛L1、L2和L4的情况下，如本领域技术人员所公知的，一系列的离子注入步骤产生N+/P/N+掺杂硅区的纵向叠层，其将被用在图4A-4C至图13A-13C显示的后续工艺步骤中以形成上拉晶体管PU1/PU2和通路栅极晶体管PG1/PG2的源极、沟道和漏极区。
具体地，进行掺杂工艺以形成源极/漏极和沟道区，其最终分别地形成保留晶体管PG1、PU2/PU1和PG2(参看图1A)，如下面参考图9A-9C、图10A-10C和图11A-11C的详细描述。制备两个外岛LI/L4，用于形成包括用于通路栅极晶体管PG1/PG2的纵向NMOS FETs、图1A的隐埋位线扩散区和完成结构。制备两个内岛L2/L3，用于制造包括具有如图1A所示的四个纵向MOSFETs PU1/PU2/PD1/PD2的交叉耦合反相器，以及隐埋Vdd和Vss线。在离子注入步骤完成后，然后除去牺牲氧化硅层SO。
用于构图器件叠层的硬掩模的形成
图4A-4C示出了在薄氮化硅衬里SL被保形地淀积覆盖包括衬垫层SN、岛L1-L4的侧壁以及背面氧化层BOX的器件的表面之后的图3A-3C的结构。薄氮化硅衬里SL被提供以构图成用于后续RIE蚀刻步骤的蚀刻停止层。下一个步骤是形成硬掩模OX1。首先，氧化硅的毯覆层被淀积、平面化和构图成硬掩模OX1。通过例如CVD氧化物淀积的工艺形成硬掩模OX1。然后，平面化硬掩模层，当其厚度足够覆盖衬垫层SN的顶表面时停止平面化，在包括四个岛L1-L4之间和之外的空间的器件上方提供平坦的表面。从而用硬掩模OX1填充绝缘间隔壁IS。然后，在硬掩模层OX1的上方，如本领域技术人员所公知的，形成由矩形带(从接近图4A的顶部延伸到接近底部)组成的构图掩模(未示出)。硬掩模OX1覆盖沿图中垂直方向上在硅层中的原始岛L1-L4的中心部分，使用RIE蚀刻工艺将该氧化物构图，该RIE蚀刻工艺对包括衬垫层SN和氮化硅衬里SL的氮化硅是选择性的。硬掩模OX1的氧化硅的构图停止在作为蚀刻终止层的氮化硅衬里SL上，从而避免蚀刻到背面氧化物BOX中。
来自岛的纵向器件叠层的形成
图5A-5C示出了在硬掩模OX1(已除去了)的构图中蚀刻岛L1-L4以形成包括四个纵向叠层ST1-ST4的有源区之后的图4A-4C的结构。优选的方法是通过RIE对图4A-4C中显示的没有被硬掩模OX1保护的岛L1-L4的部分进行各向同性的纵向蚀刻，以形成四个纵向叠层ST1-ST4。除了纵向叠层ST1-ST4之外，RIE蚀刻工艺不会进行至完成而是持续下去，直到它部分地降低岛L1-L4的水平。RIE蚀刻工艺向下穿过氮化硅衬垫SN的暴露部分(不被硬掩模层OX1保护的)和四个硅岛L1-L4的下层部分，到达高于背面氧化物层BOX的表面的水平，保留仅仅如图5B所示的N+/P/N+层的最低的N+层的部分，和仅仅P+/N/P+层的最低P+层的部分，以提供除叠层ST1-ST4之外由岛L1-L4形成的一系列隐埋导体BC1、BC2、BC3和BC4。
隐埋导体/位线的形成
如图5B所示例地，示出叠层ST2的截面图。在图5B中除纵向叠层ST2之外，在原始的Si岛L2的底部的暴露部分的位置处，氮化硅衬垫层SN和上部两个N+掺杂和P掺杂区已被彻底蚀刻掉并且下部N+掺杂区的一部分也被去除，仅仅留下在薄高密度等离子(HDP)氧化物层HD下面的以隐埋导体BC2形式存在的薄层。
参考在图5A中示出的其它三个叠层ST1、ST3和ST4，与纵向叠层ST2的情况类似，当用RIE将图案化岛L1、L3和L4蚀刻一定深度时RIE工艺结束，在该深度下留下叠层ST1的底部N+掺杂层、留下叠层ST3的底部P+掺杂层以及留下叠层ST4的底部N+掺杂层。
四个叠层ST1-ST4的四个底层的剩余厚度对于它们作为隐埋导体BC1、BC2、BC3和BC4是足够的，在每个岛L1-L4中的最底部扩散区处，形成隐埋位线BL，隐埋位线BL′、隐埋连接线Vdd以及隐埋连接线Vss，如图13A所示。概括地说，图案化岛L1/L4的最底部扩散区用于分别地形成位线BL/BL′以及图案化岛L2/L3的最底部扩散区用于提供Vss和Vdd线，如图13A所示，下面更详细地解释。
第二牺牲氧化物的形成和去除
通过氧化暴露的表面形成牺牲层并且然后除去牺牲层以除去表面杂质，优选地，留下暴露的底部结的边缘。
位线上方的高密度等离子氧化物层的形成
图5B和5C示出了在除去任何剩余侧壁氧化物之后形成的高密度等离子(HDP)氧化物层HD，所述剩余侧壁氧化物包括图5B中在隐埋导体BC2的表面上和叠层ST2的顶表面上的牺牲氧化物。在图5C中，HDP氧化硅层HD覆盖叠层ST1-ST4的顶表面和背面氧化物BOX的暴露表面。然后形成HDP氧化硅层HD的工艺淀积到足够的厚度以提供后续工艺中的蚀刻终止层。这样确保获得在后续步骤中形成的在纵向MOSFET器件的边缘上的栅极至底部源极/漏极(S/D)重叠。
栅极介质的形成
然后，如图5B和5C所看到的，在叠层ST1-ST4的暴露的硅侧壁表面上形成用于纵向FET器件的纵向栅极介质GD层。例如，栅极介质GD可以由例如热SiO2和/或氮化的SiO2的介质材料组成。
值得注意地是，如图5B所看到的，叠层ST2包括P掺杂区CBP，其是将形成在如图10A/10B所示的上拉晶体管PU1/PU2中的共享P掺杂共用体CBP。类似地，叠层ST3包括将被下拉晶体管PD1/PD2共享的共用体CBN。
掺杂的或未掺杂的栅极多晶硅的淀积
图6A-6C示出了在栅极多晶硅层GP(将被构图成栅极导体)的毯覆式淀积的淀积和平面化之后的图5A-5C的结构。如图6A-6C所示，栅极多晶硅层GP平面化到如图6B和6C所看到的向下至四个叠层ST1-ST4的顶部的衬垫层SN的顶表面。如图6A中所示，用平面化工艺除去留在衬垫层SN的顶表面上方的任何HDP氧化物HD，使在叠层ST1-ST4上方的氮化硅衬垫SN暴露出来。
栅极多晶硅层GP可以是掺杂的或未掺杂的。如果层GP是掺杂的，然后可以使用N+掺杂以形成N+栅极NFETs和N+栅极PFETs。如果希望在后面的工序中掺杂栅极导体，那么在图7A-7C所示的后续栅极多晶硅蚀刻工艺之后，且大概在图8A-8C和9A-9C所示的去除硬掩模HM之后，可以注入栅极多晶硅层GP。
用于反相器的栅极导体和绝缘区的初步定义
图7A-7C示出了在构图之后的图6A-6C的结构，其中硬掩模材料HM(即PR、氧化硅、Al2O3)被淀积和构图成图7A所示的四个图案，其是沿着图7B中的截取线7A-7A′截取的截面图，示出在硬掩模材料HM层下面的结构。值得注意地是，存在掩模HM的两个部分，其通过贯穿其中的窄槽NS使纵向叠层ST2和ST3的中心部分上方的氮化硅SN暴露。暴露的栅极多晶硅GP的横向部分，除硬掩模HM之外，然后通过选择硬掩模HM的材料、氮化硅衬垫层SN和氧化硅的RIE蚀刻工艺，将其蚀刻掉至大约底部结的深度，使得除了叠层之外的栅极多晶硅GP′的厚度保留如图7C示出的大致厚度以及如图7B中所看到的在HDP氧化物HD和隐埋导体BC2的额外厚度上方的非常薄的层GP′。这是在定义四个栅极导体G1-G4和绝缘区的工艺中的预备步骤，其将交叉耦合反相器的邻近输出节点扩散区分开。
此外，栅极多晶硅GP的蚀刻开始分离交叉耦合反相器的栅极导体的工序，此时栅极导体通过薄、保留的栅极多晶硅层GP′保持连接。从而栅极多晶硅GP的蚀刻开始将上拉反相器PU1的栅极G2′与上拉反相器PU2的栅极G3′分离的步骤。类似地，栅极多晶硅GP的蚀刻开始将下拉反相器PD1的栅极导体G2″与下拉反相器PD2的栅极导体G3″分开的步骤。
蚀刻穿过衬垫氮化物至HDP氧化物HD
图8A-8C示出了在用RIE蚀刻工艺除去衬垫层SN的暴露部分之后的图7A-7C的结构，该RIE蚀刻工艺选择掩模材料以及优选地还选择氧化硅和硅。图8A示出了沿图8B中线8A-8A′截取的截面图，在掩模HM层的下方。图8C示出了覆盖有硬掩模HM的叠层ST1和ST4。参考图8B，通过选择掩模材料和氧化硅的RIE蚀刻暴露的Si和栅极多晶硅GP′的剩余部分。该最终RIE除去在RIE的第一部分(图7A-7C)之后还保留的剩余栅极多晶硅层GP′并向下到达作为蚀刻停止层的HDP氧化物HD的表面。这将完成下述工序，即将上拉反相器PU1的栅极G2′从上拉反相器PU2的栅极G3′分离的工序，以及将下拉反相器PD1的栅极导体G2″从下拉反相器PD2的栅极导体G3″分离的同步工序。
交叉耦合反相器叠层的分离
RIE蚀刻继续穿过窄槽NS，彻底地穿过由去除氮化硅衬垫SN的暴露部分而留下的窄槽开口NS′，以蚀刻穿过在叠层ST2和ST3中的顶部源极扩散区，进入反相器MOSFET器件的沟道区CBP(图1A和8B中所示的)和CBN(图1A中所示的)的顶部部分中，达到确保顶部源极扩散区被平分的深度。图8B示出了作为RIE蚀刻穿过窄槽开口NS′的结果，上拉晶体管PU1的源极区从上拉晶体管PU2的源极区分开。类似地，通过RIE蚀刻穿过窄槽开口NS′，下拉晶体管PD1的源极区从下拉晶体管PD2的源极区分开。换句话说，通过蚀刻穿过叠层ST2和ST3的顶部源极扩散区，交叉耦合反相器的对向输出节点N1/N2在窄槽开口NS′的底部处彼此隔离。
形成反相器的STI绝缘的平面化氧化硅的淀积
图9A-9C示出了在除去硬掩模HM并且毯覆氧化硅平面化层OX2通过CVD TEOS或HDP被淀积以及被平面化以暴露剩余衬垫层SN的顶表面之后的图8A-8C的结构，使用本领域技术人员所公知的浅沟槽隔离(STI)形成方法。淀积到窄槽NS的窄槽开口NS′中的氧化硅平面化层OX2的部分形成介质STI绝缘结构STI，分别使相邻FET器件PD1/PD2和PU1/PU2之间的晶体管的源极区分开，而保留如图1A所示的共用体结构。
使栅极导体凹陷以准备形成接触
图10A-10C示出了使用公知的方法使图10B中的多晶硅栅极导体G2′/G3′和图10A中栅极导体G1(G1′/G1″)、G2(G2′/G2″)、G3(G3′/G3″)和G4(G4′/G4″)的暴露表面凹陷到氧化硅层OX2的平面化表面中后的图9A-9C的结构。如下面所解释地，用牺牲氧化物帽CO填充凹陷。在工艺中的此时，氮化硅衬垫层SN的剩余部分覆盖叠层ST1-ST4中的六个纵向FET器件PG1、PG2、PU1、PU2、PD1和PD2的漏极的位置。在准备用于形成除剩余氮化硅衬垫层SN的漏极接触的最初步骤中(图12A-12C所示例的步骤中)形成凹陷。凹陷向下到达在形成的叠层ST1-ST4中的纵向FET器件PG1、PG2、PU1、PU2、PD1和PD2的漏极位置的顶层。
用氧化硅帽填充凹陷
通过淀积毯覆CVD氧化物层正好在凹陷中形成牺牲氧化物帽CO，该CVD氧化物层被平面化到剩余氮化硅衬垫层SN的顶表面。在栅极导体上方形成氧化物帽CO，以促进后续形成至纵向MOSFETs的顶部S/D扩散区的无边界接触。无边界接触的提供(即，图12A所示的接触BS1-BS4和图12B的剖面所示的无边界接触BS2)使得可以实现重要的密度优点。
形成零位布线金属化
图11A-11C示出了在对于其它材料(即，平面化氧化硅层OX2，硅)选择性地蚀刻掉剩余的衬垫层SN以暴露下面的FET器件PG1、PG2、PU1、PU2、PD1和PD2的有源区的掺杂漏极区之后的图10A-10C的结构。可以使用各种蚀刻的任何一种用于去除衬垫层SN的剩余氮化硅。可以通过使用氢氟酸乙烯乙二醇(HFEG)来进行从结构中去除衬垫层SN。一种去除衬垫层SN的可选择的方法是用RIE蚀刻。
然后，包括下层导电金属化层M0(工业中所公知的作为零位层，由例如钨(W)的金属构成)和覆盖如上所示的下层(零位)导电层M0的氮化硅帽CN的淀积物被形成和构图。零位金属化层M0形成至FET器件PG1、PG2、PU1、PU2、PD1和PD2的有源区的掺杂漏极区的接触。如常用技术，在淀积零位金属化层M0之前可以使用衬里。该零位金属化层M0形成每个反相器中的NFET/PFET器件PU1、PU2、PD1和PD2的漏极之间的互相连接，并且还形成用于后续接触到通路栅极晶体管PG1/PG2的上部(漏极)区的导电通路。
形成依靠M0金属化层的间隔壁
然后，氮化硅层被淀积并且通过RIE被蚀刻，以形成所示的氮化硅侧壁间隔壁SP和氮化硅帽CN，作为提供零位金属化层M0和图12A和12B所示的金属接触柱BS1-BS2之间的电隔离的介质。
形成作为至栅极电极的接触的无边界柱
图12A-12C示出了第三氧化硅层OX3被淀积和平面化至形成在零位金属化层M0上方形成的氮化硅帽CN的顶表面之后的图11A-11C的结构。在第三氧化硅层OX3中形成通孔，在暴露四个栅极电极G1、G2、G3和G4的栅极多晶硅的顶表面的同时，选择性地使氮化硅侧壁间隔壁SP和氮化硅帽CN保留在原位。被覆金属化层M1被淀积和平面化至氮化硅帽CN的顶表面，以形成向下到达四个栅极电极G1、G2、G3和G4的金属接触柱BS1-BS4。柱BS1-BS4至零位布线金属化层M0是无边界的并且将后续用于接触这里称作被覆金属化层M1的“第一”位布线层。
形成第一位布线金属化层
图13A-13C示出了在淀积和定义第一位布线被覆金属化层M1以形成“第一”位布线之后的图12A-12C的结构。被覆金属化层M1形成成对的交叉耦合反相器PU1/PD1和PU2/PD2之间的互连线I1/I2、交叉耦合输出节点N1到通路栅极器件PG2的漏极之间的连接、节点N2到通路栅极器件PG1的漏极之间的连接以及通路栅极G1和G2的栅极到字线WL之间的连接。
为了降低总线电阻，可以通过中断阵列用较高的布线层周期地搭接隐埋扩散线(位线、位线条、Vdd、Vss)。完成芯片的标准工艺的后续工序是形成上部层间介质、通孔和布线层。
选择特征
在上述描述的实施例中通路栅极晶体管示出是纵向晶体管，而通路晶体管可以是平面型的或纵向的，本领域的技术人员可以充分地理解。另外，可能存在形成公知的双端SRAM器件的两对通路栅极晶体管。
栅极电极可以由重掺杂多晶半导体形成，或者可选择地栅极电极全部的或部分的由金属导体形成。
半导体可以从由硅(Si)、锗化硅(SiGe)、或碳化硅锗(SiGeC)构成的组中选择。
总结
描述了一种SRAM单元设计，使用所有具有围绕(转移)栅极的纵向MOSFET器件以同时实现高性能、低电源和小芯片尺寸。把无边界接触应用到电源线、字线和位线上。而且通过使用亚光刻侧壁间隔壁栅极，能取得尺寸的减少。紧密的纵向交叉耦合布图还能运用到通常使用常规交叉耦合器件的电路中，例如读出放大器、差分放大器，等等。在反相器中成对的上拉晶体管和成对的下拉晶体管分享提供相同Vt值的共用体区，从而克服Vt失配问题。
当根据上述具体的实施例描述本发明时，本领域的技术人员将认识到本发明在附加的权利要求的精神实质和范围内能进行修改，也就是，在不脱离本发明的精神实质和范围的情况下，在形式上和细节上做出改变。因此，所有这些改变在本发明的观点内并且本发明包含所附权利要求的主题。
Claims (18)
1、一种形成纵向静态随机存取存储器单元器件的方法，包括下列步骤：
形成通路栅极FET晶体管；
形成具有第一共用体和第一共用源极区的纵向下拉FET晶体管对；
形成具有第二共用体和第二共用源极区的纵向上拉FET晶体管对；以及
连接在静态随机存取存储器单元器件的静态随机存取存储器单元电路中的所述FET晶体管。
2、根据权利要求1的方法，包括下列步骤：
形成用于FET的最上部扩散的共用扩散区，以及然后蚀刻该扩散区以形成凹陷，从而在共用体上方形成隔离扩散区。
3、根据权利要求1的方法，包括下列步骤：
形成用于FET的最上部扩散的共用扩散区；
蚀刻该共用扩散区以在该第一共用体和该第二共用体的每个上方形成凹陷，从而在该第一共用体和该第二共用体的每个上方形成隔离扩散区；以及
用介质材料填充每个凹陷。
4、根据权利要求1的方法，包括下列步骤：
形成具有第一共用源极、第一共用体和第一共用漏极的下拉FET晶体管，然后用第一介质绝缘区平分该第一共用漏极；
形成具有第二共用源极、第二共用体和第二共用漏极的上拉FET晶体管，然后用第二介质绝缘区平分该第二共用漏极。
5、根据权利要求1的方法，其中从由平面型和纵向晶体管构成的组中选择该通路栅极FET晶体管。
6、根据权利要求1的方法，其中形成该静态随机存取存储器单元器件包括形成双端口静态随机存取存储器单元的两对通路栅极FET晶体管。
7、根据权利要求1的方法，包括用在非平面型晶体管的上部扩散区和零位金属化层之间形成的亚光刻无边界接触结构连接FET晶体管的步骤。
8、根据权利要求1的方法，包括用在非平面型晶体管的栅极电极和零位金属化层之间形成的亚光刻无边界接触结构连接FET晶体管的步骤。
9、根据权利要求1的方法，包括用在非平面型晶体管的栅极电极和第二金属化层之间形成的亚光刻无边界接触结构连接FET晶体管的步骤。
10、根据权利要求1的方法，其中共用栅极电极使下拉和上拉纵向FET互相连接。
11、根据权利要求1的方法，其中栅极电极由从Si、SiGe、SiGeC构成的组中选择的重掺杂多晶半导体材料形成。
12、根据权利要求1的方法，其中该器件是绝缘体基外延硅器件，由下列步骤形成：
在平面绝缘体上形成硅层；
把该硅层构图成平行岛；
在该平行岛的第一部分中形成具有掺杂纵向上拉层的上拉岛，其包括上拉FET晶体管对的上拉上层、上拉体层和上拉下层，该上拉上层和该上拉下层具有与该上拉体层相反类型的掺杂剂；
在该平行岛的第二部分中形成具有掺杂纵向下拉层的下拉岛，其包括下拉FET晶体管对的下拉上层、下拉体层和下拉下层，该下拉上层和该下拉下层具有与该下拉体层相反类型的掺杂剂；
蚀刻以形成平分该下拉上层的下拉隔离间隔壁，以形成该纵向下拉FET晶体管对的下拉漏极区，该下拉隔离间隔壁向下到达该下拉体层；
蚀刻以形成平分该上拉上层的上拉隔离间隔壁，以形成该纵向上拉FET晶体管对的上拉漏极区，该上拉隔离间隔壁向下到达该上拉体层；
用绝缘介质填充该下拉隔离间隔壁和该上拉隔离间隔壁。
13、根据权利要求12的方法，包括下列步骤：
形成用于FET的最上部扩散的上拉上层和下拉上层中的共用扩散区；
蚀刻该共用扩散区以在该第一共用体和该第二共用体的每个上方形成凹陷，从而在该第一共用体和该第二共用体的每个上方形成隔离扩散区；以及
用介质材料填充每个凹陷。
14、根据权利要求12的方法，其中共用栅极电极使下拉和上拉纵向FET互相连接。
15、根据权利要求12的方法，其中栅极电极由从Si、SiGe、SiGeC构成的组中选择的重掺杂多晶半导体材料形成。
16、根据权利要求12的方法，其中栅极电极全部地或部分地由金属导体形成。
17、根据权利要求12的方法，其中栅极电极完全地或部分地围绕所述FET晶体管体。
18、一种纵向静态随机存取存储器单元器件，包括：
通路栅极纵向FET晶体管对；
具有第一共用体和第一共用源极的纵向下拉FET晶体管对；
具有第二共用体和第二共用源极的纵向上拉FET晶体管对；
在静态随机存取存储器单元器件的静态随机存取存储器单元电路中的所述FET晶体管之间的连接。
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Also Published As
| Publication number | Publication date |
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| KR100530305B1 (ko) | 2005-11-22 |
| CN1507035A (zh) | 2004-06-23 |
| US20040113207A1 (en) | 2004-06-17 |
| KR20040051506A (ko) | 2004-06-18 |
| JP2004193588A (ja) | 2004-07-08 |
| JP3989888B2 (ja) | 2007-10-10 |
| US20070007601A1 (en) | 2007-01-11 |
| US7138685B2 (en) | 2006-11-21 |
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