JP2022159383A - 3次元メモリデバイス及び方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 135
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 239000003989 dielectric material Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims description 127
- 230000008569 process Effects 0.000 claims description 90
- 208000004605 Persistent Truncus Arteriosus Diseases 0.000 claims description 85
- 208000037258 Truncus arteriosus Diseases 0.000 claims description 85
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 42
- 230000015572 biosynthetic process Effects 0.000 description 30
- 238000004519 manufacturing process Methods 0.000 description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229920005591 polysilicon Polymers 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 229910052681 coesite Inorganic materials 0.000 description 15
- 229910052906 cristobalite Inorganic materials 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 229910052682 stishovite Inorganic materials 0.000 description 15
- 229910052905 tridymite Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 229910052721 tungsten Inorganic materials 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910021332 silicide Inorganic materials 0.000 description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 12
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 238000003860 storage Methods 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 238000000427 thin-film deposition Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- -1 doped Si Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 235000011007 phosphoric acid Nutrition 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
Description
特定の構成および配置について説明しているが、これは例示の目的でのみ行われていることを理解されたい。当業者は、本開示の精神および範囲から逸脱することなく、他の構成および配置を使用できることを認識するであろう。当業者には、本開示が様々な他の用途にも用いることができることが明らかであろう。
Claims (31)
- 半導体層と、
前記半導体層上に配置された交互層スタックと、
前記半導体層の分離構造上にあり、前記交互層スタックを通って垂直に延在する、誘電体構造であって、前記誘電体構造は前記交互層スタックによって取り囲まれ、前記交互層スタックは前記誘電体構造の側壁表面に接し、前記誘電体構造は単一の誘電体材料で形成される、誘電体構造と、
前記誘電体構造および前記分離構造を通って垂直に延在する1つまたは複数のスルーアレイコンタクト(TAC)と、
前記交互層スタックを通って垂直に延在する1つまたは複数のチャネル構造と、を備える、
3次元(3D)メモリデバイス。 - 前記1つまたは複数のTACのうち、少なくとも1つのTACは、少なくとも一つの周辺回路と電気的に接続されている
請求項1に記載の3Dメモリデバイス。 - 前記1つまたは複数のチャネル構造のそれぞれの上に配置されたプラグと、
前記交互層スタック内に配置された階段構造と、
前記1つまたは複数のTAC、チャネル構造、およびスリット構造上に配置された1つまたは複数のコンタクト層と、を更に含む、
請求項1に記載の3Dメモリデバイス。 - 前記誘電体構造が前記TACの側壁表面に接する、
請求項1に記載の3Dメモリデバイス。 - 前記3DメモリデバイスがNAND3Dメモリデバイスである、
請求項1または2に記載の3Dメモリデバイス。 - 前記交互層スタックが誘電体層と導体層との交互ペアを含む、
請求項1に記載の3Dメモリデバイス。 - 前記誘電体層が酸化シリコンを含み、前記導体層が金属を含む、
請求項6に記載の3Dメモリデバイス。 - 前記導体層がワードラインを含む、
請求項6に記載の3Dメモリデバイス。 - 前記誘電体材料が酸化シリコンである、
請求項1または4に記載の3Dメモリデバイス。 - 前記誘電体構造が酸化物を含む、
請求項1または4に記載の3Dメモリデバイス。 - 前記誘電体構造が前記3Dメモリデバイス内のスルーアレイコンタクト領域を画定する、
請求項1に記載の3Dメモリデバイス。 - 前記誘電体構造が前記分離構造と等しいかまたはそれよりも小さいフットプリントを有する、
請求項1に記載の3Dメモリデバイス。 - 前記分離構造は、前記半導体層内に位置する底部を有する、
請求項1に記載の3Dメモリデバイス。 - 前記分離構造は、前記半導体層の上面から下面に到達しない浅さに位置する底部を有する、
請求項1に記載の3Dメモリデバイス。 - 前記3Dメモリデバイスは、前記誘電体構造および前記分離構造を通って垂直に延在する1つのTACを備える、
請求項1に記載の3Dメモリデバイス。 - 前記交互層スタック内に配置された階段構造を更に含み、
前記誘電体構造は、前記階段構造によって取り囲まれている、
請求項1に記載の3Dメモリデバイス。 - 前記交互層スタック内に配置された階段構造を更に含み、
前記階段構造は、複数のレベルを有する、
請求項1に記載の3Dメモリデバイス。 - 前記階段構造の前記複数のレベルのそれぞれには、ワードラインコンタクトが配置されている、
請求項17に記載の3Dメモリデバイス。 - 3Dメモリデバイスを形成する方法であって、
基材層上に、第1の誘電体層と、前記第1の誘電体層とは異なる第2の誘電体層とのペアを含む交互誘電体層スタックを配置することと、
前記交互誘電体層スタックを通って垂直に延在するチャネル構造を形成することと、
前記交互誘電体層スタックをエッチングして前記基材層内の分離構造を露出させる開口部を形成することであって、前記開口は前記交互誘電体層スタックによって取り囲まれている、開口部を形成することと、
前記開口部を単一の誘電体材料からなる誘電体層で充填して、前記分離構造と等しいかまたはそれよりも小さいスルーアレイコンタクト(TAC)領域として誘電体構造を形成することと、
前記誘電体構造および前記分離構造を通ってエッチングして、前記基材層を露出するTAC開口部を形成することと、
前記TAC開口部を導体で充填して、前記TAC領域内にTAC構造を形成することと、を含む、
方法。 - 前記TAC構造のうち、少なくとも1つのTAC構造は、少なくとも一つの周辺回路と電気的に接続されている
請求項19に記載の方法。 - 前記交互誘電体層スタックを通って垂直に延在し、前記基材層のドープされた領域を露出させるスリット開口部を形成することと、
前記スリット開口部を通る前記第2の誘電体層を導体層で置き換えて、前記交互誘電体層スタックを交互誘電体/導体層スタックに変換することと、
前記スリット開口部を導体で充填して、スリット構造を形成することと、
前記交互誘電体層スタック内に、複数のレベルを含む階段構造を形成することと、
前記階段構造の前記レベルのそれぞれにワードラインコンタクトを形成することと、
前記チャネル構造およびスリット構造の上にローカルコンタクトを形成することと、
前記ローカルコンタクト、各ワードライン、および各TAC構造上に1つまたは複数のコンタクト層を形成することと、を更に含む、
請求項19に記載の方法。 - 前記第1の誘電体層が酸化シリコンを含み、前記第2の誘電体層が窒化シリコンを含む、
請求項19に記載の方法。 - 前記交互誘電体層スタック内に前記開口部を形成することが、ドライエッチングプロセスを実行することを含む、
請求項19に記載の方法。 - 前記誘電体構造が酸化シリコンを含む、
請求項19に記載の方法。 - 前記交互誘電体/導体層スタックが前記誘電体構造の側壁に接する、
請求項21に記載の方法。 - 前記誘電体構造が各TAC構造の側壁表面に接する、
請求項19に記載の方法。 - 前記分離構造は、前記基材層の上面から下面に到達しない浅さに位置する底部を有する、
請求項19に記載の方法。 - 前記方法では、前記TAC開口部を導体で充填して、前記TAC領域内に1つのTAC構造を形成する、
請求項19に記載の方法。 - 前記交互誘電体層スタック内に、階段構造を形成することを更に含み、
前記誘電体構造は、前記階段構造によって取り囲まれている、
請求項19に記載の方法。 - 前記交互誘電体層スタック内に、複数のレベルを含む階段構造を形成することを更に含む、
請求項19に記載の方法。 - 前記階段構造の前記複数のレベルのそれぞれには、ワードラインコンタクトが配置されている、
請求項30に記載の方法。
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