JP7328334B2 - 階段貫通コンタクトを有する三次元メモリデバイスおよびその形成方法 - Google Patents
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
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- 239000010941 cobalt Substances 0.000 description 1
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Description
Claims (14)
- 三次元(3D)メモリデバイスを形成するための方法であって、
半導体材料で構成された基板であって、前記基板自身に回路構造を含まない基板上に誘電体スタックを形成することであって、前記誘電体スタックは、複数のインターリーブされた誘電体層および犠牲層を含む、誘電体スタックを形成することと、
前記誘電体スタックの少なくとも一方の側に階段構造を形成することと、
前記階段構造を貫通して垂直に延在して前記基板に達するダミーホールを形成することと、
前記ダミーホールの形成と同時に、前記誘電体スタックの外側に第2のダミーホールを形成することと、
前記ダミーホールおよび前記第2のダミーホール内にスペーサを形成することであり、前記スペーサは中空コアを有する、スペーサを形成することと、
前記ダミーホール内のスペーサの前記中空コア内に第1の導体層を堆積し、同時に前記第2のダミーホール内のスペーサの前記中空コア内に第2の導体層を堆積することによって、前記基板と接触する階段貫通コンタクト(TSC)および周辺コンタクトを形成することであって、前記TSCは、前記階段構造を貫通して垂直に延在し、前記周辺コンタクトは前記基板と接触している、TSCおよび周辺コンタクトを形成することとを含む、
方法。 - 前記TSCを形成する前に、前記誘電体スタック内の前記犠牲層を導体層に置き換えることによって複数のワード線を形成することをさらに含む、
請求項1に記載の方法。 - 各々が、前記ワード線のそれぞれ1つと接触する複数のワード線コンタクトを、前記TSCの形成と同時に形成することをさらに含む、
請求項2に記載の方法。 - 前記TSCを形成した後に、前記誘電体スタック内の前記犠牲層を導体層に置き換えることによって複数のワード線を形成することをさらに含む、
請求項1に記載の方法。 - 前記スペーサを形成することは、前記ダミーホール内に誘電体層を堆積させることを含む、
請求項1に記載の方法。 - 前記第1の導体層および前記第2の導体層は同じ材料を含む、
請求項1に記載の方法。 - 三次元(3D)メモリデバイスを形成するための方法であって、
複数のインターリーブされた誘電体層および犠牲層を含む誘電体スタックを、半導体材料で構成された基板であって、前記基板自身に回路構造を含まない基板上に形成することと、
前記誘電体スタックの少なくとも一方の側に階段構造を形成するステップと、
前記基板に達するダミーチャネル構造を形成することであって、前記ダミーチャネル構造は、前記階段構造を貫通して垂直に延在する、ダミーチャネル構造を形成することと、
前記ダミーチャネル構造の一部を除去することによってスペーサを形成することであって、前記スペーサは中空コアを有する、スペーサを形成することと、
前記スペーサの形成と同時に、前記誘電体スタックの外側に第2のスペーサを形成することであって、前記第2のスペーサは中空コアを有する、第2のスペーサを形成することと、
前記スペーサの前記中空コア内に第1の導体層を堆積することによって、前記基板と接触する階段貫通コンタクト(TSC)を形成することであって、前記TSCは、前記階段構造を貫通して垂直に延在する、TSCを形成することと、
前記TSCの形成と同時に、前記第2のスペーサの前記中空コア内に第2の導体層を堆積することによって周辺コンタクトであって、前記周辺コンタクトは前記基板と接触している、周辺コンタクトを形成することとを含む、
方法。 - 前記スペーサを形成する前に、前記誘電体スタック内の前記犠牲層を導体層に置き換えることによって複数のワード線を形成することをさらに含む、
請求項7に記載の方法。 - 各々が前記ワード線のそれぞれ1つと接触する複数のワード線コンタクトを、前記TSCの形成と同時に形成することをさらに含む、
請求項8に記載の方法。 - 前記TSCを形成した後に、前記誘電体スタック内の前記犠牲層を導体層に置き換えることによって複数のワード線を形成することをさらに含む、
請求項7に記載の方法。 - 前記スペーサを形成することは、前記基板に達するように前記ダミーチャネル構造を介して開口部をエッチングすることを含む、
請求項7に記載の方法。 - 前記第1の導体層および前記第2の導体層は同じ材料を含む、
請求項7に記載の方法。 - 三次元(3D)メモリデバイスであって、
半導体材料で構成された基板であって、前記基板自身に回路構造を含まない基板と、
複数のインターリーブされた導体層および誘電体層を含む、前記基板上のメモリスタックと、
前記メモリスタックの一方の側にある階段構造と、
前記メモリスタックの前記階段構造を貫通して垂直に延在する階段貫通コンタクト(TSC)であって、前記TSCは前記基板と接触している、TSC、
前記メモリスタックの外側の周辺コンタクトであって、前記周辺コンタクトは前記基板と接触している、周辺コンタクトと、とを備え、
前記TSCおよび周辺コンタクトの各々の側壁は、名目上同じ厚さを有するスペーサによって囲まれている、
3Dメモリデバイス。 - 前記周辺コンタクトおよび前記TSCが同じ材料を含む、
請求項13に記載の3Dメモリデバイス。
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Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3850660A4 (en) * | 2019-01-02 | 2022-05-04 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL STORAGE ARRANGEMENTS WITH CONTINUOUS STAIR CONTACTS AND METHOD FOR THEIR MANUFACTURE |
WO2021026819A1 (en) * | 2019-08-14 | 2021-02-18 | Yangtze Memory Technologies Co., Ltd. | Vertical memory devices |
CN110770903B (zh) | 2019-08-23 | 2021-01-29 | 长江存储科技有限责任公司 | 竖直存储器件 |
CN110741475A (zh) * | 2019-08-29 | 2020-01-31 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
TWI738073B (zh) * | 2019-10-04 | 2021-09-01 | 旺宏電子股份有限公司 | 記憶體元件及其製作方法 |
CN110828472B (zh) * | 2019-10-14 | 2023-08-18 | 长江存储科技有限责任公司 | 三维存储器及其制备方法、及电子设备 |
TWI717063B (zh) * | 2019-10-18 | 2021-01-21 | 旺宏電子股份有限公司 | 三維及式快閃記憶體及其製造方法 |
CN111180344B (zh) * | 2020-01-02 | 2021-12-07 | 长江存储科技有限责任公司 | 三维堆叠结构及制备方法 |
US11302710B2 (en) * | 2020-01-10 | 2022-04-12 | Micron Technology, Inc. | Foundational supports within integrated assemblies |
JP2022528707A (ja) | 2020-01-21 | 2022-06-15 | 長江存儲科技有限責任公司 | 3次元メモリデバイスの相互接続構造 |
CN111403404B (zh) * | 2020-03-02 | 2021-08-13 | 长江存储科技有限责任公司 | 存储结构及其制备方法 |
US11158622B1 (en) | 2020-05-27 | 2021-10-26 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices |
US11877448B2 (en) | 2020-05-27 | 2024-01-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices |
US11963349B2 (en) | 2020-05-27 | 2024-04-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
JP7297923B2 (ja) | 2020-05-27 | 2023-06-26 | 長江存儲科技有限責任公司 | 3次元メモリデバイス及び方法 |
KR20210152471A (ko) * | 2020-06-05 | 2021-12-15 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 3차원 메모리 디바이스의 계단 구조와 그 형성 방법 |
KR20210158449A (ko) * | 2020-06-23 | 2021-12-31 | 삼성전자주식회사 | 반도체 장치 |
TWI756781B (zh) * | 2020-07-07 | 2022-03-01 | 大陸商長江存儲科技有限責任公司 | 用於形成立體記憶元件的方法 |
CN112119497B (zh) * | 2020-08-17 | 2024-01-30 | 长江存储科技有限责任公司 | 在存储块之间具有稳定结构的三维存储器件以及用于形成其的方法 |
CN114156267A (zh) * | 2020-09-07 | 2022-03-08 | 长鑫存储技术有限公司 | 半导体器件及其制备方法、存储装置 |
CN112038346B (zh) * | 2020-09-10 | 2024-05-07 | 长江存储科技有限责任公司 | 三维存储器及三维存储器制作方法 |
US20220231050A1 (en) * | 2021-01-15 | 2022-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device and method of forming the same |
JP2022145313A (ja) * | 2021-03-19 | 2022-10-04 | キオクシア株式会社 | 半導体記憶装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170148748A1 (en) | 2015-11-25 | 2017-05-25 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor devices with scribe line region structures |
US20170236746A1 (en) | 2016-02-16 | 2017-08-17 | Sandisk Technologies Llc | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof |
CN108447865A (zh) | 2018-04-19 | 2018-08-24 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
US20180301374A1 (en) | 2017-04-17 | 2018-10-18 | Sandisk Technologies Llc | Three-dimensional memory device having conductive support structures and method of making thereof |
CN108766971A (zh) | 2018-06-06 | 2018-11-06 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
US10141326B1 (en) | 2017-09-05 | 2018-11-27 | SK Hynix Inc. | Semiconductor memory device |
US20180350825A1 (en) | 2017-06-01 | 2018-12-06 | Sandisk Technologies Llc | Mid-plane word line switch connection for cmos under three-dimensional memory device and method of making thereof |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8786007B2 (en) * | 2008-12-03 | 2014-07-22 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory device |
KR101965602B1 (ko) * | 2012-10-16 | 2019-04-04 | 삼성전자주식회사 | 3차원 반도체 장치의 제조 방법 및 이에 따라 제조된 3차원 반도체 장치 |
CN103904031B (zh) * | 2012-12-26 | 2016-11-09 | 旺宏电子股份有限公司 | 半导体结构制造方法及制成的结构 |
KR102044275B1 (ko) * | 2013-07-31 | 2019-11-14 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
KR102183713B1 (ko) * | 2014-02-13 | 2020-11-26 | 삼성전자주식회사 | 3차원 반도체 장치의 계단형 연결 구조 및 이를 형성하는 방법 |
US10038006B2 (en) * | 2015-12-22 | 2018-07-31 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
US9659956B1 (en) * | 2016-01-06 | 2017-05-23 | Sandisk Technologies Llc | Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation |
US9589978B1 (en) | 2016-02-25 | 2017-03-07 | Micron Technology, Inc. | Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly under the staircase |
US10043751B2 (en) | 2016-03-30 | 2018-08-07 | Intel Corporation | Three dimensional storage cell array with highly dense and scalable word line design approach |
US10256248B2 (en) * | 2016-06-07 | 2019-04-09 | Sandisk Technologies Llc | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof |
US10121794B2 (en) * | 2016-06-20 | 2018-11-06 | Sandisk Technologies Llc | Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof |
US9576967B1 (en) * | 2016-06-30 | 2017-02-21 | Sandisk Technologies Llc | Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings |
KR102626036B1 (ko) * | 2016-08-19 | 2024-01-18 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US10115440B2 (en) | 2017-01-10 | 2018-10-30 | Sandisk Technologies Llc | Word line contact regions for three-dimensional non-volatile memory |
CN107658315B (zh) * | 2017-08-21 | 2019-05-14 | 长江存储科技有限责任公司 | 半导体装置及其制备方法 |
US10283452B2 (en) * | 2017-09-15 | 2019-05-07 | Yangtze Memory Technology Co., Ltd. | Three-dimensional memory devices having a plurality of NAND strings |
CN107658317B (zh) * | 2017-09-15 | 2019-01-01 | 长江存储科技有限责任公司 | 一种半导体装置及其制备方法 |
US10727248B2 (en) * | 2018-02-15 | 2020-07-28 | Sandisk Technologies Llc | Three-dimensional memory device containing through-memory-level contact via structures |
KR102639721B1 (ko) | 2018-04-13 | 2024-02-26 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
EP3850660A4 (en) * | 2019-01-02 | 2022-05-04 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL STORAGE ARRANGEMENTS WITH CONTINUOUS STAIR CONTACTS AND METHOD FOR THEIR MANUFACTURE |
-
2019
- 2019-01-02 EP EP19907062.4A patent/EP3850660A4/en active Pending
- 2019-01-02 WO PCT/CN2019/070009 patent/WO2020140190A1/en unknown
- 2019-01-02 JP JP2021530999A patent/JP7328334B2/ja active Active
- 2019-01-02 CN CN201980000179.1A patent/CN109844931B/zh active Active
- 2019-01-02 KR KR1020217013551A patent/KR20210062083A/ko not_active Application Discontinuation
- 2019-01-02 KR KR1020247012324A patent/KR20240052893A/ko not_active Application Discontinuation
- 2019-02-22 TW TW108105912A patent/TWI667774B/zh active
- 2019-03-04 US US16/292,268 patent/US10847539B2/en active Active
-
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- 2020-11-13 US US17/097,635 patent/US11716846B2/en active Active
-
2023
- 2023-05-24 US US18/201,660 patent/US20230301105A1/en not_active Abandoned
- 2023-08-03 JP JP2023126900A patent/JP2023145697A/ja active Pending
- 2023-09-28 US US18/374,507 patent/US20240023333A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170148748A1 (en) | 2015-11-25 | 2017-05-25 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor devices with scribe line region structures |
US20170236746A1 (en) | 2016-02-16 | 2017-08-17 | Sandisk Technologies Llc | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof |
US20180301374A1 (en) | 2017-04-17 | 2018-10-18 | Sandisk Technologies Llc | Three-dimensional memory device having conductive support structures and method of making thereof |
US20180350825A1 (en) | 2017-06-01 | 2018-12-06 | Sandisk Technologies Llc | Mid-plane word line switch connection for cmos under three-dimensional memory device and method of making thereof |
US10141326B1 (en) | 2017-09-05 | 2018-11-27 | SK Hynix Inc. | Semiconductor memory device |
CN108447865A (zh) | 2018-04-19 | 2018-08-24 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
CN108766971A (zh) | 2018-06-06 | 2018-11-06 | 长江存储科技有限责任公司 | 三维存储器及其制造方法 |
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TW202027258A (zh) | 2020-07-16 |
KR20210062083A (ko) | 2021-05-28 |
KR20240052893A (ko) | 2024-04-23 |
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