JP2023514283A - バックサイドソースコンタクトを備える3次元メモリデバイスを形成するための方法 - Google Patents
バックサイドソースコンタクトを備える3次元メモリデバイスを形成するための方法 Download PDFInfo
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- JP2023514283A JP2023514283A JP2022549345A JP2022549345A JP2023514283A JP 2023514283 A JP2023514283 A JP 2023514283A JP 2022549345 A JP2022549345 A JP 2022549345A JP 2022549345 A JP2022549345 A JP 2022549345A JP 2023514283 A JP2023514283 A JP 2023514283A
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Abstract
Description
101 基板
102 第1の半導体構造
104 第2の半導体構造
106 接合界面
108 周辺回路
110 接合層
111 接合コンタクト
112 接合層
113 接合コンタクト
114 メモリスタック
116 導電体層
118 誘電体層
120 第1の半導体層
122 第2の半導体層
124 チャネル構造
126 メモリ膜
128 半導体チャネル
129 チャネルプラグ
130 絶縁構造
132 ソースコンタクト、バックサイドソースコンタクト
133 相互接続層
134 ILD層
136 再配線層
138 パッシベーション層
140 コンタクトパッド
142、144 コンタクト
146、148 周辺コンタクト
150 チャネルローカルコンタクト
152 ワード線ローカルコンタクト
200 3Dメモリデバイス
202 ブロック
204 階段領域
206 コアアレイ領域
206A 第1のコアアレイ領域
206B 第2のコアアレイ領域
208 絶縁構造
209 バックサイドソース線
210 チャネル構造
211 Nウェルピックアップコンタクト
212 ドレインセレクトゲートカット
213 パッドアウトコンタクト
214 領域
215 ソースコンタクト
302 シリコン基板
304 N型ドープ半導体層
305 パッド酸化物層
306 犠牲層
308 誘電体スタック
310 スタック誘電体層
312 スタック犠牲層
314 チャネル構造
316 メモリ膜
318 半導体チャネル
320 スリット
322 キャビティ
324 スペーサ
326 N型ドープ半導体層
328 スタック導電体層
330 メモリスタック
332 ゲート誘電体層
334 誘電体キャッピング層
336 絶縁構造
338、340 周辺コンタクト
342 ワード線ローカルコンタクト
344 チャネルローカルコンタクト
346 接合層
348 接合層
350 シリコン基板
352 周辺回路
354 接合界面
356 ILD層
358 ソースコンタクト開口部
360、361 コンタクト開口部
362 スペーサ
364 ソースコンタクト、バックサイドソースコンタクト
366、368 コンタクト
370 再配線層
372 パッシベーション層
374 コンタクトパッド
376 相互接続層
400 方法
Claims (21)
- 3次元(3D)メモリデバイスを形成するための方法であって、
続いて、犠牲層を基板の第1の側における第2の半導体層よりも上に、誘電体スタックを前記犠牲層上に形成するステップと、
前記誘電体スタックおよび前記犠牲層を垂直方向に貫通し、前記第2の半導体層内に貫入するチャネル構造を形成するステップと、
前記犠牲層を、前記第2の半導体層と接触している第1の半導体層に置き換えるステップと、
前記誘電体スタックをメモリスタックに置き換え、それにより、前記チャネル構造は、前記メモリスタックおよび前記第1の半導体層を垂直方向に貫通し、前記第2の半導体層内に貫入する、ステップと、
ソースコンタクトを、前記第2の半導体層と接触するように前記基板の前記第1の側と反対の第2の側に形成するステップとを含む方法。 - 前記犠牲層を形成する前に、前記第1の側において、前記基板の一部にN型ドーパントをドープして、前記第2の半導体層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記犠牲層を前記第1の半導体層に置き換えるステップは、
前記誘電体スタックを垂直方向に貫通する開口部を形成して前記犠牲層の一部を露出させるステップと、
前記開口部を通して前記犠牲層をエッチングしてキャビティを形成するステップと、
N型ドープポリシリコンを前記開口部を通して前記キャビティ内に堆積して前記第1の半導体層を形成するステップとを含む、請求項1または2に記載の方法。 - 続いて前記犠牲層および前記誘電体スタックを形成するステップは、
ポリシリコンを前記第2の半導体層上に堆積して、前記犠牲層を形成するステップと、
代替的に、スタック誘電体層およびスタック犠牲層を前記犠牲層上に堆積して前記誘電体スタックを形成するステップとを含む、請求項3に記載の方法。 - 前記誘電体スタックを前記メモリスタックに置き換えるステップは、前記スタック犠牲層を前記開口部を通してスタック導電体層に置き換えるステップを含む、請求項4に記載の方法。
- 前記メモリスタックを形成した後に、1つまたは複数の誘電体材料を前記開口部内に堆積して、前記メモリスタックを垂直方向に貫通する絶縁構造を形成するステップをさらに含む、請求項3から5のいずれか一項に記載の方法。
- 前記ソースコンタクトは、前記絶縁構造に整列される、請求項6に記載の方法。
- 前記ソースコンタクトを形成する前に、前記第2の側から、前記基板を薄化して、前記第2の半導体層を露出させるステップをさらに含む、請求項1から7のいずれか一項に記載の方法。
- 前記ソースコンタクトよりも上にあり、前記ソースコンタクトに電気的に接続されている相互接続層を形成するステップをさらに含む、請求項1から8のいずれか一項に記載の方法。
- 前記第2の半導体層を通り、前記相互接続層と接触する、コンタクトを形成するステップをさらに含み、それにより前記第1の半導体層は、前記第2の半導体層、前記ソースコンタクト、および前記相互接続層を通して前記コンタクトに電気的に接続される、請求項9に記載の方法。
- 3次元(3D)メモリデバイスを形成するための方法であって、
基板の第1の側においてメモリスタックを垂直方向に貫通し、N型ドープ半導体層に貫入するチャネル構造を形成するステップであって、前記メモリスタックは、交互配置されたスタック導電体層およびスタック誘電体層を含む、ステップと、
垂直方向に前記メモリスタックを貫通する開口部内に絶縁構造を形成するステップと、
前記N型ドープ半導体層と接触し、前記絶縁構造に整列されるように前記基板の前記第1の側と反対の第2の側にソースコンタクトを形成するステップとを含む方法。 - 前記チャネル構造を形成するステップは、
前記第1の側において、前記基板の一部にN型ドーパントをドープして、第2のN型ドープ半導体層を形成するステップと、
続いて前記第2のN型ドープ半導体層よりも上に犠牲層を、前記犠牲層上に誘電体スタックを形成するステップであって、前記誘電体層は、交互配置されたスタック犠牲層および前記スタック誘電体層を含む、ステップと、
前記誘電体スタックおよび前記犠牲層を垂直方向に貫通し、前記第2のN型ドープ半導体層内に貫入する前記チャネル構造を形成するステップと、
前記犠牲層を、前記開口部を通して第1のN型ドープ半導体層で置き換えるステップとを含む、請求項11に記載の方法。 - 前記チャネル構造を形成するステップは、前記スタック犠牲層を前記スタック導電体層で置き換えて、前記メモリスタックを形成するステップをさらに含む、請求項12に記載の方法。
- 前記絶縁構造を形成するステップは、前記スタック犠牲層を前記スタック導電体層で置き換えた後に、前記開口部に1つまたは複数の誘電体材料を充填するステップを含む、請求項13に記載の方法。
- 前記ソースコンタクトを形成する前に、前記第2の側から、前記基板を薄化して、前記第2のN型ドープ半導体層を露出させるステップをさらに含む、請求項12から14のいずれか一項に記載の方法。
- 3次元(3D)メモリデバイスを形成するための方法であって、
第1の基板上に周辺回路を形成するステップと、
メモリスタックおよび第1の半導体層を垂直方向に貫通し、第2の基板上の第2の半導体層内に貫入するチャネル構造を形成するステップと、
前記第1の基板と前記第2の基板とを向かい合わせに接合し、それにより前記メモリスタックが前記周辺回路よりも上に来るようにする、ステップと、
前記第2の基板を薄化して、前記第2の半導体層を露出させるステップと、
前記メモリスタックより上にあり、前記第2の半導体層と接触しているソースコンタクトを形成するステップとを含む方法。 - 前記チャネル構造を形成するステップは、
前記第2の基板の一部にN型ドーパントをドープして前記第2の半導体層を形成するステップと、
続いて前記第2の半導体層よりも上に犠牲層を、前記犠牲層上に誘電体スタックを形成するステップと、
前記誘電体スタックおよび前記犠牲層を垂直方向に貫通し、前記第2の半導体層内に貫入する前記チャネル構造を形成するステップと、
前記犠牲層をN型ドープ半導体層で置き換えて前記第1の半導体層を形成するステップとを含む、請求項16に記載の方法。 - 前記チャネル構造を形成するステップは、前記誘電体スタックを前記メモリスタックで置き換えるステップをさらに含む、請求項17に記載の方法。
- 前記第1の基板と前記第2の基板とを接合する前に、前記メモリスタックを垂直方向に貫通する絶縁構造を形成するステップであって、前記ソースコンタクトは、前記絶縁構造に整列される、ステップをさらに含む、請求項16から18のいずれか一項に記載の方法。
- 前記ソースコンタクトよりも上にあり、前記ソースコンタクトに接触している相互接続層を形成するステップをさらに含む、請求項16から19のいずれか一項に記載の方法。
- 前記第2の半導体層を通り、前記相互接続層と接触する、コンタクトを形成するステップをさらに含み、それにより前記第1の半導体層は、前記第2の半導体層、前記ソースコンタクト、および前記相互接続層を通して前記コンタクトに電気的に接続される、請求項20に記載の方法。
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