CN115910160A - 具有很细节距的三维nor存储器阵列:装置和方法 - Google Patents

具有很细节距的三维nor存储器阵列:装置和方法 Download PDF

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Publication number
CN115910160A
CN115910160A CN202211141679.7A CN202211141679A CN115910160A CN 115910160 A CN115910160 A CN 115910160A CN 202211141679 A CN202211141679 A CN 202211141679A CN 115910160 A CN115910160 A CN 115910160A
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conductors
conductor
layer
data storage
memory
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Chinese (zh)
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E.哈拉里
S.B.赫纳
W-Y.钱
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Sunrise Memory Corp
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Sunrise Memory Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/037Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CN202211141679.7A 2017-12-28 2018-12-21 具有很细节距的三维nor存储器阵列:装置和方法 Pending CN115910160A (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201762611205P 2017-12-28 2017-12-28
US62/611,205 2017-12-28
US201862752092P 2018-10-29 2018-10-29
US62/752,092 2018-10-29
CN201880090142.8A CN111742368B (zh) 2017-12-28 2018-12-21 具有很细节距的三维nor存储器阵列:装置和方法
PCT/US2018/067338 WO2019133534A1 (en) 2017-12-28 2018-12-21 3-dimensional nor memory array with very fine pitch: device and method

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CN115910160A true CN115910160A (zh) 2023-04-04

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CN201880090142.8A Active CN111742368B (zh) 2017-12-28 2018-12-21 具有很细节距的三维nor存储器阵列:装置和方法

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US (5) US10622377B2 (enExample)
JP (2) JP7072658B2 (enExample)
KR (2) KR102457732B1 (enExample)
CN (2) CN115910160A (enExample)
WO (1) WO2019133534A1 (enExample)

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