CN1149737C - 半导体集成电路 - Google Patents
半导体集成电路 Download PDFInfo
- Publication number
- CN1149737C CN1149737C CNB971222088A CN97122208A CN1149737C CN 1149737 C CN1149737 C CN 1149737C CN B971222088 A CNB971222088 A CN B971222088A CN 97122208 A CN97122208 A CN 97122208A CN 1149737 C CN1149737 C CN 1149737C
- Authority
- CN
- China
- Prior art keywords
- circuit
- effect transistor
- field effect
- mentioned
- channel field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9066973A JPH10261946A (ja) | 1997-03-19 | 1997-03-19 | 半導体集積回路 |
| JP66973/1997 | 1997-03-19 | ||
| JP66973/97 | 1997-03-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1193846A CN1193846A (zh) | 1998-09-23 |
| CN1149737C true CN1149737C (zh) | 2004-05-12 |
Family
ID=13331485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971222088A Expired - Fee Related CN1149737C (zh) | 1997-03-19 | 1997-11-05 | 半导体集成电路 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6031778A (enExample) |
| JP (1) | JPH10261946A (enExample) |
| KR (1) | KR100300144B1 (enExample) |
| CN (1) | CN1149737C (enExample) |
| TW (1) | TW472445B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790912B (zh) * | 2004-11-01 | 2010-06-23 | 日本电气株式会社 | 半导体集成电路装置 |
Families Citing this family (66)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3732914B2 (ja) * | 1997-02-28 | 2006-01-11 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP3341681B2 (ja) * | 1998-06-12 | 2002-11-05 | 日本電気株式会社 | 半導体集積論理回路 |
| US6329874B1 (en) * | 1998-09-11 | 2001-12-11 | Intel Corporation | Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode |
| JP4397062B2 (ja) * | 1998-11-27 | 2010-01-13 | 株式会社ルネサステクノロジ | 電圧発生回路および半導体記憶装置 |
| US6166985A (en) * | 1999-04-30 | 2000-12-26 | Intel Corporation | Integrated circuit low leakage power circuitry for use with an advanced CMOS process |
| US6512406B1 (en) * | 1999-12-16 | 2003-01-28 | Intel Corporation | Backgate biased synchronizing latch |
| JP2002064150A (ja) * | 2000-06-05 | 2002-02-28 | Mitsubishi Electric Corp | 半導体装置 |
| TW501278B (en) * | 2000-06-12 | 2002-09-01 | Intel Corp | Apparatus and circuit having reduced leakage current and method therefor |
| US6744301B1 (en) * | 2000-11-07 | 2004-06-01 | Intel Corporation | System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise |
| DE10120790A1 (de) * | 2001-04-27 | 2002-11-21 | Infineon Technologies Ag | Schaltungsanordnung zur Verringerung der Versorgungsspannung eines Schaltungsteils sowie Verfahren zum Aktivieren eines Schaltungsteils |
| US6586817B1 (en) | 2001-05-18 | 2003-07-01 | Sun Microsystems, Inc. | Device including a resistive path to introduce an equivalent RC circuit |
| US6583001B1 (en) | 2001-05-18 | 2003-06-24 | Sun Microsystems, Inc. | Method for introducing an equivalent RC circuit in a MOS device using resistive paths |
| US6489224B1 (en) | 2001-05-31 | 2002-12-03 | Sun Microsystems, Inc. | Method for engineering the threshold voltage of a device using buried wells |
| US6624687B1 (en) | 2001-05-31 | 2003-09-23 | Sun Microsystems, Inc. | Method and structure for supply gated electronic components |
| US6552601B1 (en) | 2001-05-31 | 2003-04-22 | Sun Microsystems, Inc. | Method for supply gating low power electronic devices |
| US6489804B1 (en) | 2001-06-01 | 2002-12-03 | Sun Microsystems, Inc. | Method for coupling logic blocks using low threshold pass transistors |
| US6621318B1 (en) * | 2001-06-01 | 2003-09-16 | Sun Microsystems, Inc. | Low voltage latch with uniform sizing |
| US6472919B1 (en) | 2001-06-01 | 2002-10-29 | Sun Microsystems, Inc. | Low voltage latch with uniform stack height |
| US6605971B1 (en) | 2001-06-01 | 2003-08-12 | Sun Microsystems, Inc. | Low voltage latch |
| US6501295B1 (en) | 2001-06-01 | 2002-12-31 | Sun Microsystems, Inc. | Overdriven pass transistors |
| JP2003031681A (ja) * | 2001-07-16 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
| US6538471B1 (en) | 2001-10-10 | 2003-03-25 | International Business Machines Corporation | Multi-threshold flip-flop circuit having an outside feedback |
| JP2003132683A (ja) * | 2001-10-23 | 2003-05-09 | Hitachi Ltd | 半導体装置 |
| US6731157B2 (en) * | 2002-01-15 | 2004-05-04 | Honeywell International Inc. | Adaptive threshold voltage control with positive body bias for N and P-channel transistors |
| JP3951773B2 (ja) * | 2002-03-28 | 2007-08-01 | 富士通株式会社 | リーク電流遮断回路を有する半導体集積回路 |
| JP4122954B2 (ja) * | 2002-12-06 | 2008-07-23 | 沖電気工業株式会社 | 半導体集積回路 |
| US7053692B2 (en) * | 2002-12-19 | 2006-05-30 | United Memories, Inc. | Powergate control using boosted and negative voltages |
| JP4232477B2 (ja) * | 2003-02-13 | 2009-03-04 | パナソニック株式会社 | 半導体集積回路の検証方法 |
| JP3825756B2 (ja) * | 2003-02-17 | 2006-09-27 | 富士通株式会社 | 半導体集積回路 |
| JP2004336010A (ja) | 2003-04-16 | 2004-11-25 | Seiko Epson Corp | 半導体集積回路、電子機器、及びトランジスタのバックゲート電位制御方法 |
| KR100574967B1 (ko) * | 2004-01-29 | 2006-04-28 | 삼성전자주식회사 | Mtcmos용 제어회로 |
| JP2007536771A (ja) * | 2004-02-19 | 2007-12-13 | モスエイド テクノロジーズ コーポレーション | 低漏出のデータ保持回路 |
| US7227383B2 (en) | 2004-02-19 | 2007-06-05 | Mosaid Delaware, Inc. | Low leakage and data retention circuitry |
| EP1759460B1 (en) * | 2004-06-15 | 2012-08-01 | ST-Ericsson SA | Adaptive control of power supply for integrated circuits |
| US7382178B2 (en) | 2004-07-09 | 2008-06-03 | Mosaid Technologies Corporation | Systems and methods for minimizing static leakage of an integrated circuit |
| KR100560822B1 (ko) * | 2004-09-02 | 2006-03-13 | 삼성전자주식회사 | 리플-프리 내부 전압을 발생하는 반도체 장치 |
| KR100585174B1 (ko) * | 2004-10-08 | 2006-05-30 | 삼성전자주식회사 | 데이터 레이트에 따라 전력 소비를 조절할 수 있는 출력드라이버 |
| CN101069350B (zh) * | 2004-11-30 | 2012-05-23 | 飞思卡尔半导体公司 | 使用选择性电源选通来降低功耗的设备和方法 |
| JP2006172264A (ja) * | 2004-12-17 | 2006-06-29 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置および信号処理システム |
| JP4197678B2 (ja) * | 2004-12-24 | 2008-12-17 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| JPWO2007102188A1 (ja) * | 2006-03-03 | 2009-07-23 | 富士通株式会社 | 半導体記憶装置 |
| US7821050B1 (en) * | 2006-07-31 | 2010-10-26 | Altera Corporation | CRAM transistors with high immunity to soft error |
| JP2008085571A (ja) * | 2006-09-27 | 2008-04-10 | Nec Electronics Corp | 半導体集積回路 |
| US20080211568A1 (en) * | 2007-03-01 | 2008-09-04 | Infineon Technologies Ag | MuGFET POWER SWITCH |
| JP4733084B2 (ja) * | 2007-08-09 | 2011-07-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2008125095A (ja) * | 2007-11-29 | 2008-05-29 | Renesas Technology Corp | 半導体回路装置 |
| JP2008159246A (ja) * | 2007-12-21 | 2008-07-10 | Renesas Technology Corp | 半導体装置 |
| KR20100121475A (ko) * | 2008-01-30 | 2010-11-17 | 에이저 시스템즈 인크 | 전자 회로의 수율을 증가시키는 방법 및 장치 |
| CN101682325B (zh) * | 2008-02-27 | 2013-06-05 | 松下电器产业株式会社 | 半导体集成电路以及包括该半导体集成电路的各种装置 |
| US20110204148A1 (en) | 2008-07-21 | 2011-08-25 | Stuart Colin Littlechild | Device having data storage |
| CN101814315B (zh) * | 2010-04-29 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | 可增加写入裕量的静态随机存取存储器 |
| WO2012017843A1 (en) * | 2010-08-06 | 2012-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit |
| JP2010282721A (ja) * | 2010-08-09 | 2010-12-16 | Renesas Electronics Corp | 半導体装置 |
| WO2012098900A1 (ja) * | 2011-01-20 | 2012-07-26 | パナソニック株式会社 | 半導体記憶装置 |
| WO2013018217A1 (ja) * | 2011-08-03 | 2013-02-07 | 富士通株式会社 | 半導体集積回路及びラッチ回路の駆動方法 |
| KR20130053603A (ko) * | 2011-11-15 | 2013-05-24 | 에스케이하이닉스 주식회사 | 증폭 회로 및 반도체 메모리 장치 |
| US9110484B2 (en) | 2013-09-24 | 2015-08-18 | Freescale Semiconductor, Inc. | Temperature dependent biasing for leakage power reduction |
| US9472948B2 (en) * | 2013-09-30 | 2016-10-18 | Infineon Technologies Ag | On chip reverse polarity protection compliant with ISO and ESD requirements |
| US9672902B1 (en) * | 2016-08-03 | 2017-06-06 | Apple Inc. | Bit-cell voltage control system |
| DK3343769T3 (da) * | 2016-12-27 | 2019-05-06 | Gn Hearing As | Integreret kredsløb, der omfatter justerbar spærreforspænding af én eller flere logiske kredsløbsregioner |
| JP6383041B2 (ja) * | 2017-04-06 | 2018-08-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US10678287B2 (en) * | 2018-10-15 | 2020-06-09 | Globalfoundries Inc. | Positive and negative full-range back-bias generator circuit structure |
| JP2019109958A (ja) * | 2019-03-07 | 2019-07-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| CN111725857B (zh) * | 2019-03-21 | 2022-02-15 | 东莞新能安科技有限公司 | 开关驱动电路及电池控制电路 |
| US11942779B2 (en) * | 2019-10-30 | 2024-03-26 | Skyworks Solutions, Inc. | Shutdown mode for bandgap and bias circuit with voltage comparator to reduce leakage current |
| US11237580B1 (en) * | 2020-09-09 | 2022-02-01 | Qualcomm Incorporated | Systems and methods providing leakage reduction for power gated domains |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0340294A (ja) * | 1989-07-05 | 1991-02-21 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| JP3184265B2 (ja) * | 1991-10-17 | 2001-07-09 | 株式会社日立製作所 | 半導体集積回路装置およびその制御方法 |
| US5461338A (en) * | 1992-04-17 | 1995-10-24 | Nec Corporation | Semiconductor integrated circuit incorporated with substrate bias control circuit |
| JP3342730B2 (ja) * | 1993-03-17 | 2002-11-11 | 富士通株式会社 | 不揮発性半導体記憶装置 |
| JPH07130175A (ja) * | 1993-09-10 | 1995-05-19 | Toshiba Corp | 半導体記憶装置 |
| KR0169157B1 (ko) * | 1993-11-29 | 1999-02-01 | 기다오까 다까시 | 반도체 회로 및 mos-dram |
| JP3245663B2 (ja) * | 1994-01-19 | 2002-01-15 | 日本電信電話株式会社 | 論理回路 |
| JP3125081B2 (ja) * | 1994-01-19 | 2001-01-15 | 日本電信電話株式会社 | 論理回路 |
| JPH07296587A (ja) * | 1994-04-28 | 1995-11-10 | Sony Corp | スタンバイ電流制御回路 |
| JP3549602B2 (ja) * | 1995-01-12 | 2004-08-04 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
-
1997
- 1997-03-19 JP JP9066973A patent/JPH10261946A/ja active Pending
- 1997-06-12 TW TW086108152A patent/TW472445B/zh not_active IP Right Cessation
- 1997-07-23 US US08/899,306 patent/US6031778A/en not_active Expired - Lifetime
- 1997-09-04 KR KR1019970045839A patent/KR100300144B1/ko not_active Expired - Fee Related
- 1997-11-05 CN CNB971222088A patent/CN1149737C/zh not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790912B (zh) * | 2004-11-01 | 2010-06-23 | 日本电气株式会社 | 半导体集成电路装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980079348A (ko) | 1998-11-25 |
| JPH10261946A (ja) | 1998-09-29 |
| TW472445B (en) | 2002-01-11 |
| US6031778A (en) | 2000-02-29 |
| CN1193846A (zh) | 1998-09-23 |
| KR100300144B1 (ko) | 2001-09-03 |
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Legal Events
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |