CN1113607A - 芯片封装、芯片载体和用于电路基板的端电极及其制法 - Google Patents

芯片封装、芯片载体和用于电路基板的端电极及其制法 Download PDF

Info

Publication number
CN1113607A
CN1113607A CN94112790A CN94112790A CN1113607A CN 1113607 A CN1113607 A CN 1113607A CN 94112790 A CN94112790 A CN 94112790A CN 94112790 A CN94112790 A CN 94112790A CN 1113607 A CN1113607 A CN 1113607A
Authority
CN
China
Prior art keywords
carrier
chip
electrode
circuit substrate
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN94112790A
Other languages
English (en)
Other versions
CN1048824C (zh
Inventor
户村善广
别所芳宏
箱谷靖彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1113607A publication Critical patent/CN1113607A/zh
Application granted granted Critical
Publication of CN1048824C publication Critical patent/CN1048824C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10719—Land grid array [LGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0577—Double layer of resist having the same pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的芯片载体包括：具有上表面、下表面和 内部导体的载体；在载体的上表面上所形成的多个端 电极，用于使LSI芯片和内部导线相连接。在载体 的下表面上形成了多个凹入部分，用于使一个电路基 板上的多个电极与上述内部导线之间实现电气连接， 这些凹入部分与内部导线相电气连接。

Description

本发明涉及的是：一种芯片封装、一种芯片载体和用于制造该芯片载体的方法、一种用于电路基板的端电极和用于制作该端电极的方法、以及包括安装在电路基板上的上述芯片封装的复合体（此后将“安装了芯片封装的复合体”简称为复合体）。
近年来，LSI（大规模集成电路）的集成度显著地提高了，因此一个LSI芯片的引脚数目也在增多。对于采用LSI芯片封装的电子设备来说，却希望减小其大小和厚度，因而发展了一些高密度安装技术，用于将LSI芯片以高密度安装在电路基板上。对这样的LSI芯片封装的形状和结构提出了各种建议（参见NIKKEI  ELECTRONICS1993.8.2，No.587，“LSI封装展望，促进高密度安装”，PP93-99）。
在本说明书中，“芯片载体”指的是包括端电极（用于和LSI芯片的电极相连接）和接触电极（用于和电路基板相连接）的基片;“芯片封装”指的是其上安装了LSI芯片的芯片载体;芯片封装作为一个整体安装在一个电路基板上，形成一个“安装了芯片封装的复合体”。
下面将概略地介绍将常规芯片封装安装在一个电路基板上的已知方法。
首先，芯片载体是以如下的方式来形成的。通过采用激光束或者冲模技术，在一个印刷电路板上形成通路孔。除了采用印刷电路板之外，也可以采用陶瓷板。在印刷电路板上预先形成了端电极。此后，通过电镀或类似技术使印刷电路板中的内部导体与端电极相连接。其后，采用小片接合方式将LSI芯片以朝上的状态粘结在上述芯片载体的上表面上，再采用丝焊接方式将LSI芯片的电极焊盘与芯片载体上表面上的端电极相连接。在所获得的组合产品上，采用模塑树脂来覆盖LSI芯片和焊丝，从而密封该组合产品。
其次，采用印刷和类似方法，在设置在印刷电路板下表面（亦即在将芯片封装安装在电路基板上时与电路基板相对的表面）上的电极上形成一层焊料层。此后，采用红外线回流或类似技术来熔化上述焊料层，形成焊球（其直径大约为700μm）。这样，就获得了芯片载体。也可以将预先准备好的焊料球粘结在芯片载体的端电极上，从而获得芯片封装。
再其次，将芯片封装置于这样的位置上，亦即使上述焊料球位于电路基板上的预定位置上。此后，将芯片封装置于电路基板上，采用红外线回流或类似技术熔化上述焊料球，从而使芯片封装下表面上的端电极与电路基板上的端电极相连接。这样，就获得了安装了芯片封装的复合体。
然而，上述已知技术存在如下的问题：
1.由于为了使芯片载体的端电极与LSI芯片的电极焊盘相连接而进行了丝焊，因此芯片载体所占据的面积大于LSI芯片的面积。另外，由于在丝焊连接之后进行模塑树脂密封，因此所获得的芯片封装的厚度大于焊丝的环线高度。这一点阻碍了芯片封装大小和厚度的减小。
2.由于信号需要通过具有较长长度的焊丝，输入/输出信号有可能被延迟，因此降低了芯片封装的高频特性，使芯片封装有可能产生噪音。
3.成阵列地配置于芯片封装下表面上的焊料球妨碍了LSI芯片上的端子之间距离的减小。一般说来，焊料球之间需要有大约1mm的距离。
4.焊料球的大小决定了芯片封装和电路基板之间的距离。换句话说，芯片封装和电路基板之间的间距不可能小于焊料球的大小。
5.当芯片载体是采用不同于电路基板的材料制成时，由热冲击所产生的应力将会集中在焊料连接部分上，因而造成裂缝，其结果会增大焊料连接部分的电阻。
本发明提供的芯片载体包括：具有上表面、下表面和内部导线;在载体的上表面上所形成的多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接;在载体的下表面上形成了多个凹入部位，用于使一个电路基板上的多个电极与上述内部导线之间实现电气连接，这些凹入部位与内部导体相电气连接。
在本发明的一种实施例中，上述芯片载体进一步包括多个接触电极，它们与电路基板上的电极相连接，上述接触电极被埋设在相应的凹入部分中，并由导电性粘结剂构成。
在本发明的另一种实施例中，上述多个接触电极由载体的下表面向外凸出。
在本发明的再一种实施例中，上述载体包括多个通路孔;内部导线的至少一部分由设置在上述通路孔中的导电性材料构成;载体的至少某些凹入部位由上述多个通路孔构成。
在本发明的再一种实施例中，载体是由多层相互层叠在一起的绝缘层构成，载体具有多个通路孔，用于将载体的上下表面连接在一起，所述的内部导线由设置在多个通路孔中的导电性粘结材料和设置在所述多层绝缘层中的至少一层上的导电层组成。
在本发明的再一种实施例中，所述导电性粘结剂具有柔性。
在本发明的再一种实施例中，内部导体由一种从由Cu、Ag和AgPd中选出的材料制成。
另外，本发明的芯片封装由芯片载体和一个以芯片倒装方式安装在载体上的LSI芯片组成，其中芯片载体包括：具有上表面、下表面和内部导体的载体;载体的上表面上形成多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接;多个凹入部位，用于使一个电路基板上的多个电极与上述内部导线实现电气连接，这些凹入部位设置在载体的下表面上;其中LSI芯片包括：设置在LSI芯片上的电极焊盘以及在电极焊盘上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的焊结层实现电气连接，LSI芯片和芯片载体之间的空隙用模塑树脂来填充和密封。
在本发明的一种实施例中，芯片封装进一步包括与电路基板上的电极相连接的多个接触电极，这些接触电极埋设在相应的多个凹入部位之一中，接触电极由导电性粘结剂构成。
在本发明的另一种实施例中，LSI芯片的凸型电极具有两级阶梯型的凸型形状。
在本发明的再一种实施例中，所述导电性粘结剂具有柔性。
在本发明的再一种实施例中，所述粘结层由一种从导电性粘结剂、非匀质性导电性材料和焊料中选择出的材料构成。
另外，本发明的芯片封装包括芯片载体和一个以倒装方式安装在芯片载体上LSI芯片，其中芯片载体包括：具有上表面、下表面和内部导体的载体;在载体的上表面上形成的多个端电极，用于使LSI芯片和内部导线之间实现电气连接;多个接触电极，用于使电路基板上的多个电极与内部导线实现电气连接，接触电极设置在载体的下表面上，由导电性粘结剂构成，并埋设在载体下表面上所形成的多个凹入部位中;其中LSI芯片包括：设置在LSI芯片上的电极焊区以及在电极焊区上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的粘结层实现电气连接，LSI芯片和芯片载体之间的空隙用模塑树脂充填密封。
在本发明的一种实施列中，LSI芯片上的凸型电极具有两级阶梯型的凸型形状。
在本发明的另一种实施例中，所述导电性粘结剂具有柔性。
在本发明的再一种实施例中，所述粘结层由一种从导电性粘结剂、非匀质性导电性材料和焊料中选择出的材料构成。
本发明的一种制造芯片载体的方法包括如下步骤：在多层未经烧结的生料板上形成通路孔;在上述多层生料板中的一组上的通路孔中埋设内部导线的一部分，并通过涂覆方法在该组多层生料板上形成内部导线;通过将上述多层生料板中没有将其内部导线的一部分埋设在通路孔之中的生料板层叠在一组将其内部导线的一部分埋设在通路孔之中的生料板上，形成一个多层结构，并对该多层结构进行加压处理;对上述多层结构进行烧结，以便形成载体，在载体的下表面上形成多个凹入部位。
在本发明的一种实施例中，该方法进一步包括通过在载体的多个凹入部位中埋设导电性粘结剂来形成多个接触电极的步骤。
在本发明的另一种实施例中，所述导电性粘结剂具有柔性。
本发明的一种用于其上安装了芯片封装的电路基板的端电极，该端电极在电路基片上形成，并包括：一个在电路基板上形成的下阶梯部分;一个在上述下阶梯部分上形成的上阶梯部分。
在本发明的一种实施例中，所述上阶梯部分在平行于电路基板方向上的截面面积小于下阶梯部分在平行于电路基片方向上的截面面积。
另外，本发明的一种用于在电路基板上制作端电极的方法包括如下步骤：通过第一光刻步骤在电路基板上形成第一保护膜，该第一膜在对应于电路基板上的电极焊盘的位置上具有第一开口;在上述第一保护膜上的第一开口中形成端电极的下阶梯部分;通过第二光刻步骤在电路基板上形成第二保护膜，该第二保护膜在对应于端电极的下阶梯部分的位置上具有第二开口，该第二开口小于上述第一开口;在第二保护膜的第二开口中形成端电极的上阶梯部分;除去上述第一和第二保护膜，从而形成端电极。
本发明的一种安装了芯片封装的复合体，包括安装在电路基板上的芯片封装，而芯片封装包括芯片载体和以倒装方式安装在芯片载体上的LSI芯片，其中芯片载体包括：具有上表面、下表面和内部导线的载体导线;在载体的上表面上所形成的多个端电极，这些多个端电极使LSI芯片和内部导线之间实现电气连接;多个接触电极，用于使电路基板上的多个电极与内部导线实现电气连接，接触电极设置在载体的下表面上，由导电性粘结剂构成，并埋设在载体下表的多个凹入部位中;其中LSI芯片包括：设置在LSI芯片上的电极焊盘以及在电极焊盘上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的粘结层实现电气连接，LSI芯片和芯片载体之间的空隙用模塑树脂来充填密封;其中电路基板的端电极与芯片载体上的相应接触电极相接触。
在本发明的一种实施例中，所述电路基板上的端电极朝着载体上的相应凹入部位向外凸出。
在本发明另一种实施例中，电路基片上的端电极具有两级阶梯型的凸型形状。
根据本发明的芯片载体，用于以倒装方式安装LSI芯片的端电极设置在芯片载体的上表面上。在芯片载体的下表面上设置了用于和电路基板上的电极相连接的接触电极。此外，上述端电极和接触电极通过位于载体之内的内部导线进行电互连。通过使用这样的芯片载体，就能够将LSI芯片中的电路与电路基板上的电路相连接，而不需要占据大的空间。由于LSI芯片和电路基板之间的连接没有采用焊丝，电信号在LSI芯片和电路基板之间传递时只需要通过一个相对短的路径，其结果是和采用焊丝相比较，减小了连接所产生的分布电阻和分布电容，从而改善了芯片组件的高频特性。另外，通过采用载体内部的内部导线和类似物，可以使端电极的布置安排不同于接触电极的布置安排。
另外，所述接触电极是由埋设在载体下表面上的多个凹入部位之中的导电性粘结剂来形成的。导电性粘结剂的作用是一方面以机械方式将载体固定在电路基板上，另一方面使载体的内部导体与电路基板上的端电极实现电气连接。通过使接触电极位于载体下表面上的多个凹入部位之中，就能够减小载体和电路基板之间的间距。由于接触电极是用导电性粘结剂来形成的，接触电极和电路基板之间的连接很稳定，因此提高了可靠性。尤其应指出的是这样的互连能够抵抗热冲击。
根据本发明的用于制造芯片载体的方法，通过在载体下表面上的凹入部位中填入导电性粘结剂，就能够很容易地形成接触电极。
本发明的包括以倒装方式安装在上述芯片载体上的LSI芯片的芯片封装结构紧凑，而且很薄。由于能够以相对简单的方式来进行载体下表面上多个凹入部位中的填入步骤，因此可以由芯片封装的购买者自己在将芯片封装安装在电路基板上之前进行上述填入步骤。
根据本发明，电路基板上的端电极具有凸出的形状，因此能够很容易地插入到构成芯片载体的接触电极的凹入部位中。在本发明的用于制作端电极的方法中，通过采用光刻技术，能够以高的成品率来形成具有两级阶梯形状的微小凸型电极。
在本发明的安装了芯片封装的复合体中，接触电极是用导电性粘结剂来形成的，因此能够保证芯片载体与电路基板上的连接具有机械/电气稳定性。
因此，本发明的优点是：（1）能够提供一种芯片封装，它具有更小的尺寸和厚度，同时具有优良的高频特性，能够高的可靠性和稳定性与电路基板连接;（2）为上述芯片封装提供了一种芯片载体及其制造方法;（3）为电路基板提供了一种适合用于上述芯片封装的端电极及其制作方法，并进一步提供了一种将上述芯片封装安装在电路基板上的复合体。
在结合附图来阅读下面的详细说明之后，本技术领域里的普通技术人员将能够认识到本发明的上述和其他优点。
附图1是本发明的一种芯片封装的剖视图;
附图2是本发明的另一种芯片封装的剖视图;
附图3是本发明的一种芯片载体的剖视图;
附图4是本发明的另一种芯片载体的剖视图;
附图5A至5I是剖视图，显示了用于制作本发明的芯片载体的各个方法步骤;
附图6是剖视图，显示了本发明电路基板上的凸型端电极;
附图7A至7D是剖视图，显示了用于形成如附图6所示凸型端电极的各个方法步骤;
附图8是本发明的装有芯片封装的复合体的剖视图;
附图9是本发明的另一种装有芯片封装的复合体的剖视图。
下面将结合附图对本发明的实施例进行详细说明。
如附图1所示，本实施例的芯片封装19包括一个芯片载体12及一个以倒装方式安装在芯片载体12上的LSI芯片7。
上述LSI芯片7包括多个电极焊盘8和凸型电极11，在每一电极焊盘8上都形成了一个凸型电极11。任何已知和适合的LSI芯片都可以用作上述LSI芯片7。用于本发明的LSI芯片的典型尺寸是10mm×10mm×0.5mm。上述电极焊盘8和凸型电极11都设置在LSI芯片7的边缘部分上，用于将芯片上所形成的集成电路的布线与外部电路相连接。现在，凸型电极11之间的间距一般在大约0.200mm-0.120mm的范围内，将来还有可能采用更小的间距。每一个凸型电极11与芯片载体12上的多个端电极6中的一个通过设置在它们之间面上所形成的焊接层9（导电性粘结剂）实现电气连接。凸型电极11最好具有两级阶梯型的凸型形状（亦即其形状由一个凸型部分组成，其中一个部分位于另一部分之上），以便实现凸型电极11和芯片载体12上的端电极6之间的稳定互连。焊接层（导电性粘合物）9除了用导电性粘结剂构成之外，还可以由非均质性材料或焊料形成。LSI芯片7和芯片载体12之间的空隙用模塑树脂10来填充，以便实现密封。
下面将结合图3对芯片载体12进行详细的说明。本实施例的芯片载体12包括用作载体1的多层陶瓷基片，该载体1进一步包括一层内部导线。在载体1的上表面上设置了多个端电极6，用于实现LSI芯片7上的凸型电极11和内部导线之间的电气连接。在载体1的下表面上提供了多个凹入部位，用于实现电路基板（图3中未示）上的电极和内部导线之间的电气连接。每一个凹入部位的深度在大约20-100μm的范围之内，其内径大约为200μm。在每一个凹入部位中埋设了多个接触电极5中的一个，其方式应使该接触电极5和电路基板上的电极相接触。在本实施例中，上述接触电极5由载体1的下表面向下凸出大约10-20μm。然而，如果电路基板上的电极具有两级阶梯型的凸型结构，接触电极5就不需要由载体1的下表面向下凸出，对此下面将加以说明。
每一个接触电极5通过内部导线和一个相应的端电极6相连接。其结果是不需通过焊丝就可以实现LSI芯片7和电路基板（图中未示）之间的电气互连。这样，就能够获得优良的高频特性。在本实施例中，载体1中的内部导线由埋入到载体上的通路孔2中的通路3和基片内部的布线4组成。内部导线用于实现端电极6和接触电极5之间的电气连接，其中端电极6以相对小的间距安排在载体1上表面的边缘部分上，而接触电极5则以较大的间距安排在载体1的下表面上。由于LSI芯片7的电极焊盘8设置在LSI芯片的边缘部位上，因此端电极6就只能设置在载体1上表面的边缘部位上。然而，接触电极5的位置并不限于载体1下表面的边缘部位，通过利用载体1下面的整个面积来布置接触电极5，就可能以较大的间距来有效地设置接触电极。这样，就能够容易地避免在相邻接触电极5之间产生短路现象。增大接触电极5之间的间距也能够允许增大每一接触电极5的尺寸，其结果是能够在接触电极5和电路基板之间获得可靠的电气/机械互连。在本实施例中，接触电极5之间的最小容许间距为大约400μm。也可以在基片内部的布线部位上设置电路元件，例如电阻，电容等等。
LSI芯片7以如下所述的方式安装在芯片载体12上：
再参见附图1，通过球形焊接方式，在LSI芯片7的电极焊盘8上形成凸型电极11，该凸型电极由Au制成，具有两级阶梯型的凸型形状。然后，在每一个凸出电极11的端头部位上涂上导电性粘结剂9。此后，将凸型电极11置于对应于芯片载体12上的端电极6的位置上。随后，将LSI芯片7置于芯片载体12上，对导电性粘结剂进行热固化。用模塑树脂10来填充LSI芯片7和芯片载体12之间的空隙，并对模塑树脂10进行热固化。在LSI芯片7上形成的凸型电极11可以具有任何的结构，例如用电镀方式形成的Au凸块、用电镀方式形成的焊料凸块、或者焊料球形凸块等等，只要能够允许以倒装方式进行安装即可。
本发明的芯片载体12和芯片封装19的一个重要特点是用填入到载体1的凹入部位的导电性粘结剂来形成芯片载体12的接触电极5。上述导电性粘结剂可以采用例如由Ablestik公司生产的聚合导电性粘结剂。由这样的导电性粘结剂所形成的接触电极5具有如下的优点：
芯片封装19和安装该封装的电路基板之间的间距与采用诸如焊料球之类的电极时相比大大减小了。此外，这样的接触电极5能够很容易地和电路基板上的任何凸出的电极相连接。通过将电路基板上的凸出电极插入到芯片封装19上的接触电极5中，就能够相对容易的防止诸如粘结剂流动和凸出电极5短路之类的问题。另外，在电路基板的凸出电极和导电性粘结剂之间能够确保较大的接触面积，从而提供了大的结合强度，改善了可靠性。特别是当导电性粘结剂具有柔性时，即使受热冲击时，也能够避免接触电极5产生破裂。
也可以采用如附图4所示的基片来作为本发明芯片载体12的载体1，通过通路3将接触电极5直接与端电极6相连接。在附图2中显示了一个采用上述基片的芯片封装实例。在这一封装中，没有提供基片内部的布线。然而，在载体1的上表面上提供了引线（图中未示），使之由端电极6伸出，因而能够将通路孔2和通路3置于不同于端电极6的位置上。尽管如附图4所示的芯片载体的设计自由度和附图3所示的芯片载体相比是减小了，但是仍然可能采用这种方式以不同于端电极6的图形来安排接触电极5。附图2显示的芯片封装是将LSI芯片7装在芯片载体12上的情形。
下面将参照附图5A-5I对本发明的芯片载体的制造方法进行说明。
首先，如附图5A所示，在多个未经烧结的陶瓷生料板1a和1b上分别用激光束或模冲法形成通路孔2a和2b。在形成如附图3所示的芯片载体时，根据所采用的生料板1a或1b，通路孔2a和2b可以有不同的布局图形;然而，在附图5A-5I中，为了简明起见，通路孔2a和2b在所有的生料板1a和1b上都具有相同的布局图形。
诸如由日本电气玻璃公司生产的陶瓷生料板（以MLS-100作为其主要原料）可以用作生料板1a和1b。将厚度大约为200μm的5-10块这样的生料板层迭在一起来形成载体1。未经烧结的生料板1a和1b（其厚度：200μM）经过烧结之后将具有大约为150μM的厚度，因此整个载体1的厚度在0.7mm-1.5mm的范围之内。载体1最好具有较小的厚度，以便减小芯片载体和芯片封装的厚度。
其次，如附图5B所示，通过印制法，在生料板1a的通路孔2a中埋入导电性材料，形成通路3a。此后，如附图5F所示，通过印制形成内部基片之间的布线4a。这样，就形成了内部导线的构件。
将其通路孔2b中没有形成通路的生料板1b置于多层生料板1a上，以形成一个多层结构。此后，在加热的同时对该多层结构加压。此后如附图5G所示，对层叠在一起的生料板1a和1b进行烧结，形成载体1，其下表面上具有多个凹部2b。上述凹部2b由载体1最下层的生料板1b上的通路孔2b（未填充的）构成。上述载体1的制造步骤可以用其他已知的方法来代替。
在进行烧结之后，如附图5H所示，在载体1的上表面上形成端电极6。其次，如附图5I所示，通过在一个掩模14上进行印制，在载体1的面对电路基板一面上的多个凹入部位2b中埋入导电性粘结剂。在上述印制过程中采用刮板13。这样，就在载体1的凹入部位2b中埋入了导电性粘接剂，形成接触电极5。上述导电性粘结剂可以具有柔软性。导电性粘结剂中包含导电性颗粒，导电性颗粒最好由AgPd、Au、Ag、Cu或复合合金粉末构成。
填充凹入部位2b中的接触电极5可以由载体1的表面向外凸出，也可以不凸出。当接触电极5不凸出于载体1的表面时，电路基板上所形成的电极形状应该使之能够插入到载体1的凹入部位2b之中。
在用上述方法来形成载体1时，每一个接触电极5的长度，亦即在垂直于载体1下表面方向上的尺寸，由构成载体1最下层的生料板1b的厚度来确定。如果生料板1b经过烧结之后的厚度为150μm，那么每一个接触电极5的长度就在150-170μm的范围之内。如果增加每一个接触电极5的长度，接触电极所具有的相对较大的电阻值就会变得不可忽视。因此，接触电极5的长度最好等于或小于200μm。
当内部导线用非贵金属制成时，在生料板1b的通路孔2b中填充导电性粘结剂之前，可以在通路孔2b的内表面镀上一层不会氧化的导体，例如金。通过这样的镀层，就增大了导电性粘结剂和生料板1b之间的电气接触面积，从而减小了接触电极5和内部导线之间的电阻。
形成接触电极5的步骤可以在将LSI芯片安装在载体1上之前进行，也可以在其后进行。在某些情况下，可以将装有LSI芯片、但是不具有接触电极5的芯片封装出售给用户。在这样的情况下，至少可以在将芯片封装安装在电路基板上之前将接触电极5埋入到载体1下表面上的凹入部位2b中。
除了玻璃陶瓷之外，用于制造载体1的材料可以是具有良好散热性能的氧化铝。
在制造如附图4所示的芯片载体时，省略了形成内部基片的布线4的步骤，因而只进行如附图5A-5E的步骤。附图5C-5E分别对应于附图5G-5I。
下面，将结合附图6对适合于芯片载体12和芯片封装19的电路基板17上的电极结构进行说明。电路基板17具有两级阶梯型的凸型形状的端电极6，这样的端电极适合于用于载体1上的接触电极5基本上不凸出于载体1下表面的情况。
如附图6所示的电路基板17包括在其上表面上形成的电极焊盘16，并进一步包括在电极焊盘16上形成的具有两级阶梯型的凸型形状的端电极18。每一个端电极18的下阶梯部分在电路基板17上形成，而上阶梯则在下阶梯上形成。从电路基板的上方来看，端电极18的形状即可以是圆形的，也可以是方形的。上阶梯部分在平行于电路基板方向上的截面面积最好小于下阶梯部分在同一方向上的截面面积。端电极18可以由能够进行电镀的金属，例如Au、Cu、Ag，以及焊料制成。电极焊盘16可以用任何能够电镀的材料来形成。电路基板17可以具有如附图6所示的通路孔22、通路23、和基片内部的布线24。
下面将参照附图7A-7D来说明在电路基板上形成具有两级阶梯型形状的凸型电极18的方法。
首先，如附图7A所示，通过光刻方法在设置了电极焊盘16的电路基片17上形成一层保持膜A，保护膜A在上述电极焊盘16的位置上形成了开口（内径大约为250μm），芯片载体12上的接触电极5将与这些电极焊盘16相连接。
其次，如附图7B所示，在保护膜A的上述开口中设端电极8的下阶梯部分18a（其厚度大约为几十μm）。这样，就在电路基板17的未被保护膜A覆盖的区域上有选择性地形成了端电极18的下阶梯部分18a。下阶梯部分18a的形状和大小取决于保持护A上的开口的形状和大小，其分布图形由保护膜A上的开口的分布图形来确定。
此后，如附图7C所示，通过光刻方法在电路基板17上形成保护膜B。保护膜B在每一个端电极18的下阶梯部分18a的中心部位附近具有开口（其内径大约为100μm）。保护膜B上的上述开口小于保护膜A上的开口。此后，如附图7D所示，通过电镀方式来形成端电极18的上阶梯部分18b（其高度大约为几十μm）。
最后，通过溶解或打磨方法除去保护膜A和B。此后，如必要，可以进行清洗处理。这样，就在电路基板17的电极焊盘16上形成了具有两级阶梯型凸出形状的端电极18。
本发明对电镀材料没有任何特殊限制，任何可以电镀的材料，例如Au、Cu、Ag，以及焊料均可以用作电镀材料。
下面将结合附图8说明将本发明的芯片封装安装在上述电路基板上的方法。
在采用导电性粘结剂来形成芯片封装19上的接触电极5之后，将接触电极5的位置对准电路基板17上的相应端电极18的位置。所采用的电路基片17上具有通路孔和基片内部的布线。
此后，将端电极18插入到芯片封装19的凹入部位之中。在芯片封装19的凹入部位中已经预先填入了接触电极5。此后，在50-150℃的温度下对构成接触电极5的导电性粘结剂进行固化。这样，接触电极5就以电气和机械方式与端电极18相连接，并从而将芯片封装19安装在电路基板17上。以这种方式获得的安装了芯片载体的复合体具有如下的优点：在接触电极5和电路基板17上的端电极之间获得了牢固的连接，即使电路基片17的热膨胀系数不同于载体1的膨胀系数，载体1也不大可能产生裂缝。在导电性粘结剂具有柔性的情况下，接触电极5具有能够抵抗热冲击的优良可靠性。此外，减小了载体1和电路基板17之间的距离（亦即间距），从而能够减小安装了芯片封装的复合体的整体厚度。
附图9显示了安装了芯片封装19的复合体，其中是将芯片封装19安装在不具有凸出端电极18的电路基板上。在这一实施例中，接触电极5直接粘结在电路基板17的电极焊接盘16上。
如上所述，根据本发明的实施例，LSI芯片7是以倒装方式安装在芯片载体12上，因此芯片封装19占据较小的面积，并具有较薄的厚度。此外，芯片封装19内部的布线仅仅延伸相对短的距离，从而能够获得优良的频率特性。
此外，芯片载体12上的接触电极5是由填入到载体1下表面上的凹入部位中的导电性粘结剂来形成的。通过将电路基板17的电极焊盘16上所形成的具有两级阶梯型凸型形状的端电极18插入到接触电极5之中，可以在端电极18和接触电极5之间获得牢固的连接。安装了芯片封装19的复合体的整体厚度也能够被减小。
这样，本发明提供了一种占据较小面积的芯片封装（包括安装在芯片载体上的LSI芯片）。此外，在将芯片封装安装在电路基板上之后，从电路基板出发所测得的芯片封装的厚度也很小。因此，本发明的芯片封装适合于进行高密度安装。
由于芯片封装的接触电极是由导电性粘结剂制成的，并最好采用具有柔性的导电性粘结剂，因此能够通过将电路基板的端电极上所形成的具有两级凸型形状的电极插入到接触电极之中，将芯片封装安装在电路基片上，同时能够保持在进行上述安装之后所获得的电路部件的厚度。
此外，在将电路基板上所形成的具有两级阶梯型凸型形状的端电极插入到芯片封装的接触电极之中时，端电极的上述凸型形状能够防止粘结剂的蠕变和相邻端电极之间的短路现象。另外，这样的端电极能够以高的几率并以较大的接触面积和导电性粘结剂相接触，从而增加了焊接的可靠性。
本技术领域里的普通技术人员在不脱离本发明的范围和实质性内容的前提下还可以对本发明作出种种改进。因此，下面的权利要求不应局限于说明书的内容，而是应该获得更为广泛的解释。

Claims (25)

1、一种芯片载体，包括：
具有上表面、下表面和内部导线的载体；
在载体的上表面上所形成的多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接；
在载体的下表面上形成了多个凹入部分，用于使一个电路基板上的多个电极与上述内部导线之间实现电气连接，这些凹入部分与内部导线电气连接。
2、如权利要求1所述的芯片载体，其特征在于进一步包括与电路基板上的电极相连接的多个接触电极，这些接触电极埋设在相应的多个凹入部分之中，接触电极由导电性粘结剂构成。
3、如权利要求1所述的芯片载体，其特征在于所述多个接触电极由载体的下表面向外凸出。
4、如权利要求1所述的芯片载体，其特征在于：
载体包括多个通路孔;
内部导线的至少一部分由设置在上述多个通路孔中导电性材料构成;以及
载体上的至少某些凹入部分由上述多个通路孔构成。
5、如权利要求1所述的芯片载体，其特征在于所述载体是由多层相互层叠在一起的绝缘层构成，载体具有多个通路孔，用于将载体的上下表面连接在一起，所述的内部导线由设置在多个通路孔中的导电性粘结剂材料和设置在所述多层绝缘层中的至少一层上的导电层组成。
6、如权利要求2所述的芯片载体，其特征在于所述导电性粘结剂具有柔性。
7、如权利要求1所述的芯片载体，其特征在于所述内部导线由一种从由Cu、Ag和AgPd中选出的材料制成。
8、一种芯片封装，由芯片载体和一个以倒装方式安装在芯片载体上的LSI芯片组成，其中芯片载体包括：
具有上表面、下表面和内部导线的载体;
在载体的上表面上所形成的多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接;以及
多个凹入部分，用于使一个电路基板上的多个电极与上述内部导线实现电气连接，这些凹入部分设置在载体的下表面上;
其中LSI芯片包括：
设置在LSI芯片上的电极焊盘以及在电极焊盘上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的焊结层实现电气连接，LSI芯片和芯片载体之间的空隙由模塑树脂来密封。
9、如权利要求8所述的芯片封装，其特征在于进一步包括与电路基板上的电极相连接的多个接触电极，这些接触电极埋设在相应的凹入部位中，接触电极由导电性粘结剂构成。
10、如权利要求8所述的芯片封装，其特征在于LSI芯片的凸出电极具有两极阶梯型的凸型状态。
11、如权利要求8所述的芯片封装，其特征在于所述导电性粘结剂具有柔性。
12、如权利要求8所述的芯片封装，其特征在于所述焊结层由一种从导电性粘结剂、非匀质性导电性材料和焊料中选择出的材料构成。
13、一种芯片封装，由芯片载体和一个以倒装方式安装在芯片载体上LSI芯片组成，其中芯片载体包括：
具有上表面、下表面和内部导体的载体;
在载体的上表面上形成的多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接;
多个接触电极，用于使电路基板上的多个电极与内部导线实现电气连接，接触电极设置在载体的下表面上，由导电性粘结剂构成，并埋设在载体下表面上所形成的多个凹入部分中;
其中LSI芯片包括：
设置在LSI芯片上的电极焊盘以及在电极焊盘上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的粘结层实现电气连接，LSI芯片和芯片载体之间的空隙用模塑树脂来密封。
14、如权利要求13所述的芯片封装，其特征在于所述LSI芯片上的凸型电极具有两级阶梯型的凸型形状。
15、如权利要求13所述的芯片封装，其特征在于所述导电性粘结剂具有柔性。
16、如权利要求13所述的芯片封装，其特征在于所述焊结层由一种从导电性粘结剂、非匀质性导电材料和焊料中选择出的材料构成。
17、一种制造芯片载体的方法，包括如下步骤：
在多层未经烧结的生料板上形成通路孔;
在上述多层生料板的一组通路孔中埋设内部导线的一部分，并通过印制方法在上述多层生料板的一组上形成内部导线;
通过将上述多层生料板中没有将其内部导线体的一部分埋设在通路孔之中的生料板层叠在一组将其内部导线的一部分埋设在通路孔之中的生料板上，形成一个多层结构，并对该多层结构进行加压处理;
对上述多层生料板进行烧结，以便形成载体，在载体的下表面上形成多个凹入部分。
18、如权利要求17所述的芯片载体制造方法，其特征在于该方法进一步包括通过在载体的多个凹入部分中埋设导电性粘结剂来形成多个接触电极。
19、如权利要求18所述的芯片载体制造方法，其特征在于所述导电性粘结剂具有柔性。
20、一种用于其上安装了芯片封装的电路基板的端电极，该端电极在电路基片上形成，并包括：
一个在电路基板上形成的下阶梯部分;以及
一个在上述下阶梯部分上形成的上阶梯部分。
21、如权利要求20所述用于电路基板的端电极，其特征在于上阶梯部分在平行于电路基板方向上的截面面积小于下阶梯部分在平行于电路基片方向上的截面面积。
22、一种用于在电路基板上制作端电极的方法，包括如下步骤：
通过第一光刻步骤在电路基板上形成第一保护膜，该第一保护膜在对应于电路基板上的电极焊盘的位置上具有第一开口;
在上述第一保护膜上的第一开口中形成端电极的下阶梯部分;
通过第二光刻步骤在电路基板上形成第二保护膜，该第二保护膜在对应于端电极的下阶梯部分的位置上具有第二开口，该第二开口小于上述第一开口;
在第二保护膜的第二开口中形成端电极的上阶梯部分;
除去上述第一和第二保护膜，从而形成端电极。
23、一种安装了芯片封装的复合体，包括安装在电路基板上的芯片封装，而芯片封装包括芯片载体和以倒装方式安装在芯片载体上的LSI芯片，
其中芯片载体包括：
具有上表面、下表面和内部导线的载体;
在载体的上表面上所形成的多个端电极，这些端电极使LSI芯片和内部导线之间实现电气连接;以及
多个接触电极，用于使电路基板上的多个电极与内部导线实现电气连接，接触电极设置在载体的下表面上，由导电性粘结剂构成，并埋设在载体下表面上所形成的多个凹入部分中;
其中LSI芯片包括：
设置在LSI芯片上的电极焊盘以及在电极焊盘上形成的凸型电极，该凸型电极和芯片载体上的相应端电极通过设置在它们之间的焊结层实现电气连接，LSI芯片和芯片载体之间的空隙用模塑树脂来密封;以及
其中电路基板的端电极与芯片载体上的相应接触电极相连接。
24、如权利要求23所述的安装了芯片封装的复合体，电路基板上的端电极朝着载体上的相应凹入部分向外凸出。
25、如权利要求24所述的安装了芯片封装的复合体，其特征在于电路基片上的端电极具有两级阶梯型的凸型形状。
CN94112790A 1993-12-13 1994-12-13 芯片载体及其制造方法以及芯片载体的应用 Expired - Fee Related CN1048824C (zh)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP311980/1993 1993-12-13
JP31198093 1993-12-13
JP311980/93 1993-12-13
JP314966/93 1993-12-15
JP31496693 1993-12-15
JP314966/1993 1993-12-15
JP320126/1993 1993-12-20
JP320126/93 1993-12-20
JP32012693 1993-12-20
JP320117/93 1993-12-20
JP320117/1993 1993-12-20
JP32011793 1993-12-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNB981225861A Division CN1159956C (zh) 1993-12-13 1994-12-13 装有芯片封装的电路基板的端电极及其制造方法

Publications (2)

Publication Number Publication Date
CN1113607A true CN1113607A (zh) 1995-12-20
CN1048824C CN1048824C (zh) 2000-01-26

Family

ID=27480058

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB981225861A Expired - Fee Related CN1159956C (zh) 1993-12-13 1994-12-13 装有芯片封装的电路基板的端电极及其制造方法
CN94112790A Expired - Fee Related CN1048824C (zh) 1993-12-13 1994-12-13 芯片载体及其制造方法以及芯片载体的应用

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CNB981225861A Expired - Fee Related CN1159956C (zh) 1993-12-13 1994-12-13 装有芯片封装的电路基板的端电极及其制造方法

Country Status (4)

Country Link
US (2) US5640051A (zh)
EP (1) EP0657932B1 (zh)
CN (2) CN1159956C (zh)
DE (1) DE69428181T2 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100405591C (zh) * 2004-03-10 2008-07-23 株式会社东芝 半导体器件及其制造方法
CN102083281A (zh) * 2010-10-27 2011-06-01 北京遥测技术研究所 一种提升高频qfn器件焊装可靠性的方法
CN104752380A (zh) * 2013-12-31 2015-07-01 晟碟信息科技（上海）有限公司 半导体装置
CN107438894A (zh) * 2015-03-10 2017-12-05 索尼半导体解决方案公司 电子部件、电子部件安装基板和用于安装电子部件的方法
CN110849511A (zh) * 2019-11-13 2020-02-28 苏州市东科电子有限公司 一种厚膜电容压力传感器引线针的安装方法
CN111683471A (zh) * 2019-03-11 2020-09-18 株式会社村田制作所 多层布线基板

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
JP3330468B2 (ja) * 1995-06-30 2002-09-30 富士通株式会社 配線基板及び半導体装置
JP3311215B2 (ja) * 1995-09-28 2002-08-05 株式会社東芝 半導体装置
CN1094717C (zh) 1995-11-16 2002-11-20 松下电器产业株式会社 印刷电路板的安装体
KR0182073B1 (ko) * 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP2951882B2 (ja) * 1996-03-06 1999-09-20 松下電器産業株式会社 半導体装置の製造方法及びこれを用いて製造した半導体装置
JP3409957B2 (ja) * 1996-03-06 2003-05-26 松下電器産業株式会社 半導体ユニット及びその形成方法
US5759737A (en) * 1996-09-06 1998-06-02 International Business Machines Corporation Method of making a component carrier
EP0883173B1 (en) * 1996-09-12 2007-09-12 Ibiden Co., Ltd. Circuit board for mounting electronic parts
JPH10135613A (ja) * 1996-10-28 1998-05-22 Ngk Spark Plug Co Ltd 配線基板
DE19646476C2 (de) * 1996-11-11 2002-03-14 Fraunhofer Ges Forschung Verbindungsstruktur
JPH10163386A (ja) * 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
JP3065549B2 (ja) * 1997-01-09 2000-07-17 富士通株式会社 半導体チップ部品の実装方法
US5770477A (en) * 1997-02-10 1998-06-23 Delco Electronics Corporation Flip chip-on-flip chip multi-chip module
US5786238A (en) * 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates
US5889332A (en) * 1997-02-21 1999-03-30 Hewlett-Packard Company Area matched package
JP3578581B2 (ja) * 1997-02-28 2004-10-20 富士通株式会社 ベアチップの実装構造および実装方法およびそれに用いるインターポーザ
WO1998048449A2 (en) * 1997-04-21 1998-10-29 Flip Chip Technologies, L.L.C. Flip chip and chip scale package
US6175161B1 (en) * 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
JPH1168026A (ja) * 1997-06-13 1999-03-09 Ricoh Co Ltd 配線用補助パッケージおよび印刷回路配線板構造
US5926731A (en) * 1997-07-02 1999-07-20 Delco Electronics Corp. Method for controlling solder bump shape and stand-off height
JP3000975B2 (ja) * 1997-10-20 2000-01-17 富士通株式会社 半導体素子の実装構造
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
US6432744B1 (en) * 1997-11-20 2002-08-13 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
EP0962978A1 (en) * 1998-06-04 1999-12-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same
US6084296A (en) * 1998-07-09 2000-07-04 Satcon Technology Corporation Low cost high power hermetic package with electrical feed-through bushings
CN1318274A (zh) * 1998-09-17 2001-10-17 伊比登株式会社 多层叠合电路板
JP2000138313A (ja) 1998-10-30 2000-05-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6069407A (en) 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US6246587B1 (en) 1998-12-03 2001-06-12 Intermedics Inc. Surface mounted device with grooves on a termination lead and methods of assembly
US6218729B1 (en) * 1999-03-11 2001-04-17 Atmel Corporation Apparatus and method for an integrated circuit having high Q reactive components
JP3403677B2 (ja) * 1999-09-06 2003-05-06 マイクロ・テック株式会社 半田ボール形成方法
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
US6642613B1 (en) * 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
JP3549017B2 (ja) * 2000-07-21 2004-08-04 松下電器産業株式会社 フリップチップ実装方法
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
US7138583B2 (en) * 2002-05-08 2006-11-21 Sandisk Corporation Method and apparatus for maintaining a separation between contacts
US6897566B2 (en) * 2002-06-24 2005-05-24 Ultra Tera Corporation Encapsulated semiconductor package free of chip carrier
JP2004039867A (ja) * 2002-07-03 2004-02-05 Sony Corp 多層配線回路モジュール及びその製造方法
US7505862B2 (en) * 2003-03-07 2009-03-17 Salmon Technologies, Llc Apparatus and method for testing electronic systems
US7205649B2 (en) * 2003-06-30 2007-04-17 Intel Corporation Ball grid array copper balancing
US7408258B2 (en) * 2003-08-20 2008-08-05 Salmon Technologies, Llc Interconnection circuit and electronic module utilizing same
US20050095835A1 (en) * 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7566960B1 (en) 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US7005742B2 (en) * 2004-02-05 2006-02-28 Texas Instruments Incorporated Socket grid array
US20050184376A1 (en) * 2004-02-19 2005-08-25 Salmon Peter C. System in package
US20050205986A1 (en) * 2004-03-18 2005-09-22 Ikuroh Ichitsubo Module with integrated active substrate and passive substrate
US20050255722A1 (en) * 2004-05-07 2005-11-17 Salmon Peter C Micro blade assembly
JP4627632B2 (ja) * 2004-05-17 2011-02-09 Ｏｋｉセミコンダクタ株式会社 半導体装置
US7340957B2 (en) 2004-07-29 2008-03-11 Los Alamos National Security, Llc Ultrasonic analyte concentration and application in flow cytometry
US7427809B2 (en) * 2004-12-16 2008-09-23 Salmon Technologies, Llc Repairable three-dimensional semiconductor subsystem
US20070007983A1 (en) * 2005-01-06 2007-01-11 Salmon Peter C Semiconductor wafer tester
US20070023889A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Copper substrate with feedthroughs and interconnection circuits
US7586747B2 (en) * 2005-08-01 2009-09-08 Salmon Technologies, Llc. Scalable subsystem architecture having integrated cooling channels
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US20070023923A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Flip chip interface including a mixed array of heat bumps and signal bumps
JP4404139B2 (ja) * 2005-10-26 2010-01-27 株式会社村田製作所 積層型基板、電子装置および積層型基板の製造方法
JP2008166373A (ja) * 2006-12-27 2008-07-17 Nec Electronics Corp 半導体装置およびその製造方法
TWI357647B (en) * 2007-02-01 2012-02-01 Siliconware Precision Industries Co Ltd Semiconductor substrate structure
TWI356480B (en) * 2007-05-07 2012-01-11 Siliconware Precision Industries Co Ltd Semiconductor package substrate
US7911066B2 (en) * 2007-08-29 2011-03-22 Agilent Technologies, Inc. Through-chip via interconnects for stacked integrated circuit structures
US8266951B2 (en) 2007-12-19 2012-09-18 Los Alamos National Security, Llc Particle analysis in an acoustic cytometer
US7741151B2 (en) * 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
JP2011187681A (ja) * 2010-03-09 2011-09-22 Toshiba Corp 半導体装置の製造方法および半導体装置
US8975117B2 (en) * 2012-02-08 2015-03-10 Infineon Technologies Ag Semiconductor device using diffusion soldering
US9171790B2 (en) * 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR102037866B1 (ko) * 2013-02-05 2019-10-29 삼성전자주식회사 전자장치
KR102059402B1 (ko) * 2013-04-15 2019-12-26 삼성전자주식회사 전자소자 패키지 및 이에 사용되는 패키지 기판
KR20200037246A (ko) * 2017-08-14 2020-04-08 소니 주식회사 전자 부품 모듈, 그 제조방법, 내시경 장치 및 이동체 카메라
US10461078B2 (en) 2018-02-26 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Creating devices with multiple threshold voltage by cut-metal-gate process
DE102019127915A1 (de) 2019-10-16 2021-04-22 Tdk Electronics Ag Sensorelement und Verfahren zur Herstellung eines Sensorelements
DE102019127924B3 (de) * 2019-10-16 2021-01-21 Tdk Electronics Ag Bauelement und Verfahren zur Herstellung eines Bauelements

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810841A (ja) * 1981-07-13 1983-01-21 Mitsubishi Electric Corp 樹脂封止形半導体装置
JPS5921047A (ja) * 1982-07-27 1984-02-02 Fuji Xerox Co Ltd リ−ドレスチツプキヤリア
JPS59158539A (ja) * 1983-02-28 1984-09-08 Sharp Corp 樹脂封止型半導体装置
JPS6124253A (ja) * 1984-07-13 1986-02-01 Hitachi Ltd 半導体パツケ−ジ構造
US4714570A (en) * 1984-07-17 1987-12-22 Matsushita Electric Industrial Co., Ltd. Conductor paste and method of manufacturing a multilayered ceramic body using the paste
JPS61208853A (ja) * 1985-03-14 1986-09-17 Toshiba Corp Ｉｃパツケ−ジ
JPS62136865A (ja) * 1985-12-11 1987-06-19 Hitachi Ltd モジユ−ル実装構造
JPS62266857A (ja) * 1986-05-15 1987-11-19 Oki Electric Ind Co Ltd 半導体装置
JPH07118340B2 (ja) * 1986-10-28 1995-12-18 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション コネクタ・アセンブリ
JPH0728128B2 (ja) * 1988-03-11 1995-03-29 松下電器産業株式会社 セラミック多層配線基板とその製造方法
JPH02310941A (ja) * 1989-05-26 1990-12-26 Mitsui Mining & Smelting Co Ltd バンプを有するプリント回路基板およびバンプの形成方法
FR2650471B1 (fr) * 1989-07-27 1991-10-11 Bull Sa Procede de formation de piliers du reseau multicouche d'une carte de connexion d'au moins un circuit integre de haute densite
JP2978511B2 (ja) * 1989-09-20 1999-11-15 株式会社日立製作所 集積回路素子実装構造体
JPH045844A (ja) * 1990-04-23 1992-01-09 Nippon Mektron Ltd Ｉｃ搭載用多層回路基板及びその製造法
JPH0430544A (ja) * 1990-05-28 1992-02-03 Hitachi Ltd 半導体集積回路装置
JP3210321B2 (ja) * 1990-05-31 2001-09-17 株式会社ガスター 自動風呂装置における浴槽水位検出方法
JP2881270B2 (ja) * 1990-08-28 1999-04-12 日本特殊陶業株式会社 多層配線基板の製造方法
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
DE69229661T2 (de) * 1991-04-26 1999-12-30 Citizen Watch Co., Ltd. Verfahren zur Herstellung einer Anschlusstruktur für eine Halbleiteranordnung
KR920022482A (ko) * 1991-05-09 1992-12-19 가나이 쯔도무 전자부품 탑재모듈
CA2071662A1 (en) * 1991-06-26 1992-12-27 Jon J. Gulick Integrated socket-type package for flip-chip semiconductor devices and circuits
JP2966972B2 (ja) * 1991-07-05 1999-10-25 株式会社日立製作所 半導体チップキャリアとそれを実装したモジュール及びそれを組み込んだ電子機器
US5316788A (en) * 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5239448A (en) * 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5315239A (en) * 1991-12-16 1994-05-24 Hughes Aircraft Company Circuit module connections
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
JPH05226487A (ja) * 1992-02-14 1993-09-03 Nec Corp 半導体装置
JPH05243330A (ja) * 1992-02-28 1993-09-21 Nippondenso Co Ltd 多層配線基板とフリップチップｉｃの接続構造
US5213676A (en) * 1992-05-11 1993-05-25 Eastman Kodak Company Method of generating a substrate electrode for flip chip and other applications
JPH0685103A (ja) * 1992-08-31 1994-03-25 Kyocera Corp 回路基板及び回路基板の電極形成方法
US5404044A (en) * 1992-09-29 1995-04-04 International Business Machines Corporation Parallel process interposer (PPI)
EP0591862B1 (en) * 1992-10-02 1999-05-26 Matsushita Electric Industrial Co., Ltd. A semiconductor device, an image sensor device, and methods for producing the same
JP3370704B2 (ja) * 1992-10-12 2003-01-27 株式会社日立製作所 通信制御方法
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5397917A (en) * 1993-04-26 1995-03-14 Motorola, Inc. Semiconductor package capable of spreading heat

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100405591C (zh) * 2004-03-10 2008-07-23 株式会社东芝 半导体器件及其制造方法
CN102083281A (zh) * 2010-10-27 2011-06-01 北京遥测技术研究所 一种提升高频qfn器件焊装可靠性的方法
CN104752380A (zh) * 2013-12-31 2015-07-01 晟碟信息科技（上海）有限公司 半导体装置
CN104752380B (zh) * 2013-12-31 2018-10-09 晟碟信息科技（上海）有限公司 半导体装置
CN107438894A (zh) * 2015-03-10 2017-12-05 索尼半导体解决方案公司 电子部件、电子部件安装基板和用于安装电子部件的方法
CN107438894B (zh) * 2015-03-10 2021-03-09 索尼半导体解决方案公司 电子部件、电子部件安装基板和用于安装电子部件的方法
CN111683471A (zh) * 2019-03-11 2020-09-18 株式会社村田制作所 多层布线基板
CN111683471B (zh) * 2019-03-11 2023-11-21 株式会社村田制作所 多层布线基板
CN110849511A (zh) * 2019-11-13 2020-02-28 苏州市东科电子有限公司 一种厚膜电容压力传感器引线针的安装方法

Also Published As

Publication number Publication date
US5640051A (en) 1997-06-17
EP0657932B1 (en) 2001-09-05
DE69428181T2 (de) 2002-06-13
US5628919A (en) 1997-05-13
CN1221309A (zh) 1999-06-30
EP0657932A3 (en) 1996-02-28
DE69428181D1 (de) 2001-10-11
CN1159956C (zh) 2004-07-28
EP0657932A2 (en) 1995-06-14
CN1048824C (zh) 2000-01-26

Similar Documents

Publication Publication Date Title
CN1159956C (zh) 装有芯片封装的电路基板的端电极及其制造方法
CN1266764C (zh) 半导体器件及其制造方法
US6469260B2 (en) Wiring boards, semiconductor devices and their production processes
US7488897B2 (en) Hybrid multilayer substrate and method for manufacturing the same
US8841772B2 (en) Semiconductor device and method of manufacturing the same
KR970000214B1 (ko) 반도체 장치 및 그 제조방법
JP2819284B2 (ja) 半導体パッケージ用基板およびその製造方法と その基板を利用した積層型半導体パッケージ
JP5123664B2 (ja) 半導体装置およびその製造方法
US5796163A (en) Solder ball joint
US20120021541A1 (en) Light emitting device and method of fabricating the same
JPH10504137A (ja) 一体的にバンプされた電子パッケージコンポーネント
JPH07169872A (ja) 半導体装置及びその製造方法
US20040135243A1 (en) Semiconductor device, its manufacturing method and electronic device
CN1577813A (zh) 电路模块及其制造方法
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
JP2001156212A (ja) 樹脂封止型半導体装置及びその製造方法
CN1362733A (zh) 半导体装置及其制造方法、电路板以及电子设备
CN1392601A (zh) 电路装置及其制造方法
US10667419B2 (en) Manufacturing method of an electronic component module
CN1193417C (zh) 电路装置的制造方法
CN1282242C (zh) 芯片比例封装及其制造方法
CN110139476A (zh) 在封装上的pcb模块
JP3320932B2 (ja) チップパッケージ実装体、及びチップパッケージが実装される回路基板、並びに回路基板の形成方法
KR100533763B1 (ko) 반도체패키지
KR19990049144A (ko) 칩 사이즈 반도체 패키지 및 그의 제조 방법

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee