CN1392601A - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN1392601A
CN1392601A CN02123154A CN02123154A CN1392601A CN 1392601 A CN1392601 A CN 1392601A CN 02123154 A CN02123154 A CN 02123154A CN 02123154 A CN02123154 A CN 02123154A CN 1392601 A CN1392601 A CN 1392601A
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China
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conducting film
wiring layer
conductive wiring
manufacture method
layer
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CN02123154A
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CN1191619C (zh
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五十岚优助
坂本则明
小林义幸
中村岳史
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

目前将具有导电图案的挠性板作为支承基板采用，在其上安装半导体元件，开发将其整体模装的半导体装置。这时会产生以下问题，不能形成多层配线结构、和在制造工序的绝缘树脂板的弯曲显著。本发明采用以绝缘树脂2粘合第一导电膜3和第二导电膜4得到的绝缘树脂板，以第一导电膜3形成第一导电配线层5，以第二导电膜4形成第二导电配线层6，二者以多层配线装置12连接。半导体元件7固定在覆盖第一导电配线层5的外敷层树脂8上，这样，以第一导电配线层5和第二导电配线层6实现多层配线结构。另外由于有厚厚地形成的第二导电膜4，所以可防止热膨胀系数的不同产生的弯曲。

Description

电路装置及其制造方法
技术领域
本发明涉及一种电路装置及其制造方法，特别是涉及一种以采用2张导电膜的薄型，也能实现多层配线的电路装置及其制造方法。
背景技术
近年来，IC部件不断向在移动设备及小型、高密度安装设备中采用而迈进，目前的IC部件与其实际安装概念将有很大的变化。例如特开2000-133678号公报所述。这是一种涉及半导体装置的技术，该半导体装置作为绝缘树脂板的一例，采用了挠性板的聚酰亚胺树脂板。
图12-图14中，将挠性板50作为插件基板采用，另外，各图之上面的图为平面图，下面的图为A-A线的断面图。
首先，在图12表示的挠性板50之上，通过粘接剂粘贴准备铜箔图案51。该铜箔图案51虽因实际安装的半导体元件为晶体管、IC其图案不同，但一般的来说，形成有焊盘51A、隔离岛51B。另外符号52，是用于从挠性板50的背面取出电极的开口部，露出前述铜箔图案51。
然后，该挠性板50送到装片机，如图13，实际安装半导体元件53。之后，该挠性板50送到引线接合器，焊盘51A和半导体元件53的接点用金属细线54进行电联接。
最后，如图14(A)，挠性板50的表面设置密封树脂55进行密封。在此，为将焊盘51A、隔离岛51B、半导体元件53及金属细线54覆盖而进行传递模模装。
之后，如图14(B)所示，设置焊料及焊料球之类的连接装置56，通过焊料反射炉，经开口部52，形成焊盘51A、与熔融的球状焊锡56。而且在挠性板50上矩阵状形成半导体元件53，因此，如图14所示切割分离为一个一个的元件。
另外，图14(C)表示的断面图，是在挠性板50的两面，作为电极形成51A、51D。该挠性板50一般两面形成图案，由厂商提供。
发明内容
采用所述挠性板50的半导体装置，不用周知的金属框架，所以具有能够以极其小型化实现薄形组件结构的优点。但存在以下问题，实际上只是由设置在挠性板50表面的一层铜箔图案51实施配线，故不能实现多层配线。
为了实现多层配线结构，就要确保支承强度，因此，必须将挠性板50设置的很厚，使其厚度大约为200μm，与薄形化有背道而驰的问题。
而且在制造方法中，在所述的制造装置，例如，在装片机、引线接合器、传递模装置、反射炉等中，传送挠性板50，并将其安装在被称为载物台或工作台的部分。
但如果构成挠性板50基础的绝缘树脂的厚度很薄，为50μm左右，那么，在表面形成的铜箔图案51的厚度也很薄只有9-35μm，此时，如图15所示，存在弯曲传送性很差，在所述载物台或工作台的安装性恶化的缺点。这认为是由于绝缘树脂自身很薄形成的弯曲、铜箔图案51和绝缘树脂的热膨胀系数差形成的弯曲。特别是没有玻璃布纤维芯材的硬的绝缘材料，当如图15所示弯曲时，会因来自上边的加压而简单地开裂。
另外开口部52部分，模装时从上边加压，故作用使焊盘51A的周边向上弯曲的力，也常常使焊盘51A的粘接性恶化。
另外构成挠性板50的树脂材料自身没有柔软性，或者为了提高热传导性，而掺入填料时会变硬。在这种状态下用引线接合器进行接合时，接合部分常常产生裂纹。另外在传递模模装时，在模型接触的部分也常常产生裂纹。这一点在如图15所示具有弯曲时，更明显。
以前说明的挠性板50背面未形成电极，但如图14(C)所示，挠性板50背面也常形成电极51D。这时，电极51D会与所述制造装置接触，或与该制造装置的传送装置的传送面接触，所以，在电极51D的背面会产生损伤。由于在带有该损伤的状态下构成电极，通过之后的加热等，电极51D自身会产生裂纹。
另外，当挠性板50的背面设置有电极51D时，在传递模模装时，就不能与载物台面接触。这时，如果如上所述，挠性板50以硬材料构成，那么电极51D构成支点，由于电极51D的周围被向下方加压，所以会在挠性板50产生裂纹。
本发明是鉴于所述课题而开发的，第一，在结构上，利用以下电路装置来解决，该电路装置包括：第一导电膜；第二导电膜；将所述第一导电膜和所述第二导电膜粘接为板状的绝缘树脂；蚀刻第一导电膜形成的第一导电配线层；蚀刻第二导电膜形成的第二导电配线层；在所述第一导电配线层上电绝缘地固定的半导体元件；在所需部位贯通前述绝缘树脂，连接所述第一导电配线层和所述第二导电配线层的多层连接装置；覆盖所述第一导电配线层和所述半导体元件的密封树脂层；在所述第二导电配线层的所需部位设置的外部电极。
以极薄的绝缘树脂将第一导电膜和第二导电膜电气绝缘，同时实现物理性一体化的板，以第一导电膜形成第一导电配线层，以第二导电膜形成第二导电配线层，以多层连接装置连接第一导电配线层和第二导电配线层，实现多层配线结构。
另外，半导体元件以外敷层树脂，与第一导电配线层电气绝缘地被固定安装，所以在半导体元件下部能够自由地环绕第一导电配线层。
第二，本发明的电路装置的制造方法，包括以下工序：
预备用绝缘树脂粘接第一导电膜和第二导电膜的电路基板的工序；在所述电路基板的所需部位，在所述第一导电膜与所述绝缘树脂上形成通孔，选择性地露出所述地2导电膜的工序；在所述通孔形成多层连接装置，使所述第一导电膜和第二导电膜电气联接的工序；将所述第一导电膜蚀刻为所需的图案，形成第一导电配线层的工序；在所述第一导电配线层上电气绝缘地固定安装半导体元件的工序；以密封树脂层覆盖所述第一导电配线层及所述半导体元件的工序；将所述第二导电膜蚀刻为所需的图案，形成第二导电配线层的工序；在所述第二导电配线层的所需的部位，形成外部电极的工序。
由于以第一导电膜和第二导电膜厚厚地形成，即使绝缘树脂薄，也能维持板状电路基板的平整性。
另外，在用密封树脂层覆盖第一导电配线层及半导体元件的工序前，用第二导电膜维持机械性强度，之后用密封树脂层维持机械性强度，所以，可很容易地以第二导电膜形成第二导电配线层。其结果是，绝缘树脂不需要机械性强度，只要是能够保持电气绝缘的厚度，能够形成得很薄。
而且，由于传递模装置的下模能与第二导电膜整体面接触，所以没有局部加压，可抑制绝缘树脂的裂纹的产生。
而且第一导电膜在通孔形成多层连接装置之后，形成第一导电配线层，所以，能无掩膜地形成多层连接装置。
附图说明
图1是说明本发明电路装置的断面图；
图2是说明本发明电路装置的平面图；
图3是说明本发明电路装置制造方法的断面图；
图4是说明本发明电路装置制造方法的断面图；
图5是说明本发明电路装置制造方法的断面图；
图6是说明本发明电路装置制造方法的断面图；
图7是说明本发明电路装置制造方法的断面图；
图8是说明本发明电路装置制造方法的断面图；
图9是说明本发明电路装置制造方法的断面图；
图10是说明本发明电路装置制造方法的断面图；
图11是说明本发明其他电路装置的断面图；
图12是说明目前半导体装置制造方法的图；
图13是说明目前半导体装置制造方法的图；
图14是说明目前半导体装置制造方法的图；
图15是说明目前的挠性板的图。
具体实施方式
说明电路装置的第一实施例
如图1所示，本发明的电路装置包括：第一导电膜3；第二导电膜4；将第一导电膜3和第二导电膜4板状粘接的绝缘树脂2；蚀刻所述第一导电膜3形成的第一导电配线层5；蚀刻所述第二导电膜4形成的第二导电配线层6；在所述第一导电配线层5上电气绝缘地固定安装的半导体元件7；在所需部位贯通所述绝缘树脂2，将所述第一导电配线层5及所述第二导电配线层6连接的多层连接装置12；覆盖所述第一导电配线层5及所述半导体元件7的密封树脂层13；在所述第二导电配线层6的所需部位设置的外部电极14。
首先说明绝缘树脂板。图3整体是绝缘树脂板1，中间设置着绝缘树脂2。在该绝缘树脂2的表面形成第一导电膜3，背面形成第二导电膜4。
就是说绝缘树脂板1的表面，在实质性的全部区域形成第一导电膜3，背面也在实质性的全部区域形成第二导电膜4。另外绝缘树脂2的材料是由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料。另外，第一导电膜3及第二导电膜4最好是以铜作为主要材料，或是公知的引线框架材料，以电镀法、蒸镀法或喷镀法覆盖在绝缘树脂2，或也可以粘贴利用压延法和电镀法形成的金属箔。
另外，绝缘树脂板1以铸塑法形成也可以。以下简单地叙述其制造方法。首先，在平膜状的第一导电膜上涂敷糊状的聚酰亚胺树脂，另外在平膜状的第二导电膜上也涂敷糊状的聚酰亚胺树脂。在两者的聚酰亚胺半硬化后互相粘合就形成绝缘树脂板1。因此绝缘树脂板1不用补强用的玻璃布纤维。
本发明的特征在于，第二导电膜4比第一导电膜3厚。
第一导电膜3，形成厚度为5-35μm的程度，尽可能薄地形成精细图案。第二导电膜4厚度以70-200μm程度为好，重视具有支承强度这一点。
因此通过较厚地形成第二导电膜4，可维持绝缘树脂板1的平坦性。提高后续工序的操作性，防止绝缘树脂2产生缺陷、及诱发裂纹等。
另外可一边维持平坦性，一边使密封树脂硬化，所以部件背面也能平坦，绝缘树脂板1的背面形成的电极也能平整地配置。因此，安装基板上的电极与绝缘树脂板1背面的电极可以接触，可防止焊接不良。
绝缘树脂2最好是聚酰亚胺树脂、环氧树脂等。在涂敷糊状物形成薄片的铸塑法的情况下，其膜厚为10μm-100μm。另外，形成薄片时，市售的最小膜厚为25μm。另外，考虑热传导性，其中掺入填料也可以。作为材料可以考虑玻璃、氧化硅、氧化铝、氮化铝、碳化硅、氮化硼等。
这样，绝缘树脂2可以选择掺入所述填料的低热阻树脂、超低热阻树脂或聚酰亚胺树脂，根据形成的电路装置的性质不同分类使用。
第一导电配线层5是蚀刻第一导电膜3形成的，第一导电膜3形成厚度为5-35μm的程度，利用蚀刻，在周边形成焊盘10、和从焊盘10向中央延伸的第一导电配线层5。装载的半导体元件接点数越多越要求精细图案化。
第二导电配线层6，是蚀刻第二导电膜形成的，第二导电膜4的膜厚为70-200μm的程度，不适合细微图案，但外部电极14的形成是主要的，根据需要可形成多层配线。
半导体元件7用粘接剂固定在覆盖第一导电配线层5的外敷层树脂8上，半导体元件7和第一导电配线层5电气绝缘。其结果是，在半导体元件7之下，精细图案的第一导电配线层5能自由配线，配线的自由度大幅增加。半导体元件7的各电极接点9用接合线11连接在焊盘10，该焊盘10设置在周边，是第一导电配线层5的一部分。还有，焊盘10为能进行接合，表面实施了镀金或镀银。
多层接线装置12在所需部位贯通所述绝缘树脂2，将所述第一导电配线层5及所述第二导电配线层6连接。作为多层配线装置12具体地说适合铜的镀膜。另外，金、银、钯等的镀膜也可以。
密封树脂层13覆盖第一导电配线层5及半导体元件7。该密封树脂层13还兼有完成的电路装置的机械性支承的功能。
外部电极14设置在第二导电配线层6的所需部位。即，第二导电配线层6的大部分被外敷层树脂15覆盖，焊料形成的外部电极14设置在露出的第二导电配线层6上。
参照图2，说明具体的本发明的电路装置。首先，以实线表示的图案是第一导电配线层5，以虚线表示的图案就是第二导电配线层6。第一导电配线层5象包围半导体元件7那样，将焊盘10设置在周边。一部分配置为2段，对应具有多个接点的半导体元件7。焊盘10以接合线11与半导体元件7对应的电极接点9连接，多个精细图案的第一导电配线层5从焊盘10延伸到半导体元件7之下，以用黑点表示的多层连接装置12与第二导电配线层6连接。
如果是这种构造，即使具有200以上接点的半导体元件，也能利用第一导电配线层5的精细图案，以多层配线结构延伸到所需的第二导电配线层6，可进行从设置在第二导电配线层6的外部电极14向外部电路的连接。
说明电路装置的制造方法的第二实施例
参照图1-图10说明本发明电路装置的制造方法
本发明电路装置的制造方法包括以下工序：预备用绝缘树脂2粘接第一导电膜3和第二导电膜4的绝缘树脂板1的工序；在所述绝缘树脂板1的所需部位，在所述第一导电膜3与所述绝缘树脂2形成通孔21，选择性地露出所述第二导电膜4的背面的工序；在所述通孔21形成多层连接装置12，将第一导电膜3和第二导电膜4电连接的工序；将所述第一导电膜3蚀刻为所需的图案，形成第一导电配线层5的工序；在所述第一导电配线层5上电绝缘地固定半导体元件7的工序；以密封树脂层13覆盖所述第一导电配线层5及半导体元件7的工序；将所述第二导电膜4蚀刻为所需的图案，形成第二导电配线层6的工序；在所述第二导电配线层6的所需部位，形成外部电极14的工序。
本发明的第一工序如图3所示，预备用绝缘树脂2粘接第一导电膜3和第二导电膜4的绝缘树脂板1。
绝缘树脂板1的表面实质性地在全部区域形成第一导电膜3，背面也实质性地在全部区域形成第二导电膜4。另外绝缘树脂2的材料是由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料。另外，第一导电膜3及第二导电膜4最好是以铜作为主要材料，或是公知的引线框架材料，以电镀法、蒸镀法或喷镀法覆盖在绝缘树脂2，或也可以粘贴利用压延法和电镀法形成的金属箔。
另外，绝缘树脂板1以铸塑法形成也可以。以下简单地叙述该制造方法。首先，在平膜状的第一导电膜3上涂敷糊状的聚酰亚胺树脂，在平膜状的第二导电膜4上也涂敷糊状的聚酰亚胺树脂，然后在使两者的聚酰亚胺树脂半硬化后互相粘合就形成绝缘树脂板1。
本发明的特征在于，形成的第二导电膜4比第一导电膜3厚。
第一导电膜3形成5-35μm的厚度，可尽可能薄地形成精细图案。第二导电膜4厚度以70-200μm程度为好，重视保持支承强度这一点。
绝缘树脂2最好是聚酰亚胺树脂、环氧树脂等。在涂敷糊状物形成薄片的铸塑法的情况下，其膜厚为10μm-100μm的程度。另外，形成薄片时，市售的最小膜厚为25μm。另外，考虑热传导性，在其中掺入填料也可以。作为材料可以考虑为玻璃、氧化硅、氧化铝、氮化铝、炭化硅、氮化硼等。
这样，绝缘树脂2可以选择掺入所述填料的低热阻树脂、超低热阻树脂或聚酰亚胺树脂，根据形成的电路装置的性质不同区分使用。
本发明的第二工序在于，如图4所示，在绝缘树脂板1的所需部位，在第一导电膜3与所述绝缘树脂2形成通孔21，选择性地露出第二导电膜4。
只露出形成第一导电膜3的通孔21的部分，以光致抗蚀剂覆盖整个面。而且通过该光致抗蚀剂蚀刻第一导电膜3。第一导电膜3是以铜为主要材料的，所以腐蚀液可以采用氯化铁或氯化铜，进行化学蚀刻。通孔21的开口直径由于光刻法的图像分辨率不同而改变，在此为50-100μm的程度。另外在进行该蚀刻时，第二导电膜4以粘接性的薄片罩住以不变腐蚀液侵蚀。但第二导电膜4本身很厚，只要是蚀刻后还能维持平坦性的膜厚，那么即使稍微蚀刻也没关系。另外作为第一导电膜3可以是Al、Fe、Fe-Ni、公知的引线框材料等。
然后除去光致抗蚀剂之后，将第一导电膜3作为掩膜，利用激光除去通孔21正下方的绝缘树脂2，在通孔21的底部，使第二导电膜4的背面露出。作为激光最好采用二氧化碳激光。另外，用激光使绝缘树脂蒸发后，开口部的底部留有残渣时，用过锰酸钠或过硫酸氨等进行湿蚀刻，除去该残渣。
另外，在本工序中，第一导电膜3仅10μm那样薄时，可在以光致抗蚀剂覆盖通孔21以外部位之后，再以二氧化碳激光对第一导电膜3及绝缘树脂2一起形成通孔21。这时必须有将预定的第一导电膜3的表面进行粗糙化的黑化处理工序。
本发明的第三工序在于如图5所示，在通孔21形成多层连接装置12，将第一导电膜3与第二导电膜4电联接。
在包含通孔21的第一导电膜3整个面上形成镀膜，作为将第二导电膜4和第一导电膜3进行电连接的多层连接装置12。该镀膜以无电解电镀和电解电镀两方面形成，在此，利用无电解电镀至少在包含通孔21的第一导电膜3整个面形成大约2μm的铜。由此使第一电镀膜3与第二导电膜4电气导通，再次以第一及第二导电膜3、4作为电极进行电解电镀，电镀约20μm的铜。由此通孔21以铜填充，形成多层连接装置12。另外，如果采用商品名为埃弗拉德莱特(ェバラュ-ジラィト)的电镀液，也能选择性地只填充通孔21。另外镀膜在此采用铜，但也可以采用Au、Ag、Pd等。另外也可使用掩膜进行局部电镀。
本发明的第四工序在于，如图6及图7所示，将第一导电膜3蚀刻为所需的图案，形成第一导电配线层5。
以所需的图案的光致抗蚀剂覆盖在在第一导电膜3上，利用化学腐蚀，形成焊盘10和从焊盘10向中央延伸的第一导电配线层5。第一导电膜3是以铜作为柱材料的，所以腐蚀液可以采用氯化铁、氯化铜。
第一导电膜3形成厚度为5-35μm的程度，第一导电配线层5能形成50μm以下的精致图案。
然后，使第一导电配线层5的焊盘10露出，其它部分被外敷层树脂8覆盖。外敷层树脂8以网印附着由溶剂溶解的环氧树脂等，并使其热硬化而得到。
另外，如图7所示，在焊盘10上考虑接合性，形成Au、Ag等的镀膜22。该镀膜22以外敷层树脂8作为掩膜，以无电场电镀选择性地附着在焊盘10上，或者以第二导电膜4作为电极以电场电镀附着。
本发明的第五工序在于，如图8所示，在第一导电配线层5上电绝缘地固定半导体元件7。
半导体元件7以裸片状态由绝缘性粘接树脂25在外敷层树脂8上进行装片，半导体元件7和其下的第一导电配线层5用外敷层树脂8进行电气绝缘，所以第一导电配线层5即使在半导体元件7之下，也能自由配线，能够实现多层配线结构。
另外，半导体元件7的各电极接点9，由接合线11连接在焊盘10上，其中，焊盘10为设置在周边的第一导电配线层5的一部分。半导体元件7也可以表面向下安装。这时，在半导体元件7的各电极接点9，设置焊料球及凸起，在绝缘树脂板1的表面上与焊料球位置对应的部分设置与焊盘10同样的电极。(参照图11)
下面叙述引线接合时采用绝缘树脂板1的优点。一般采用Au线的引线接合时，要加热到200-300℃。这时，如果第二导电膜4薄，绝缘树脂板1就会弯曲，如果以该状态通过焊盘对绝缘树脂板1加压，则绝缘树脂板1有可能产生龟裂。这点当在绝缘树脂2掺入填料时，由于材料自身变硬，失去柔软性，故更明显。另外树脂比金属柔软，所以在Au和Al的接合时，加压和超声波的能量会发散。但通过使绝缘树脂2变薄而第二导电膜4自身较厚地形成可以解决这些问题。
本发明的第六工序在于，如图9所示，将第一导电配线层5及半导体元件7用密封树脂13覆盖。
将绝缘树脂板1设置在模装装置上，进行树脂模装。作为模装方法，可以为传递模、注入模、涂敷、浸渍等。但如果考虑批量生产，则传递模、注入模更适合。
本工序中，在模腔的下模，绝缘树脂板1必须以平面接触，厚的第二导电模4实施这一功能。而且从模腔取出后，一直到密封树脂层13的收缩完全结束，都由第二导电模4维持封装的平坦性。
即，本工序之前的绝缘树脂板1的机械支承的作用，由第二导电膜4承担。
本发明的第七工序在于，如图10所示，将第二导电膜4蚀刻为所需的图案，形成第二导电配线层6。
第二导电膜4以所需图案的光致抗蚀剂覆盖，以化学蚀刻形成第二导电配线层6。由于第二导电膜4厚，所以不适合精细图案化，但大部分是为了形成外部电极14，故没有问题。第二导电配线层6如图2所示，以一定的间隔排列，每个都通过多层连接装置12，与第一导电配线层5电气联接，实现多层配线结构。再者如果有必要，可以在空白部分形成由于使第一导电配线层5交叉的第二导电配线层6。
本发明的第八工序在于，如图1所示，在第二导电配线层6的所需部位形成外部电极14。
第二导电配线层15露出形成外部电极14的部分，对溶剂溶解的环氧树脂等进行网印，用外敷层树脂15覆盖大部分。然后利用焊料的反流，同时在该露出的部分形成电极14。
最后，在绝缘树脂板1上，矩阵状形成多个电路装置，所以将密封树脂层13及绝缘树脂板1切块，将其分离为一个个电路装置。
在图11表示半导体元件7表面向下安装的结构。与图1相同的结构要素赋以同一符号。在半导体元件7上设置凸出电极31，该凸出电极31与接点电极10连接。外敷层树脂8与半导体元件7的间隙以填充树脂32填充。在该结构中可以没有接合线，可以使密封树脂层13的厚度更薄。另外外部电极14也可以由凸出电极实现，该凸出电极是将第二导电膜4蚀刻，将表面以金或钯的镀膜33覆盖而形成的。
根据本发明，结构上有以下优点。
第一，由于第一导电膜形成得薄，所以，第一导电配线层可以形成精细图案化，可实现电极接点数量在100以上的半导体元件的组装。
第二，能够以外敷层树脂将半导体元件与第一导电配线层电气绝缘，所以一直到半导体元件之下都可配线，第一导电配线层的引导自由度大幅增加，实现多层配线结构。
第三，通过采用绝缘树脂板，与目前的采用玻璃环氧树脂基板和挠性板等的选插基板时相比，能以第二导电膜及密封树脂层保持机械性强度，所以可以实现极薄型的结构。
第四，作为绝缘树脂，采用低热树脂或超低热树脂，所以不仅绝缘树脂能变薄，而且能大幅降低其热阻，使半导体元件的热量迅速散热。
另外本发明的制造方法有以下优点。
第一，作为绝缘树脂板，能用第二导电膜消除弯曲，能够提高搬送性等。
第2，以二氧化碳激光形成在绝缘树脂上形成的通孔，所以之后可以直接进行多层连接装置的电镀，工序变得很简单，另外作为多层连接装置，如果采用镀铜，则与铜的第一导电膜及第二导电膜为同一材料，之后的工序变得简单。
第三，能以镀膜实现多层连接装置，所以在形成第一导电配线层之前，能以无掩膜形成多层连接装置，形成第一导电配线层时，能同时形成图案，所以多层连接装置的形成很容易。
第四，密封树脂层形成之前，以第二导电膜进行绝缘树脂板的机械性的支承，第二导电配线层形成后，用密封树脂层进行绝缘树脂板的机械性的支承。所以可不用考虑绝缘树脂的机械性的强度，实现极薄型的安装方法。
第五，无论绝缘树脂自身硬，还是另外掺入填料而变硬，由于两面以第一及第二导电膜罩住，所以在制造工序中绝缘树脂板自身的平整性高，可以防止产生裂纹。
第六，绝缘树脂板由于背面形成厚的第二导电膜，所以能作为用于芯片的接合、引线接合器、半导体元件密封的支承基板利用。而且即使绝缘树脂材料自身柔软时，也能提高引线接合时的能量传送，也可提高引线接合性。

Claims (24)

1、一种电路装置，其特征在于，包括：
第一导电膜，
第二导电膜，
将所述第一导电膜和第二导电膜粘接为板状的绝缘树脂，
蚀刻所述第一导电膜形成的第一导电配线层，
蚀刻所述第二导电膜形成的第二导电配线层，
在所述第一导电配线层上电绝缘地固定的半导体元件，
在所需部位贯通所述绝缘树脂将所述第一导电配线层和所述第二导电配线层连接的多层连接装置，
覆盖所述第一导电配线层及所述半导体元件的密封树脂层，
设置在所述第二导电配线层的所需部位的外部电极。
2、权利要求书1所述的电路装置，其特征在于，所述第二导电膜比所述第一导电膜形成得厚，并具有支承强度。
3、权利要求书1所述的电路装置，其特征在于，所述绝缘树脂以聚酰亚胺树脂或环氧树脂为主要成分。
4、权利要求书1所述的电路装置，其特征在于，所述绝缘树脂比所述第二导电膜薄。
5、权利要求书1所述的电路装置，其特征在于，所述半导体元件固定在覆盖所述第一导电配线层的外敷层树脂上。
6、权利要求书1所述的电路装置，其特征在于，所述多层连接装置是导电金属的镀膜。
7、权利要求书1所述的电路装置，其特征在于，以外敷层树脂覆盖所述第二导电配线层的大部分，将由焊料构成的外部电极，设置在从该外敷层树脂露出的所需部位。
8、一种电路装置的制造方法，其特征在于，包括以下工序，
预备以绝缘树脂粘接第一导电膜和第二导电膜形成的绝缘树脂板的工序；
在所述绝缘树脂板的所需部位，在所述第一导电膜和所述绝缘树脂形成通孔，选择性地露出所述第二导电膜背面的工序；
在所述通孔形成多层连接装置，将所述第一导电膜和第二导电膜电气连接的工序；
将所述第一导电膜蚀刻为所需的图案，形成第一导电配线层的工序；
在所述第一导电配线层上电绝缘地固定半导体元件的工序；
将所述第一导电配线层及所述半导体元件用密封树脂层覆盖的工序；
将所述第二导电膜蚀刻为所需的图案，形成第二导电配线层的工序；
在所述第二导电配线层的所需部位形成外部电极的工序。
9、权利要求书8所述的电路装置的制造方法，其特征在于，所述第一导电膜和所述第二导电膜以铜箔形成。
10、权利要求书8所述的电路装置的制造方法，其特征在于，所述第一导电膜比所述第二导电膜形成得薄，将所述第一导电配线层形成精细图案。
11、权利要求书8所述的电路装置的制造方法，其特征在于，所述第二导电膜比所述第一导电膜形成得厚，在用所述密封树脂层覆盖的工序前，以所述第二导电膜机械性地支承。
12、权利要求书8所述的电路装置的制造方法，其特征在于，在以所述密封树脂层覆盖的工序后，以所述密封树脂层机械性地支承。
13、权利要求书8所述的电路装置的制造方法，其特征在于，所述通孔在蚀刻所述第一导电膜后，将所述第一导电膜作为掩膜，激光蚀刻所述绝缘树脂而成。
14、权利要求书13所述的电路装置的制造方法，其特征在于，所述激光蚀刻采用二氧化碳激光。
15、权利要求书8所述的电路装置的制造方法，其特征在于，所述多层连接装置，以导电金属的无电场电镀及电场电镀形成于所述第一导电膜的表面上。
16、权利要求书8所述的电路装置的制造方法，其特征在于，所述第一导电配线层形成后，除保留所需部位外，以外敷层树脂覆盖。
17、权利要求书16所述的电路装置的制造方法，其特征在于，在所述第一导电配线层的所需部位形成金或银的镀层。
18、权利要求书16所述的电路装置的制造方法，其特征在于，在所述外敷层树脂上固定所述半导体元件。
19、权利要求书17所述的电路装置的制造方法，其特征在于，将所述半导体元件的电极和所述金或银的镀层以接合线连接。
20、权利要求书8所述的电路装置的制造方法，其特征在于，所述密封树脂层以传递模形成。
21、权利要求书8所述的电路装置的制造方法，其特征在于，所述第二导电配线层的大部分以外敷层树脂覆盖。
22、权利要求书8所述的电路装置的制造方法，其特征在于，所述外部电极以焊料的网印附着焊料，并加热熔融形成。
23、权利要求书8所述的电路装置的制造方法，其特征在于，所述外部电极以焊料的反流形成。
24、权利要求书8所述的电路装置的制造方法，其特征在于，所述外部电极是将所述第二导电膜蚀刻为所需的图案，其表面镀金或钯而形成的。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696613B2 (en) 2005-09-07 2010-04-13 Shinko Electric Industries Co., Ltd. Multilayered wiring substrate including wiring layers and insulating layers and method of manufacturing the same
CN1957465B (zh) * 2004-05-21 2011-04-06 日本电气株式会社 半导体器件及配线基板
CN101604675B (zh) * 2007-03-30 2011-07-27 三洋电机株式会社 基板及其制造方法、电路装置及其制造方法
CN107431017A (zh) * 2015-03-31 2017-12-01 浜松光子学株式会社 半导体装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4107952B2 (ja) * 2002-12-04 2008-06-25 三洋電機株式会社 回路装置の製造方法
JP2005026364A (ja) 2003-06-30 2005-01-27 Sanyo Electric Co Ltd 混成集積回路
JP3877717B2 (ja) * 2003-09-30 2007-02-07 三洋電機株式会社 半導体装置およびその製造方法
JP4651359B2 (ja) * 2004-10-29 2011-03-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4558539B2 (ja) * 2005-03-09 2010-10-06 日立協和エンジニアリング株式会社 電子回路用基板、電子回路、電子回路用基板の製造方法および電子回路の製造方法
JP2007004775A (ja) * 2005-05-23 2007-01-11 Toshiba Corp 半導体メモリカード
TWI283056B (en) * 2005-12-29 2007-06-21 Siliconware Precision Industries Co Ltd Circuit board and package structure thereof
JP2008091719A (ja) * 2006-10-03 2008-04-17 Shinko Electric Ind Co Ltd 半導体装置
US7863102B2 (en) * 2008-02-22 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with external interconnects within a die platform
US8604610B1 (en) * 2012-06-13 2013-12-10 Fairchild Semiconductor Corporation Flexible power module semiconductor packages
US10043707B2 (en) * 2012-10-16 2018-08-07 Qorvo Us, Inc. Additive conductor redistribution layer (ACRL)
CN104995731B (zh) * 2013-03-29 2019-11-26 三菱综合材料株式会社 功率模块
DE112014003204B4 (de) * 2013-07-11 2020-01-30 Mitsubishi Electric Corporation Leistungsmodul
DE102018200023A1 (de) * 2018-01-02 2019-07-04 Osram Gmbh Konversionsvorrichtung mit geschichteter leiterstruktur

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473512A (en) * 1993-12-16 1995-12-05 At&T Corp. Electronic device package having electronic device boonded, at a localized region thereof, to circuit board
US6384344B1 (en) * 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
CN1971899B (zh) * 1997-10-17 2010-05-12 揖斐电株式会社 封装基板
JPH11307689A (ja) * 1998-02-17 1999-11-05 Seiko Epson Corp 半導体装置、半導体装置用基板及びこれらの製造方法並びに電子機器
US6365979B1 (en) * 1998-03-06 2002-04-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
JP3169919B2 (ja) * 1998-12-21 2001-05-28 九州日本電気株式会社 ボールグリッドアレイ型半導体装置及びその製造方法
US6707152B1 (en) * 1999-04-16 2004-03-16 Micron Technology, Inc. Semiconductor device, electrical conductor system, and method of making
JP2001320171A (ja) * 2000-05-08 2001-11-16 Shinko Electric Ind Co Ltd 多層配線基板及び半導体装置
JP2001339043A (ja) * 2000-05-30 2001-12-07 Mitsubishi Electric Corp 半導体装置及びそれを用いた半導体モジュール
JP3916854B2 (ja) * 2000-06-28 2007-05-23 シャープ株式会社 配線基板、半導体装置およびパッケージスタック半導体装置
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
JP2003007918A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP3583396B2 (ja) * 2001-10-31 2004-11-04 富士通株式会社 半導体装置の製造方法、薄膜多層基板及びその製造方法
US6573595B1 (en) * 2002-04-24 2003-06-03 Scientek Corp. Ball grid array semiconductor package with resin coated metal core

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1957465B (zh) * 2004-05-21 2011-04-06 日本电气株式会社 半导体器件及配线基板
US7696613B2 (en) 2005-09-07 2010-04-13 Shinko Electric Industries Co., Ltd. Multilayered wiring substrate including wiring layers and insulating layers and method of manufacturing the same
CN101604675B (zh) * 2007-03-30 2011-07-27 三洋电机株式会社 基板及其制造方法、电路装置及其制造方法
US8258409B2 (en) 2007-03-30 2012-09-04 Sanyo Electric Co., Ltd. Circuit board and circuit device
CN107431017A (zh) * 2015-03-31 2017-12-01 浜松光子学株式会社 半导体装置
CN107431017B (zh) * 2015-03-31 2020-12-04 浜松光子学株式会社 半导体装置

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