JP3549017B2 - フリップチップ実装方法 - Google Patents

フリップチップ実装方法 Download PDF

Info

Publication number
JP3549017B2
JP3549017B2 JP2000219911A JP2000219911A JP3549017B2 JP 3549017 B2 JP3549017 B2 JP 3549017B2 JP 2000219911 A JP2000219911 A JP 2000219911A JP 2000219911 A JP2000219911 A JP 2000219911A JP 3549017 B2 JP3549017 B2 JP 3549017B2
Authority
JP
Japan
Prior art keywords
electrode
circuit
circuit board
semiconductor element
electrode material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000219911A
Other languages
English (en)
Other versions
JP2002043364A (ja
Inventor
謙治 森本
博 越智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2000219911A priority Critical patent/JP3549017B2/ja
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to KR10-2002-7003675A priority patent/KR100429740B1/ko
Priority to PCT/JP2001/006230 priority patent/WO2002009485A2/en
Priority to CNB018021085A priority patent/CN1239056C/zh
Priority to AT01951916T priority patent/ATE442764T1/de
Priority to DE60139852T priority patent/DE60139852D1/de
Priority to EP01951916A priority patent/EP1232677B1/en
Priority to US10/088,479 priority patent/US6750132B2/en
Priority to TW090117657A priority patent/TW517317B/zh
Publication of JP2002043364A publication Critical patent/JP2002043364A/ja
Priority to US10/839,157 priority patent/US7034389B2/en
Application granted granted Critical
Publication of JP3549017B2 publication Critical patent/JP3549017B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0514—Photodevelopable thick film, e.g. conductive or insulating paste

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はフリップチップ実装体およびその実装方法に関し、詳しくはフリップチップ実装に適した電極構造を回路基板に持たせたフリップチップ実装体およびその実装方法に関する。
【０００２】
【従来の技術】
近年、電子回路は高密度化が進んでおり、実装されるデバイスには面積および接続抵抗の低減が強く求められている。高密度実装を達成する１つの手段にフリップチップ実装があり、そのための実装方法が各種あるなかで、リペアの容易さや近年クローズアップされている無鉛化を考えると、ＳＢＢ方式（Stud Bump Bonding ）は望ましい工法である。ＳＢＢ方式とは、半導体素子上に金などの材料を用いてワイヤーボンディング手法により突起電極を形成し、その突起電極と回路基板上の電極とを導電性樹脂により接続する工法である。
【０００３】
図３を用いて説明すると、まず回路基板１１上にスクリーン印刷などの方法によってペースト状電極材料を印刷し、この電極材料が焼結する温度にて回路基板１１を焼成することにより、回路基板１１上に回路電極１２を形成する。一方で、半導体素子１３上にワイヤーボンディングなどの方法により突起電極１４を形成し、その突起電極１４上に転写などの方法によって導電性樹脂１５の層を形成する。その後に、回路基板１１と半導体素子１３とを高精度に位置合わせし、適当な荷重をかけることにより、回路基板１１上に半導体素子１３を実装する。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記した従来の実装方法には以下のような課題があった。第１に、近年は半導体素子１３の電極ピッチが狭くなる一方であり、当然のことながらそれに伴って回路基板１１上の電極ピッチも狭くしなければならない。ところが、従来のスクリーン印刷方法ではピッチを３００μｍとするのが限界で、それ以下のピッチでの印刷は非常に困難であり、ショートや断線が多発し歩留まりが低くなる原因となっていた。
【０００５】
第２に、半導体素子１３の電極ピッチが狭くなると、半導体素子１３の突起電極１４上に転写する導電性樹脂１５の量のコントロールが非常に困難になり、特にショートの危険性が増す。ショートを防ぐために導電性樹脂１５の量を従来よりも低減するようにしているが、回路電極１２は、電極材料が横に拡がってしまう結果、例えば電極ピッチ１００μｍ以下では断面が半円状を呈しており、この回路電極１２に対してフリップチップ実装を行うと、図３に示したように回路電極１２から導電性樹脂１５がはみ出し、隣接した回路電極１２からはみ出した導電性樹脂１５とショートすることがある。
【０００６】
本発明が課題とするのは、半導体素子の電極ピッチが狭い場合も安定して回路基板に接続できるようにすることである。
【０００７】
【課題を解決するための手段】
上記課題を解決するために本発明は、半導体素子に形成した突起電極を導電性樹脂を用いて回路基板の回路電極に接続するに際して、
(a) 光重合性物質を含んだペースト状の電極材料を用いて電極材料膜を所定の乾燥膜厚にて形成する工程、
(b) 電極材料膜を露光し現像する工程、
(c) 現像した電極材料膜を焼成する工程、
(d) 上記工程により形成された回路電極上に半導体素子をフリップチップ実装する工程、を行なうものである。
【０００８】
このようにすることにより、周縁部が反った回路電極を形成し、その凹面を受け皿として、導電性樹脂のはみ出しを来たすことなく半導体素子をフリップチップ実装することが可能になる。その結果、ショートの発生を皆無にすることができ、信頼性の高い半導体素子の実装を実現できる。
【０００９】
回路基板としてはセラミックを用いることができる。この回路基板には、上記したような半導体素子を搭載するための回路電極を備えた回路はもちろんのこと、半導体素子以外の部品を搭載するための回路や、別の基板への接続のための回路を設けることができる。
【００１０】
電極材料は少なくとも、金や銀や銅などの金属材料とガラスを無機成分として含み、重合性物質であるモノマーやポリマー、光重合開始剤を有機成分として含有したものを用いる。形成した回路電極の表面にニッケルや金などのメッキを施してもよい。
【００１１】
半導体素子は、金、アルミニウム、銅、半田などの金属材料で突起電極が形成されたものを使用する。突起電極の形成方法はワイヤーボンディングやメッキなど、工法を問わない。
【００１２】
導電性樹脂は、半導体素子上の突起電極と回路基板上の回路電極とを接続する金や銀や銅など導電性成分を含有していればよく、樹脂自体は熱硬化性でも熱可塑性でもよく、その種類は問わない。
【００１３】
上記工程(a) では、回路基板上にペースト状の電極材料を印刷することにより膜を形成する。電極材料は半導体素子が実装される実装領域のみ印刷すればよく、それ以外の領域については、前述した従来法により予め回路パターンを形成しておくなどの工法をとればよい。また印刷に際しては、回路パターンを形成するのではないので、実装領域にベタ印刷すればよく、従来のスクリーン印刷などのラフな印刷法で十分である。印刷後には電極材料の流動を防ぐために適度な温度で乾燥させる。ただし、乾燥後に所定の膜厚、望ましくは１０〜２０（μｍ）になるように印刷版および印刷条件を設定する。
【００１４】
工程(b) では、印刷・乾燥を行った回路基板に、半導体素子が搭載される電極領域のみ光が透過するように形成されたガラスマスクなどを位置合わせし、波長３２０〜３７０ｎｍの紫外線を３００〜５００ｍＪ照射する。これにより、紫外線が透過する電極領域の重合性物質が光重合開始剤によって反応を開始しポリマー化する。適当時間後に未反応の重合性物質が溶解する溶液を用いて基板全体を現像することにより、電極領域以外の膜を除去し、電極領域の膜を残留させる。なおこの時、膜厚を調整しておくことにより、光が届きにくい基板寄り部分の重合性物質を重合不十分のまま残留させ、現像時に非電極領域の膜除去跡から侵食させ、結果的に、電極領域の膜の断面形状が台形を呈するようにしておく。膜厚が薄いと電極領域の重合性物質は全て重合し、台形断面形状が得られないので、前述した膜厚が必要となる。
【００１５】
工程(c) では、露光・現像が完了した回路基板を、電極材料が焼結する温度にて焼成することにより、回路基板上に回路電極を焼き付ける。このとき電極材料膜がやや収縮するため、形成される回路電極は両側がやや反り返り（この部分はエッジカールと呼ばれる）、断面が円弧の様な形状となる。焼成後に電極表面の保護を目的としてニッケルや金などのメッキを施してもよい。
【００１６】
工程(d) では、突起電極が形成された半導体素子を、導電性樹脂を用いて回路基板上にフリップチップ実装する。このときには、回路電極のエッジカールが壁として機能するため、導電性樹脂のはみ出しは防止される。
【００１７】
【発明の実施の形態】
請求項１記載の本発明は、突起電極が形成された半導体素子を導電性樹脂を用いて回路基板上にフリップチップ実装するに際して、前記回路基板上の半導体素子実装領域に、光重合性物質を含んだペースト状の電極材料を印刷して所定厚さの膜を形成し、この電極材料膜を予め決めた電極領域のみ残留するように露光および現像した後に焼成することにより、前記回路基板上に周縁部が基板表面から離間する方向に反った凹状の回路電極を作成し、前記半導体素子の突起電極と前記回路電極の凹面とを当接させ、前記電極どうしの当接部を囲み前記回路電極の凹面に保持される前記導電性樹脂を介して接続することを特徴とする。
【００１８】
請求項２記載の本発明は、請求項１記載のフリップチップ実装方法において、電極材料膜を、乾燥膜厚が１０〜２０マイクロメートルとなるように形成することを特徴とする。
【００１９】
請求項３記載の本発明は、請求項１または請求項２のいずれかに記載のフリップチップ実装方法において、現像後に残留する電極材料膜が、回路基板から離れるほど拡幅する台形状の断面を有することを特徴とする。
【００２０】
請求項４記載の本発明は、請求項１〜請求項３のいずれかに記載のフリップチップ実装方法において、回路電極が円弧状の断面を有することを特徴とする。
【００２２】
以下、本発明の実施の形態を図面を参照しながら具体的に説明する。
図１は本発明の実施の形態１における半導体素子の実装方法を説明する工程断面図である。
【００２３】
図１(a) に示すように、回路基板１上の半導体素子搭載エリアに、光重合性物質を含んだペースト状の電極材料２を印刷し、印刷後の電極材料２が流動しないように適度な温度にて乾燥させる。このとき、電極材料２は、乾燥後の膜厚が１０〜２０μｍになるように印刷版、条件を設定して印刷する。
【００２４】
次に、図１(b) に示すように、電極材料２の膜の上に、所望の回路パターン形状にて光が透過するように、ここでは電極領域に相応する５０μｍ幅の開口部３ａが１００μｍピッチで形成されたガラスマスク３を、回路基板１に対して位置合わせし設置する。そして、ガラスマスク３の上方から、波長３２０〜３７０ｎｍのＵＶ（紫外線）を３００〜５００ｍＪ照射する。
【００２５】
このことにより、開口部３ａを通過したＵＶにより、図１(c) に示すように、電極領域２ａの電極材料２で光重合性物質、すなわち光重合開始剤，モノマー，ポリマーが反応してポリマー化が進み、非電極領域２ｂの電極材料２では重合反応は起こらない。回路基板１付近にはＵＶは侵入し難いため、この部分の電極材料２では重合反応は起こりにくい。
【００２６】
次に、アルカリ性の水溶液などを用いて現像を行なうことにより、重合反応が全く、あるいは十分に起こらなかった電極材料２を溶解・除去する。このことにより、図１(d) に示すように、非電極領域２ｂの電極材料２が除去され、電極領域２ａの電極材料２は、その表面付近は浸食されずガラスマスク３の開口部３ａ形状に相応した形状で残留する一方で、回路基板１付近では開口部３ａ形状よりも大きく浸食され、結果として、電極領域２ａの電極材料２の断面は台形を呈する。
【００２７】
その後に、電極材料２が焼結する温度で回路基板１を焼成することにより、図１(e) に示すように、回路基板１上の電極材料２を回路電極４として焼き付ける。図からわかるように、焼成時の電極材料２の収縮によって、回路電極４は、周縁部が回路基板１から離れる方向に反り入る（エッジカールする）形となり、円弧状の断面を呈する。
【００２８】
最後に、図１(f) に示すように、突起電極５に導電性樹脂６を転写した半導体素子７を回路基板１上に、突起電極５と回路電極４とが対向するように高精度に位置合わせし、適当な荷重をかけて互いに当接させ、導電性樹脂６を硬化させることにより、半導体素子７のフリップチップ実装を完了する。
【００２９】
このようにして製造されるフリップチップ実装体では、エッジカールした回路電極４が、この回路電極４から導電性樹脂６がはみ出すのを防ぐので、電極ピッチを１００μｍピッチとした半導体素子７を実装する際も、隣接する電極どうしがショートすることはない。
【００３０】
なおここで、回路電極４についてさらに説明する。
図１(e) に示したような、回路基板１表面からエッジカールした回路電極４までの最大距離をエッジカール量Ｌと定義すると、エッジカール量Ｌは、図１(a) に示した電極材料２の乾燥膜厚に大きく依存する。乾燥膜厚が１０〜２０μｍの場合にはエッジカール量Ｌは２〜１０μｍとなり、回路電極４は受け皿としての機能を果たす。
【００３１】
これに対し、乾燥膜厚を２０μｍ以上とすると、未重合部分が多くなり、本来現像されて消滅すべき部分の電極材料２が残るため、ショートを引き起こす。逆に乾燥膜厚を１０μｍ以下とすると、エッジカール量Ｌが２μｍ以下となり、受け皿としての機能が充分に発揮されない。
【００３２】
図２に本発明の実施の形態２における半導体素子の実装方法を説明する工程断面図を示す。
図２(a) に示すように、実施の形態１と同様にして、回路基板１上にエッジカールした回路電極４を形成する。次に、回路電極４に相応する部分が開口されたマスクを位置合わせし印刷などの手法を用いて、図２(b) に示すように回路電極４に導電性樹脂６を塗布する。その後に、図２(c) に示すように、この回路基板１に対して、突起電極５が形成された半導体素子７を位置合わせし適当な荷重をかけることにより、半導体素子７のフリップチップ実装を完了する。
【００３３】
このような方法によっても、実施の形態１と同様に、エッジカールした回路電極４が受け皿となり導電性樹脂６のはみ出しを防ぐので、ショートの発生がなくなる。
（実施例）
上記した製造工程にしたがって半導体素子を実装しその性能を評価した。使用した部材、材料は以下の通りである。
【００３４】
Figure 0003549017
電極材料は、金属成分として銀を含み乾燥膜厚１５μmとした。そして、この電極材料膜を、約５０μm幅の開口部を形成したガラスマスクを用いて露光・現像し、約８００〜１０００℃で焼成することにより、回路電極とした。このときエッジカールは４μmであった。表面保護のためＮｉメッキ、Ａｕメッキを施した。
【００３５】
ＩＣ：ダミーＩＣ
ＩＣサイズ１０×１０×０．５(mm)
ＩＣ電極パッドピッチ：１００（μm)
ピン数：３６０ピン
上記ＩＣの電極上に金線を用いて突起電極を形成し、形成した突起電極に金属成分として銀を含み樹脂成分としてエポキシを含有する導電性樹脂を転写した。この導電性樹脂を備えたＩＣを上記回路基板と位置あわせし、１つの突起電極あたり数ｇの加重をかけることにより実装した。そして、導電性樹脂を加熱により硬化させた後に、ショート・オープンについて評価を行ない、表１のような結果を得た。
【００３６】
【表１】
Figure 0003549017
表１からわかるように、本発明の工法ではオープン、ショートとも全く発生しなかったのに対し、従来の工法では４／５実装体にショートが発生し、本発明の有効性が確認された。
【００３７】
【発明の効果】
以上のように本発明によれば、回路基板上にエッジカールした回路電極を形成し、この回路電極に半導体素子の突起電極を導電性樹脂を用いて接続するようにしたことにより、回路電極を受け皿として導電性樹脂のはみ出しを防止することができ、ショートが発生しない、信頼性の高い半導体素子の実装を実現できる。
【図面の簡単な説明】
【図１】本発明の実施の形態１における半導体素子のフリップチップ実装方法を説明する工程断面図
【図２】本発明の実施の形態２における半導体素子のフリップチップ実装方法を説明する工程断面図
【図３】従来の半導体素子のフリップチップ実装方法を説明する工程断面図
【符号の説明】
１ 回路基板
２ 電極材料
2a 電極領域
2b 非電極領域
３ ガラスマスク
４ 回路電極
５ 突起電極
６ 導電性樹脂
７ 半導体素子
Ｌ エッジカール量

Claims (4)

  1. 突起電極が形成された半導体素子を導電性樹脂を用いて回路基板上にフリップチップ実装するに際して、
    前記回路基板上の半導体素子実装領域に、光重合性物質を含んだペースト状の電極材料を印刷して所定厚さの膜を形成し、この電極材料膜を予め決めた電極領域のみ残留するように露光および現像した後に焼成することにより、前記回路基板上に周縁部が基板表面から離間する方向に反った凹状の回路電極を作成し、前記半導体素子の突起電極と前記回路電極の凹面とを当接させ、前記電極どうしの当接部を囲み前記回路電極の凹面に保持される前記導電性樹脂を介して接続することを特徴とするフリップチップ実装方法。
  2. 電極材料膜は乾燥膜厚が１０〜２０マイクロメートルとなるように形成することを特徴とする請求項１記載のフリップチップ実装方法。
  3. 現像後に残留する電極材料膜が、回路基板から離れるほど拡幅する台形状の断面を有することを特徴とする請求項１または請求項２のいずれかに記載のフリップチップ実装方法。
  4. 回路電極が円弧状の断面を有することを特徴とする請求項１〜請求項３のいずれかに記載のフリップチップ実装方法。
JP2000219911A 2000-07-21 2000-07-21 フリップチップ実装方法 Expired - Fee Related JP3549017B2 (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP2000219911A JP3549017B2 (ja) 2000-07-21 2000-07-21 フリップチップ実装方法
US10/088,479 US6750132B2 (en) 2000-07-21 2001-07-18 Flip chip package, circuit board thereof and packaging method thereof
CNB018021085A CN1239056C (zh) 2000-07-21 2001-07-18 倒装片封装、其电路板以及其封装方法
AT01951916T ATE442764T1 (de) 2000-07-21 2001-07-18 Flip-chip gehäuse, schaltplatte und dessen verpackungsmethode
DE60139852T DE60139852D1 (de) 2000-07-21 2001-07-18 Flip-chip gehäuse, schaltplatte und dessen verpackungsmethode
EP01951916A EP1232677B1 (en) 2000-07-21 2001-07-18 Flip chip package, circuit board thereof and packaging method thereof
KR10-2002-7003675A KR100429740B1 (ko) 2000-07-21 2001-07-18 플립칩 패키지, 그 회로기판 및 그 패키지 방법
PCT/JP2001/006230 WO2002009485A2 (en) 2000-07-21 2001-07-18 Flip chip package, circuit board thereof and packaging method thereof
TW090117657A TW517317B (en) 2000-07-21 2001-07-19 A flipchip package, wiring substrate, and package method for the same
US10/839,157 US7034389B2 (en) 2000-07-21 2004-05-06 Flip chip package, circuit board thereof and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000219911A JP3549017B2 (ja) 2000-07-21 2000-07-21 フリップチップ実装方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2004016423A Division JP3926335B2 (ja) 2004-01-26 2004-01-26 フリップチップ実装体およびそのための回路基板

Publications (2)

Publication Number Publication Date
JP2002043364A JP2002043364A (ja) 2002-02-08
JP3549017B2 true JP3549017B2 (ja) 2004-08-04

Family

ID=18714606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000219911A Expired - Fee Related JP3549017B2 (ja) 2000-07-21 2000-07-21 フリップチップ実装方法

Country Status (9)

Country Link
US (2) US6750132B2 (ja)
EP (1) EP1232677B1 (ja)
JP (1) JP3549017B2 (ja)
KR (1) KR100429740B1 (ja)
CN (1) CN1239056C (ja)
AT (1) ATE442764T1 (ja)
DE (1) DE60139852D1 (ja)
TW (1) TW517317B (ja)
WO (1) WO2002009485A2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822836B2 (en) 2008-09-19 2014-09-02 Nec Corporation Bonding sheet, electronic circuit device and its manufacturing method

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4639586B2 (ja) * 2003-12-05 2011-02-23 セイコーエプソン株式会社 導電パターンの形成方法、配線の形成方法、半導体装置の製造方法、回路基板の製造方法、並びに、電子部品の製造方法
US20070045647A1 (en) * 2005-09-01 2007-03-01 Wintek Corporation Display panel package
JP4294722B2 (ja) * 2006-04-27 2009-07-15 パナソニック株式会社 接続構造体及びその製造方法
AT505111B1 (de) * 2007-04-12 2009-05-15 Rosenbauer Int Ag Einsatzvorrichtung zur brandbekämpfung
KR100842921B1 (ko) 2007-06-18 2008-07-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
JP5002633B2 (ja) * 2009-09-30 2012-08-15 三洋電機株式会社 半導体モジュールおよび携帯機器
CN101807532B (zh) * 2010-03-30 2012-05-09 上海凯虹科技电子有限公司 一种超薄芯片的倒装式封装方法以及封装体
KR102082778B1 (ko) 2012-08-27 2020-03-02 삼성디스플레이 주식회사 Ｆｐｃｂ 조립체 및 그것을 채용한 평판 표시 장치
KR101431918B1 (ko) * 2012-12-31 2014-08-19 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 표면처리방법
CN112822866B (zh) * 2021-01-07 2022-05-27 Tcl华星光电技术有限公司 用于表面贴装的锡膏、驱动电路板及表面贴装方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049480A (en) * 1990-02-20 1991-09-17 E. I. Du Pont De Nemours And Company Photosensitive aqueous developable silver conductor composition
JPH0666355A (ja) 1992-08-20 1994-03-08 Mitsubishi Motors Corp 自動車のエンジンとトルクコンバータとの結合構造
US5338391A (en) * 1993-10-12 1994-08-16 Motorola, Inc. Method of making a substrate having selectively releasing conductive runners
DE69428181T2 (de) 1993-12-13 2002-06-13 Matsushita Electric Industrial Co., Ltd. Vorrichtung mit Chipgehäuse und Verfahren zu Ihrer Herstellung
JP3320932B2 (ja) * 1993-12-13 2002-09-03 松下電器産業株式会社 チップパッケージ実装体、及びチップパッケージが実装される回路基板、並びに回路基板の形成方法
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
JPH0878476A (ja) * 1994-09-08 1996-03-22 Hitachi Ltd 半導体集積回路装置
JPH08222840A (ja) * 1995-02-15 1996-08-30 Sumitomo Metal Ind Ltd 電極パッド付き回路基板およびその製造方法
US5903056A (en) * 1997-04-21 1999-05-11 Lucent Technologies Inc. Conductive polymer film bonding technique
JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
JPH11121527A (ja) * 1997-10-21 1999-04-30 Pfu Ltd ベアチップ実装方法およびセラミック基板の製造方法およびセラミック基板ならびに半導体装置
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
JP4159213B2 (ja) * 1999-11-17 2008-10-01 日本アビオニクス株式会社 フリップチップ実装方法
JP2001267366A (ja) * 2000-03-16 2001-09-28 Matsushita Electric Ind Co Ltd 半導体実装方法およびプリント回路基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822836B2 (en) 2008-09-19 2014-09-02 Nec Corporation Bonding sheet, electronic circuit device and its manufacturing method

Also Published As

Publication number Publication date
WO2002009485A3 (en) 2002-06-06
WO2002009485A2 (en) 2002-01-31
CN1386394A (zh) 2002-12-18
US20040227253A1 (en) 2004-11-18
DE60139852D1 (de) 2009-10-22
US6750132B2 (en) 2004-06-15
EP1232677B1 (en) 2009-09-09
KR100429740B1 (ko) 2004-05-03
US7034389B2 (en) 2006-04-25
JP2002043364A (ja) 2002-02-08
US20020175407A1 (en) 2002-11-28
KR20020030122A (ko) 2002-04-22
ATE442764T1 (de) 2009-09-15
EP1232677A2 (en) 2002-08-21
CN1239056C (zh) 2006-01-25
TW517317B (en) 2003-01-11

Similar Documents

Publication Publication Date Title
US7579684B2 (en) Methods for packing microfeature devices and microfeature devices formed by such methods
JP3549017B2 (ja) フリップチップ実装方法
JP2000058709A (ja) 突起電極構造および突起電極形成方法
JP2001094003A (ja) 半導体装置及びその製造方法
JP3871634B2 (ja) Ｃｏｆ半導体装置の製造方法
JP2002203869A (ja) バンプの形成方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP4015787B2 (ja) 半導体装置の製造方法
JP2007517410A (ja) パターン回路およびその製造方法
JP3926335B2 (ja) フリップチップ実装体およびそのための回路基板
JP2002184802A (ja) 微小バンプの製造方法
JP4015790B2 (ja) 半導体装置の製造方法
JPH07326853A (ja) プリント配線板のボールバンプ形成方法
JP2002299361A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JPH08293661A (ja) セラミックス回路基板及びその製造方法
JP4461628B2 (ja) 半導体パッケージの製造方法
JP2980402B2 (ja) 回路部品搭載用中間基板の製造法
JP2003100792A (ja) 突起電極の形成方法
TWI263315B (en) Leadframe, semiconductor package and method for manufacturing the same
JP2001144405A (ja) 実装基板
JPH08191179A (ja) 半田バンプ用半田ダムの形成方法及び半田バンプの形成方法
JP2000022305A (ja) チップ実装用配線基板の製造方法
JPH0389537A (ja) セラミックパッケージおよびその製造方法
JP3021509B2 (ja) 導電突起の形成方法
JPH02304945A (ja) 半導体素子の実装方法
JP2003051574A (ja) リードフレームの製造方法

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20031209

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040126

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20040217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040316

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040413

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080430

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090430

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100430

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110430

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120430

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130430

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees