TWI263315B - Leadframe, semiconductor package and method for manufacturing the same - Google Patents

Leadframe, semiconductor package and method for manufacturing the same Download PDF

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Publication number
TWI263315B
TWI263315B TW093140835A TW93140835A TWI263315B TW I263315 B TWI263315 B TW I263315B TW 093140835 A TW093140835 A TW 093140835A TW 93140835 A TW93140835 A TW 93140835A TW I263315 B TWI263315 B TW I263315B
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TW
Taiwan
Prior art keywords
annular
lead frame
pins
pin
manufacturing
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TW093140835A
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Chinese (zh)
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TW200623344A (en
Inventor
Hung-Ta Hsu
Tzu-Bin Lin
Ya-Ling Hung
Ya-Yu Hsieh
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Advanced Semiconductor Eng
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Priority to TW093140835A priority Critical patent/TWI263315B/en
Publication of TW200623344A publication Critical patent/TW200623344A/en
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Publication of TWI263315B publication Critical patent/TWI263315B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package includes a chip and a leadframe. The chip includes a plurality of solder bumps disposed thereon. The leadframe includes a plurality of leads and annular stoppers, wherein each lead has a surface, and the annular stoppers are respectively formed on the surfaces of the leads and respectively define a solder area for soldering to the corresponding solder bump of the chip.

Description

1263315 九、發明說明： 【發明所屬之技術領域】 本兔明係有關於一種半導體封裝構造，更特別 環 種具有導線架之半導體封裝構造’料線架包含複= 狀擋件。 【先前技術】 於半導體封裝製程中，一導線架通常用以承载晶片，、， 用以將該晶片電性連接於一外部電路板。該導線架之並 可為導電性金屬，諸如銅或銅合金。炎老筮]'' 彡巧矛1及2圖，該 導線架20之引腳24之上下表面及側面係塗佈有_高分子 材料層40,然後一矩形狀中空部分42係藉由雷射切^製 程而形成該高分子材料層40内，並裸露出該矩形狀中空部 分42下方之引腳24。該矩形狀中空部分於該引腳24上界 定一潤濕區域（wettable regi〇n)21，用於迴銲製程時可辉接 一銲錫凸塊（solder bump)14。該高分子材料層4〇之表面界 定一非潤濕區域（non wettable region)22，用於迴銲製程時 將融化後之銲錫凸塊限制於該潤濕區域内。然而，該高分 子材料層係塗佈於該引腳之之整個上下表面及侧面上，如 此將增加高分子材料之成本。 美國專利第6,593,545號，標題為“用於覆晶導線架封 裝構造製造方法之被雷射界定之接墊（Laser Defined Pad For Flip Chip On Leadframe Package Fabrication method)” ，揭示一種用以改善導線架潤濕區域之方法。該 方法係利用雷射裝置形成非潤濕性阻障。該非潤濕性阻障 〇〇994-TW(ASEK-1158) 5 1263315 界定-潤濕區域。由於該非濁濕性阻障係藉由雷射裝置之 單-自動步驟而形& ’因此該非潤濕性阻障係以低成本而 形成。當晶片係藉由銲錫凸塊固定於導線架時，該非潤濕 性阻障可碟保融化後之銲錫凸塊限制於該潤濕區域内。然 而$知方法並無利用非潤濕性阻障之高度或深度作為阻 !融化後之銲錫凸塊溢出。再者，習知方法亦無揭示利用 環狀非潤濕性阻障作為阻擋融化後之銲錫凸塊溢出。 因此，便有需要提供一種導線架及半導體封裝構造，能 夠解決前述的缺點。 壯本t月之目的在於提供一種具有導線架之半導體封 衣構义a ^線& &含複數個玉袁狀擔件，用於阻撞融化後 之鮮錫凸塊溢出。 人為達上述目的，本發明提供一種半導體封裝構造，其包 含曰曰片及導線架。該晶片包含複數個銲錫凸塊配置於 其^。該導線架包含複數個引腳及複數個環狀擋件，其中 j母一引腳具有一表面，而該等環狀擋件係分別形成於該 等引腳之表面，並分別界定出―銲接區與該晶片上相對應 之該銲錫凸塊銲接接合。 本發明之環狀擂件係可為一環狀築壩，其具有一預定高 度，可於迴銲製程時阻擋融化後之銲錫凸塊溢出。再者， 由=忒％狀築壩之高分子材料具有非潤濕性，可於迴銲製 私％將融化後之詳錫凸塊限制於該潤濕區域内。 本發明之環狀擋件係可為一環狀溝槽，其具有一預定深 00994-TW (ASEK-1158) 6 1263315 父：於迴鲜製程時阻擋融化後之焊錫凸塊溢出， ^于錫凸塊之兩度，亦即相較於 腳之間隙係較小，且銲错λ+η 射丁料墊與旬i 鲜錫凸塊與該引腳接合面積係較大 因此於溫度循環測試下具有較佳的可靠度。 為了讓本發明之上述和其 他a的知斂、和優點能更明 頒’下文將配合所附圖示，作詳細說明如下。 【實施方式】 麥考第2a及2b圖’其顯示本發明之第一實施例之導 架12〇。該導線架120包含複數個㈣124及 停 ，用以支撐該引腳124。通常地，該導線架之形成方^ 係將—導體基材圖案化或㈣，以形成該引腳及支撐肋 條。才复數個核狀擔株，含卷上班 牛啫如裱狀榮壩（dam) 126係可藉由網 板印刷製程或微影颠刻製程分別形成於該複數個引腳m 之表面。该％狀築壩126係可為圓形狀i27(如第&圖所示） 或矩形狀（圖中未示），且可為非潤濕性材料（non wettable material) 4如咼分子材料所製。該環狀築壩I%於該引 腳 124 上界定_々曰&广 丨疋-杯接區，諸如潤濕區域（wettable region)m，用於迴銲製程時可銲接一銲錫凸塊（μ七r bump)或錫球(s〇lder baU)。該環狀築壩圍繞銲錫凸塊 或錫球用於迴銲製程時阻擋融化後之銲錫凸塊或錫球溢 出。 本第一實施例之導線架製造方法，如下列之第3圖至第 6圖。參考第3圖，提供一導線架120，其包含複數個引腳 124。麥考第4圖，將一網板，諸如鋼板n 1，配置於該引 00994-TW (ASEK-1158) 7 1263315 腳1 24上，其中該鋼板13 1具有一環狀中空部分132。參 考第5圖，將一高分子材料1 34塗佈於該鋼板i 3丨表面上， 並填滿該環狀中空部分132。參考第6圖，提供一刮刀136, 將該鋼板130表面上之高分子材料134刮除。將該鋼板13〇 移除，並將位於該環狀中空部分132内之高分子材料134 硬化，如此將該環狀築壩！ 26形成於該導線架工2〇之引腳 124上，如第2a及2b圖所示。換言之，複數個環狀築壩 126係藉由網板印刷製程分別形成於該複數個引腳上。 本第一實施例之導線架之另一製造方法，如下列之第 3、7及8圖。參考第3圖，提供一導線架12〇，其包含複 數個引腳124。參考第7圖，將—感光性高分子材料14〇, 諸如正光阻塗佈於該引腳i 24上。參考第8圖，將一遮罩 142配置於该咼分子材•斗14〇上方，其中該遮罩⑷具有 %狀中空部分144;以及提供一光源146，諸如紫外光 (uv)’將该環狀中空部> 142下方之高分子材料““更化。 將。亥遮罩142及光源、146移除，並將未硬化之高分子材料 140蝕刻而移除，如此將該環狀築壩126形成於該導線竿 W之引腳124上，如第以及2b圖所示。換言之，複數 個&狀築丨！ 26係藉由微影飯刻製程分別形成於該複數個 引腳124上。 麥考第9圖，其顯示本發明之第一實施例之半導體封裝 構w 100。該半導體封裝構造1〇〇包含本發明之導線架 及一晶片110。該晶片11〇包含複數個銲墊112，其分別藉 由禝數個銲錫凸塊114電性連接於該導線架12〇之引腳 124,亦即該晶片H0係藉由覆晶接合方式固定於該導線架 00994-TW (ASEK-1158) 1263315 之引腳124上，且該導線架12〇之引腳124係可電性 連$於一外部電路板（圖中未示）。該銲錫凸塊u4係配置 /、千墊Π 2上，並與該導線架} 2〇之環狀築壩1的上相 對，之#接區_接接合。該晶片i丨Q及該導線架㈣係可 十衣於封膠體130内，並裸露出該導線架12〇之引腳124 之部分。 芩考第10圖，本發明之導線架12〇之環狀築壩126具 有一預定高度hi，可於迴銲製程時阻擋融化後之銲錫凸塊 114溢出。較佳地，若環狀築壩126之高度hi約等於三分 之一的該銲墊112與該引腳124之間隙出時，亦即hi = 1/3 H1，該環狀築壩126可有效阻播融化後之銲錫凸塊114溢 出°再者·’·由於該環狀築壩126之高分子材料具有非潤濕 (wettability)’可於迴銲製程時將融化後之銲錫凸塊114 限制於該潤濕區域1 2 1内。 參考第Ua及llb圖，其顯示本發明之第二實施例之導 線木220。遠導線架22〇包含複數個引腳224及支撐肋條 228 ’用以支撐該引腳224。複數個環狀撞件，諸如環狀溝 槽（gro〇ve)226係可藉由雷射刻印製程或微影㈣製程分別 形成於該複數個引腳224之表面。料狀溝槽以係可為 圓形狀（圖中未示）或矩形狀227(如第Ua圖所示）。該環狀 溝槽226於該引腳224上界定—銲㈣’諸如第—潤濕區 域221及第二潤濕區域222，其中該第—潤濕區域221係 用於迴銲製程時可銲接一銲錫凸塊或錫球，且該第二潤渴 區域222,用於迴銲製程時可容置融化後之銲錫凸塊或錫 球，並阻播融化後之銲錫凸塊或錫球溢出，以㈣該鮮錫 9 00994-TW (ASEK-1158) I263315 $塊或錫球之高度。因此，該環狀溝槽226圍繞銲锡凸塊 或錫球，可阻擋融化後之銲錫凸塊或錫球溢出。 ^本第二實施例之導線架製造方法，如下列之第12圖至 弟U圖。參考第12圖，提供一導線架22〇，其包含複數 :引腳224。參考第13目，提供-雷射裝置231，將複數 们溝槽232形成於該複數個引腳224内。將該雷射裝置 移除，如此將該環狀溝槽226形成於該導線架22〇之引腳 224上，如第i丨a及i丨b圖所示。換言之，複數個環狀溝槽 226係藉由雷射刻印製程分別形成於該複數個引腳上。 本第二實施例之導線架之另一製造方法，如下列之第 n圖及第14至17圖。參考第丨2圖，提供一導線架22〇, 其包含複數個引腳224。參考第14圖，將一光阻材料24〇， 诸如負光阻塗佈於該引腳224上。參考第i 5圖，將一遮罩 242配置於該光阻材料24〇上方，其中該遮罩242具有一 環狀中空部分244 ;以及提供一光源246，諸如紫外光 (UV) ’將該環狀中空部分2料下方之光阻材料24〇曝光而 形成一已曝光光阻材料248。參考第16圖，將該遮罩242 及光源246移除，並將已曝光光阻材料蝕刻而形成一環狀 中空部分250。參考第17圖，將該環狀中空部分25〇下方 之引腳224之表面蝕刻，以形成一溝槽252。將未曝光之 光阻材料移除，如此將該環狀溝槽226形成於該導線架22〇 之引腳224内，如第lla及nb圖所示。換言之，複數個 壞狀溝槽226係藉由微影蝕刻製程分別形成於該複數個引 腳224上° 〇〇994-TW(ASEK-1158) 10 1263315 毛月任何本發明所屬技術領域中且有、g ^ ^ 脫籬太於n口 J K a〒具有通常知識者，在不 因此本=之精rt範圍内，當可作各種之更動與修改。 為準。x之保4範圍#視後附之中請專利範圍所界定者 【圖式簡單說明】 剖面示意 圖 弟1及2圖為先前技術之導線架之引腳平面及 圖 第2a圖為本發 明之第一實施例之導線架之平面示意 第2b圖為沿第2a圖之剖線m之放大剖面示意圖。 第3至6圖為本發明之第—實施例之導線架製造方法之 剖面示意圖。 弟7至8圖為本發明之第-實施例之導線架之另/製造 方法之剖面示意圖。 一第9圖為本發明之第一實施例之半導體封裝構造之劄 面示意圖。 第10圖為第9圖之A部分放大剖面示意圖。 第1U圖為本發明之第二實施例之導線架之平面.意 圖。 第ub ®為沿帛lla圖之剖線llb-llb之放大刻面系意 圖。 第12至13圖為本發明之第二實施例之導線架製造方法 之剖面示意圖。 00994-TW (ASEK-1158) 12 1263315 第1 4至1 7圖為本發明之第二實施例之導線架之另一製 造方法之剖面示意圖。 第1 8圖為本發明之第二實施例之半導體封裝構造之剖 面示意圖。 第19圖為第1 8圖之B部分放大剖面示意圖。 【主要元件符號說明】 14 銲錫凸塊 16 錫鬚 20 導線架 21 潤濕區域 22 非潤濕區域 24 引腳 40 高分子材料層 42 矩形狀中空部分 100 半導體封裝構造 110 晶片 112 銲墊 114 銲錫凸塊 120 導線架 121 潤濕區域 124 引腳 126 環狀築壩 127 圓形狀 128 支撐肋條 130 封膠體 131 鋼板 132 環狀中空部分 134 高分子材料 136 刮刀 140 感光性南分子材料 142 遮罩 144 環狀中空部分 146 光源 200 半導體封裝構造 210 晶片 00994-TW (ASEK-1158) 13 1263315 212 銲墊 214 銲錫凸塊 220 導線架 221 第一潤濕區域 222 第二潤濕區域 224 引腳 226 環狀溝槽 227 矩形狀 228 支撐肋條 230 封膠體 231 雷射裝置 232 溝槽 240 光阻材料 242 遮罩 244 環狀中空部分 246 光源 248 已曝光光阻材料 250 環狀中空部分 252 溝槽 00994-TW (ASEK-1158) 141263315 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having a lead frame. The material line frame includes a complex-shaped stopper. [Prior Art] In a semiconductor packaging process, a lead frame is usually used to carry a wafer, and is used to electrically connect the chip to an external circuit board. The lead frame may be a conductive metal such as copper or a copper alloy.炎老筮]'' 彡 矛 矛 1 and 2, the lower surface and side of the lead 24 of the lead frame 20 are coated with a layer _ polymer material 40, and then a rectangular hollow portion 42 by laser The inside of the polymer material layer 40 is formed by a process, and the pins 24 under the rectangular hollow portion 42 are exposed. The rectangular hollow portion defines a wettable region 21 on the pin 24 for soldering a solder bump 14 during the reflow process. The surface of the polymer material layer 4 defines a non-wettable region 22 for limiting the melted solder bumps in the wetted region during the reflow process. However, the layer of the high molecular material is applied to the entire upper and lower surfaces and sides of the pin, thus increasing the cost of the polymer material. U.S. Patent No. 6,593,545, entitled "Laser Defined Pad For Flip Chip On Lead Frame Package Fabrication Method", discloses a method for improving lead frame run-up The method of wet area. This method utilizes a laser device to form a non-wetting barrier. The non-wetting barrier 〇〇994-TW(ASEK-1158) 5 1263315 defines the wetted area. Since the non-turbidity barrier is formed by the single-automatic step of the laser device, the non-wetting barrier is formed at a low cost. When the wafer is fixed to the lead frame by solder bumps, the non-wetting barrier can be shielded from melting solder bumps in the wetted region. However, the known method does not utilize the height or depth of the non-wetting barrier as a resistance! The solder bump overflow after melting. Furthermore, the conventional method does not disclose the use of a ring-shaped non-wetting barrier as a solder bump overflow after blocking melting. Therefore, there is a need to provide a lead frame and a semiconductor package structure that can solve the aforementioned drawbacks. The purpose of Zhuang Ben Tyue is to provide a semiconductor package with a lead frame. The a-line &&&&> contains a plurality of jade-like loaders for blocking the overflow of the fresh tin bumps after melting. In order to achieve the above object, the present invention provides a semiconductor package structure including a cymbal sheet and a lead frame. The wafer includes a plurality of solder bumps disposed thereon. The lead frame comprises a plurality of pins and a plurality of annular stops, wherein the j-pin has a surface, and the annular stops are respectively formed on the surfaces of the pins, and respectively define "welding" The region is solder bonded to the solder bump corresponding to the wafer. The annular member of the present invention may be an annular dam having a predetermined height to prevent the molten solder bump from overflowing during the reflow process. Furthermore, the polymer material dammed by = 忒% has non-wetting properties, and the molten tin bumps can be confined in the wetted region in the reflow process. The annular stop of the present invention can be an annular groove having a predetermined depth of 00994-TW (ASEK-1158) 6 1263315. The parent: the solder bump overflows after the melting process is blocked during the fresh-back process, ^ Yu The two degrees of the bump, that is, the gap between the two is smaller than that of the foot, and the welding error λ+η is the ratio of the joint area of the solder pad to the pin and the bonding area of the pin is large. Therefore, under the temperature cycle test Has better reliability. The above and other aspects of the present invention will become more apparent from the following description. [Embodiment] The Mai Khao 2a and 2b drawings show the guide 12 of the first embodiment of the present invention. The leadframe 120 includes a plurality of (four) 124 and stops for supporting the pins 124. Typically, the leadframe is patterned to pattern or (4) the conductor substrate to form the pins and support ribs. Only a plurality of nucleus-bearing plants, including rolls of work, burdocks such as 裱 荣 dam dam 126 can be formed on the surface of the plurality of pins m by a screen printing process or a lithography process. The % dam 126 can be a circular shape i27 (as shown in the figure & figure) or a rectangular shape (not shown), and can be a non-wettable material 4 such as a bismuth molecular material. system. The annular dam I% defines a 々曰 amp amp amp 杯 杯 杯 杯 , , , , , , , , , 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 124 ( Μ7 r bump) or tin ball (s〇lder baU). The annular dam is surrounded by solder bumps or solder balls to prevent the molten solder bumps or solder balls from overflowing during the reflow process. The lead frame manufacturing method of the first embodiment is as shown in Figs. 3 to 6 below. Referring to Figure 3, a leadframe 120 is provided that includes a plurality of pins 124. In McCaw 4, a screen, such as steel plate n 1, is placed on the foot 00994-TW (ASEK-1158) 7 1263315, which has an annular hollow portion 132. Referring to Fig. 5, a polymer material 134 is applied to the surface of the steel sheet i 3 , and the annular hollow portion 132 is filled. Referring to Fig. 6, a doctor blade 136 is provided to scrape the polymer material 134 on the surface of the steel sheet 130. The steel sheet 13 is removed, and the polymer material 134 located in the annular hollow portion 132 is hardened, so that the ring is dammed! 26 is formed on the lead 124 of the lead frame, as shown in Figures 2a and 2b. In other words, a plurality of annular dams 126 are formed on the plurality of pins by a screen printing process. Another method of manufacturing the lead frame of the first embodiment is as shown in Figures 3, 7 and 8 below. Referring to Figure 3, a leadframe 12A is provided that includes a plurality of pins 124. Referring to Fig. 7, a photosensitive polymer material 14?, such as a positive photoresist, is applied to the pin i24. Referring to FIG. 8, a mask 142 is disposed above the cymbal material hopper 14 ,, wherein the mask (4) has a % hollow portion 144; and a light source 146 such as ultraviolet light (uv) is provided to the ring The hollow material > 142 under the polymer material "". will. The black mask 142 and the light source 146 are removed, and the uncured polymer material 140 is etched and removed, so that the annular dam 126 is formed on the lead 124 of the wire ,W, as shown in FIG. 2b. Shown. In other words, a plurality of & The 26 series are formed on the plurality of pins 124 by a lithography process. Fig. 9 is a diagram showing a semiconductor package w 100 of the first embodiment of the present invention. The semiconductor package structure 1 includes a lead frame of the present invention and a wafer 110. The wafer 11A includes a plurality of solder pads 112 electrically connected to the leads 124 of the lead frame 12 by a plurality of solder bumps 114, that is, the wafer H0 is fixed by flip chip bonding. The lead frame of the lead frame 00994-TW (ASEK-1158) 1263315 and the lead wire 124 of the lead frame 12 are electrically connected to an external circuit board (not shown). The solder bumps u4 are arranged on the /, the pad Π 2, and are opposite to the upper side of the ring dam 1 of the lead frame, and the #接区_ is joined. The wafer i丨Q and the lead frame (4) can be embedded in the encapsulant 130 and exposed portions of the lead 124 of the lead frame 12〇. Referring to Fig. 10, the annular dam 126 of the lead frame 12 of the present invention has a predetermined height hi to prevent the molten solder bumps 114 from overflowing during the reflow process. Preferably, if the height hi of the annular dam 126 is approximately equal to one third of the gap between the pad 112 and the pin 124, that is, hi = 1/3 H1, the annular dam 126 can Effectively blocking the molten solder bump 114 from overflowing. Further, since the polymer material of the annular dam 126 has non-wetting ability, the solder bump 114 which will be melted during the reflow process Limited to the wetted area 1 2 1 . Referring to Figures Ua and 11b, there is shown a wire 220 of a second embodiment of the present invention. The distal leadframe 22A includes a plurality of pins 224 and support ribs 228' for supporting the pins 224. A plurality of annular strikers, such as annular grooves 226, may be formed on the surface of the plurality of pins 224 by a laser marking process or a lithography process. The material-like grooves may be in the shape of a circle (not shown) or a rectangular shape 227 (as shown in Figure Ua). The annular groove 226 defines a solder (four) such as a first wetted region 221 and a second wetted region 222 on the pin 224, wherein the first wetted region 221 is solderable during the reflow process. Solder bumps or solder balls, and the second thirsty region 222 can be used for reflow soldering bumps or solder balls during the reflow process, and to prevent the solder bumps or solder balls from overflowing after being melted. (d) The height of the fresh tin 9 00994-TW (ASEK-1158) I263315 $ block or solder ball. Therefore, the annular groove 226 surrounds the solder bump or the solder ball to block the molten solder bump or the solder ball from overflowing. The method of manufacturing the lead frame of the second embodiment is as shown in Fig. 12 below. Referring to Fig. 12, a lead frame 22A is provided which includes a plurality of pins 224. Referring to item 13, a laser device 231 is provided to form a plurality of trenches 232 in the plurality of pins 224. The laser device is removed such that the annular groove 226 is formed on the lead 224 of the lead frame 22, as shown in Figures ia and i丨b. In other words, a plurality of annular trenches 226 are formed on the plurality of pins by laser marking processes, respectively. Another manufacturing method of the lead frame of the second embodiment is as shown in the following nth and 14th to 17th. Referring to FIG. 2, a lead frame 22A is provided which includes a plurality of pins 224. Referring to Figure 14, a photoresist material 24, such as a negative photoresist, is applied to the pin 224. Referring to FIG. 5, a mask 242 is disposed over the photoresist material 24, wherein the mask 242 has an annular hollow portion 244; and a light source 246 is provided, such as ultraviolet light (UV). The photoresist material 24 under the hollow portion 2 is exposed to form an exposed photoresist material 248. Referring to Fig. 16, the mask 242 and the light source 246 are removed, and the exposed photoresist material is etched to form an annular hollow portion 250. Referring to Fig. 17, the surface of the lead 224 below the annular hollow portion 25 is etched to form a trench 252. The unexposed photoresist material is removed such that the annular trench 226 is formed in the lead 224 of the leadframe 22A as shown in Figures 11a and nb. In other words, a plurality of bad trenches 226 are formed on the plurality of pins 224 by a photolithography process respectively. 〇〇994-TW (ASEK-1158) 10 1263315 Mao Yue Any technical field of the present invention and , g ^ ^ The fence is too much for the n-port JK a〒 has the usual knowledge, in the range of the fine rt, it can be used for various changes and modifications. Prevail. x之保4范围# As defined in the attached patent, the scope of the patent is defined [Simple description of the diagram] The profile diagrams of the schematic diagrams 1 and 2 are the lead planes of the lead frame of the prior art and Fig. 2a is the The plane of the lead frame of an embodiment is shown in Fig. 2b as an enlarged cross-sectional view along the line m of Fig. 2a. 3 to 6 are schematic cross-sectional views showing a method of manufacturing a lead frame according to a first embodiment of the present invention. 7 to 8 are schematic cross-sectional views showing another embodiment of the lead frame of the present invention. Fig. 9 is a schematic view showing the structure of a semiconductor package according to a first embodiment of the present invention. Fig. 10 is an enlarged cross-sectional view showing a portion A of Fig. 9. Fig. 1U is a plan view showing the lead frame of the second embodiment of the present invention. The first ub ® is an enlarged facet of the llb-llb along the 帛lla diagram. 12 to 13 are schematic cross-sectional views showing a method of manufacturing a lead frame according to a second embodiment of the present invention. 00994-TW (ASEK-1158) 12 1263315 FIGS. 14 to 17 are schematic cross-sectional views showing another manufacturing method of the lead frame of the second embodiment of the present invention. Fig. 18 is a cross-sectional view showing the structure of a semiconductor package of a second embodiment of the present invention. Fig. 19 is an enlarged cross-sectional view showing a portion B of Fig. 18. [Main component symbol description] 14 solder bump 16 tin whisker 20 lead frame 21 wetted area 22 non-wetting area 24 pin 40 polymer material layer 42 rectangular hollow portion 100 semiconductor package structure 110 wafer 112 pad 114 solder bump Block 120 lead frame 121 wetted area 124 pin 126 annular dam 127 round shape 128 support rib 130 sealant 131 steel plate 132 annular hollow part 134 polymer material 136 scraper 140 photosensitive south molecular material 142 mask 144 ring Hollow Portion 146 Light Source 200 Semiconductor Package Construction 210 Wafer 00994-TW (ASEK-1158) 13 1263315 212 Pad 214 Solder Bump 220 Lead Frame 221 First Wetting Area 222 Second Wetting Area 224 Pin 226 Annular Trench 227 Rectangular 228 Support rib 230 Sealant 231 Laser device 232 Groove 240 Photoresist material 242 Mask 244 Annular hollow portion 246 Light source 248 Expoted photoresist material 250 Annular hollow portion 252 Groove 00994-TW (ASEK- 1158) 14

Claims (1)

1263315 ， ί j1263315 , ί j 1、 一種導線架，包含： 複數個引腳，每一引腳具有一表面； 複數個環狀擋件，分別形成於該等引腳之表面，並分 別界定出一銲接區，其中該環狀擋件係為一環狀溝槽， 其具有一預定深度；以及 複數個環狀非潤濕區域，形成於該等環狀溝槽之外 圍。 2、 依申請專利範圍第1項之導線架，其中該環狀溝槽係為 圓形狀。 3、 依申請專利範圍第1項之導線架，其中該環狀溝槽係為 * τ- -ΤΓΓ/ ，” ;'iZ ；1人 υ 4、 依申請專利範圍第1項之導線架，其中該環狀溝槽於該 引腳上界定一第一及第二潤濕區域，該第一潤濕區域係 用於銲接該銲錫，且該第二潤濕區域係用於容置融化後 銲錫，並阻擋融化後之銲錫溢出，以控制該銲錫之高度。 5、 一種導線架製造方法，包含下列步驟： 提供一導體基材； 圖案化該導體基材形成複數個引腳，該每一引腳具有 一表面； 將複數個環狀擋件分別形成於該等引腳之表面，並分 ，斤疋，-卜….焊接头丫线壤狀播件糸為-.;火薄彳曾， 其具有一預定深度；以及 00994-TW(ASEK-1158) 1263315 圍 激區域形成於該等環狀 之外 6 依申請專利範 溝槽係藉由—:、之導線架製造方法，其中該環狀 每射刻印製程形成於該引腳内。 依申請專利範圚窜< ^ 」U不5 j貝之導妗单制生 溝槽係藉由—n 卞农心力"、，其中該環狀 支衫蝕刻碱程形成於該引腳内。 依申請專利範岡裳7/ 溝槽形成方式:：；：：導線架製造方法，其中該環狀 、匕含下列步驟： 將-光阻材料塗佈於該弓丨腳上； 肘遮罩配置於該光阻材料上方 第-環狀中空部分；“上方，其中遠遐罩具有— :ί疋供—7^» >1^ ， 1]^ ^ 结 凹 0” ^厂，…r域中空部分下方之光” 蛄凡而形成—已曝光光阻材料； 一ΤΓ 二遮=源移除’並將已曝光光阻材料㈣而形 欣 弟一 ¥狀中空部分； 將該第二環狀中空部分下方之 义衣面敍乡彳；以及 將未曝光之光阻材料移除，如此將 該引腳内。 及狀，丹匕形成於 其中該光阻 9、依申請專利範圍第8項之導線架製造方法 材料係為負光阻Q 10 種半導體封裝構造，包含： 個 以及 00994-TW(ASEK-1158) !6 1263315 一辱縛罙 ' 包含： 複數個引腳，每一引腳具有一表面； 複數個環狀擋件，分別形成於該等引腳之表面，並 分別界定出一銲接區與該晶片上相對應之該銲錫凸 塊銲接接合，其中該環狀擋件係為一環狀溝槽，其具 有一預定深度；以及 複數個環狀非潤濕區域，形成於該等環狀溝槽之外 圍。 11、 依申請專利範圍第10項之半導體封裝構造，另包含 一封膠體’用以封裝該晶片及該導線架’並裸露出該導 線架之引腳之部分。 12、 依申請專利範圍第1 0項之半導體封裝構造，其中該 環狀溝槽之深度係約等於三分之一的該晶片與該引腳 之間隙。 13、 一種導線架，包含： 複數個引腳，每一引腳具有一表面；以及 複數個環狀擋件，分別形成於該等引腳之表面，並分 別界定出一銲接區，其中該環狀擋件係為一環狀築壩， 其具有一預定高度。 14、 依申請專利範圍第1 3項之導線架，其中該環狀築壩 係為圓形狀。 15、 依申請專利範圍第1 3項之導線.架，其中該環狀築増 係為矩形狀。 00994-TW (ASEK-1158) 1263315 16、 依申請專利範圍第13項之導線架，其中該環狀築壩 係為非潤濕性材料所製。 17、 依申請專利範圍第1 3項之導線架，其中該環狀築壩 係為高分子材料所製。 18、 依申請專利範圍第1 3項之導線架，其中該銲接區係 為一潤濕區域，適於與一銲錫銲接。 19、 一種導線架製造方法，包含下列步驟： 提供一導體基材； 圖案化該導體基材形成複數個引腳’該每一引廢卩具有 一表面；以及 將複數個環狀擋件分別形成於該等引腳之表面，並分 別界定出一銲接區，其中該環狀擋件係為一環狀築壩， 其具有一預定高度。 20、 依申請專利範圍第1 9項之導線架製造方法，其中該 環狀築壩係藉由一網板印刷製程形成於該引腳上。 21、 依申請專利範圍第20項之導線架製造方法，其中該 環狀築壩形成方式包含下列步驟： 將一網板配置於該引腳上，其中該網板具有一環狀中 空部分； 將一非潤濕性材料塗佈於該網板上，並填滿該環狀中 空部分； 將該網板上之非潤浅性材料刮除；以 將該網板移除，並將位於該環狀中空部分内之非潤濕 00994-TW (ASEK-1158) 1263315 性.#料硬化，如此將該環狀築塌形成於該引聯上。 22、 依申請專利範圍第21項之導線架製造方法，其中該 網板係為一鋼板。 23、 依申請專利範圍第2 1項之導線架製造方法，其中該 非潤濕性材料係為高分子材料。 24、 依申請專利範圍第1 9項之導線架製造方法，其中該 環狀築壩係藉由一微影I虫刻製程形成於該引腳上。 25、 依申請專利範圍第24項之導線架製造方法，其中該 環狀築壩形成方式包含下列步驟： 將一感光性非潤濕性材料塗佈於該引腳上； 將一遮罩配置於該感光性非潤濕性材料上方，其中該 遮罩1有一環狀中空部分； 提供一光源，將該環狀中空部分下方之該感光性非潤 濕性材料硬化；以及 將該遮罩及光源移除，並將未硬化之感光性非潤濕性 材料蝕刻而移除，如此將該環狀築壩形成於該引腳上。 26、 依申請專利範圍第25項之導線架製造方法，其中該 感光性非潤濕性材料係為感光性高分子材料。 27、 依申請專利範圍第26項之導線架製造方法，其中該 感光性高分子材料係為正光阻。 28、 一種半導體封裝構造，包含： …晶./1 ' …'沒寥调许靠勿ώ挺心至。ί共上，以及 00994-TW (ASEK^1158) 19 1263315 複數個引腳5每一引腳具有一表面；以及 複數個環狀擋件，分別形成於該等引腳之表面 分別界定出一銲接區與該晶片上相對應之該銲 堍銲接捿合，其申該環狀擋件係為一環狀纂壩， 有一預定高度。 29 ' 依申請專利範圍第28頊之半封f構造，另 一封膠體，用以封裝該晶片及該導線架，並裸露出 線架之引腳之部分。 30、 依申請專利範圍第28項之半導體封裝構造，其 環狀築壩係為非潤濕性材料所製。 3 1、 依申請葶利範圍第30項之半導體封裝構造，其 非潤濕性材料係為高分子材料。 32、 依申請專利範圍第28項之半導體封裝構造，其 環狀築壩之高度等於約三分之一的該晶片與該引 間隙。 ，並 錫凸 盆旦 包含 該導 中該 中該 中該 腳之 00994-TW (ASEK-1158 20A lead frame comprising: a plurality of pins each having a surface; a plurality of annular stops formed on the surfaces of the pins and defining a soldering region, wherein the ring The stop is an annular groove having a predetermined depth; and a plurality of annular non-wetting regions are formed on the periphery of the annular grooves. 2. The lead frame according to item 1 of the patent application scope, wherein the annular groove has a circular shape. 3. The lead frame according to item 1 of the patent application scope, wherein the annular groove is * τ- - ΤΓΓ / , "; iZ ; 1 person υ 4, according to the lead frame of the first application of the patent scope, wherein The annular groove defines a first and second wetted region on the pin, the first wetted region is used for soldering the solder, and the second wetted region is used for accommodating the molten solder. And blocking the molten solder overflow to control the height of the solder. 5. A lead frame manufacturing method comprising the steps of: providing a conductor substrate; patterning the conductor substrate to form a plurality of pins, each pin Having a surface; forming a plurality of ring-shaped members on the surface of the pins, and dividing, 疋, - 卜....welding head 丫 壤 壤 壤 壤 壤 - ; ; ; ; ; ; ; Having a predetermined depth; and 00994-TW (ASEK-1158) 1263315 The enveloping region is formed outside the loops. 6 According to the patent application vane, the lead frame manufacturing method is: The marking process is formed in the pin. According to the patent application specification < ^ U is not a j j 之 妗 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽 沟槽According to the application patent Fan Gangshang 7/groove formation method::;:: lead frame manufacturing method, wherein the ring and the cymbal include the following steps: coating a photoresist material on the arch foot; elbow mask configuration Above the photoresist material, the first annular hollow portion; "above, wherein the distal cover has - - ί 疋 - 7 ^ » > 1 ^ , 1] ^ ^ 结 concave 0" ^ factory, ... r domain Part of the light below 形成 形成 形成 形成 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已 已The lower part of the Yiyi noodles; and the removal of the unexposed photoresist material, so that the pin is inside, and the shape of the tantalum is formed in the photoresist, according to the wire of item 8 of the patent application scope The manufacturing method material is a negative photoresist Q 10 semiconductor package structure, including: 00994-TW (ASEK-1158) !6 1263315 an insult 罙' contains: a plurality of pins, each pin has a surface a plurality of annular stops formed on the surfaces of the pins and respectively Determining a soldering region to solder joints corresponding to the solder bumps on the wafer, wherein the annular barrier is an annular trench having a predetermined depth; and a plurality of annular non-wetting regions are formed On the periphery of the annular trenches. 11. The semiconductor package structure according to claim 10 of the patent application, further comprising a colloid 'for packaging the wafer and the lead frame' and exposing the lead of the lead frame The semiconductor package structure according to claim 10, wherein the annular trench has a depth equal to about one third of a gap between the wafer and the pin. 13. A lead frame comprising: a plurality of pins each having a surface; and a plurality of annular stops respectively formed on the surfaces of the pins and respectively defining a soldering region, wherein the annular blocking member is a ring shape The dam is constructed to have a predetermined height. 14. The lead frame according to item 13 of the patent application scope, wherein the annular dam is rounded. 15. According to the wire of the claim 13th, Ring-shaped raft 00994-TW (ASEK-1158) 1263315 16. The lead frame according to item 13 of the patent application scope, wherein the annular dam is made of non-wetting material. 17. According to the patent application scope 1 The lead frame of the item, wherein the annular dam is made of a polymer material. 18. The lead frame according to claim 13 of the patent application, wherein the welding zone is a wetted area, suitable for welding with a solder. 19. A method of manufacturing a lead frame, comprising the steps of: providing a conductor substrate; patterning the conductor substrate to form a plurality of pins; each of the depleting hoppers has a surface; and separating the plurality of ring members Formed on the surface of the pins, and respectively define a weld zone, wherein the ring stop is an annular dam having a predetermined height. 20. The lead frame manufacturing method according to claim 19, wherein the annular dam is formed on the pin by a screen printing process. 21. The lead frame manufacturing method according to claim 20, wherein the annular dam formation method comprises the following steps: arranging a stencil on the pin, wherein the stencil has an annular hollow portion; a non-wetting material is applied to the stencil and fills the annular hollow portion; the non-wetting material on the stencil is scraped off; the stencil is removed and will be located in the ring Non-wetting in the hollow portion 00994-TW (ASEK-1158) 1263315. The material is hardened, so that the ring is collapsed and formed on the lead. 22. The method of manufacturing a lead frame according to claim 21, wherein the stencil is a steel plate. 23. The lead frame manufacturing method according to claim 21, wherein the non-wetting material is a polymer material. 24. The lead frame manufacturing method according to claim 19, wherein the annular dam is formed on the pin by a lithography process. 25. The lead frame manufacturing method according to claim 24, wherein the annular dam forming method comprises the steps of: applying a photosensitive non-wetting material to the pin; and arranging a mask on the Above the photosensitive non-wetting material, wherein the mask 1 has an annular hollow portion; a light source is provided to harden the photosensitive non-wetting material under the annular hollow portion; and the mask and the light source are The uncured photosensitive non-wetting material is removed by etching and removed, so that the annular dam is formed on the pin. 26. The lead frame manufacturing method according to claim 25, wherein the photosensitive non-wetting material is a photosensitive polymer material. 27. The method of manufacturing a lead frame according to claim 26, wherein the photosensitive polymer material is a positive photoresist. 28, a semiconductor package structure, comprising: ... crystal. / 1 ' ... ... did not adjust to rely on the heart to the heart. ί, and 00994-TW (ASEK^1158) 19 1263315 a plurality of pins 5 each having a surface; and a plurality of annular stops respectively formed on the surfaces of the pins to define a solder The region is soldered to the solder joint corresponding to the wafer, and the annular stopper is an annular dam having a predetermined height. 29 ' According to the half-f structure of the 28th 申请 patent application, another gel is used to encapsulate the wafer and the lead frame, and expose the part of the lead of the wire frame. 30. According to the semiconductor package structure of claim 28, the annular dam is made of non-wetting material. 3 1. The non-wetting material is a polymer material according to the semiconductor package structure of the application for profit range 30. 32. The semiconductor package structure of claim 28, wherein the height of the annular dam is equal to about one-third of the wafer and the gap. And the tin-convex potent contains the 00994-TW (ASEK-1158 20)
TW093140835A 2004-12-27 2004-12-27 Leadframe, semiconductor package and method for manufacturing the same TWI263315B (en)

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