CN105514111A - 非挥发性存储器 - Google Patents

非挥发性存储器 Download PDF

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CN105514111A
CN105514111A CN201510620869.0A CN201510620869A CN105514111A CN 105514111 A CN105514111 A CN 105514111A CN 201510620869 A CN201510620869 A CN 201510620869A CN 105514111 A CN105514111 A CN 105514111A
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doped region
floating grid
transistor
well region
grid
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CN105514111B (zh
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徐德训
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eMemory Technology Inc
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Abstract

本发明公开一种非挥发性存储器，包括基底、浮置栅极晶体管、选择晶体管与应力释放晶体管。浮置栅极晶体管、选择晶体管与应力释放晶体管设置于基底上且彼此串接。应力释放晶体管位于浮置栅极晶体管与选择晶体管之间。所述非挥发性存储器可有效地降低选择晶体管所承受到的应力。

Description

非挥发性存储器
技术领域
本发明涉及一种存储器，且特别是涉及一种非挥发性存储器。
背景技术
当半导体进入深次微米(DeepSub-Micron)的制作工艺时，元件的尺寸逐渐缩小，对于存储器元件而言，也就是代表存储单元尺寸愈来愈小。另一方面，随着信息电子产品需要处理、存储的数据日益增加，在这些信息电子产品中所需的存储器容量也就愈来愈大。对于这种尺寸变小而存储器容量却需要增加的情形，如何制造尺寸缩小、高集成度，又能兼顾其品质的存储器元件是产业的一致目标。
非挥发性存储器元件由于具有使存入的数据在断电后也不会消失的优点，所以已成为个人电脑和电子设备所广泛采用的一种存储器元件。
一种现有的非挥发性存储器，由选择晶体管与浮置栅极晶体管所构成。由于只需要形成一层多晶硅，因此此种非挥发性存储器的制作工艺可以与互补式金属氧化物半导体晶体管的制作工艺整合在一起，而能够减少制造成本。
然而，在现有的非挥发性存储器中，一般是采用输入输出元件来作为选择晶体管，因此无法以低电力(lowpower)与高速(highspeed)的方式进行操作非挥发性存储器。
此外，若为了达成低电力与高速操作，而采用逻辑元件(coredevice)来作为选择晶体管，则在对非挥发性存储器进行程式化操作与抹除操作时，会对导致选择晶体管承受过大应力(stress)，而造成氧化层击穿(oxidebreakdown)的情况。
发明内容
本发明的目的在于提供一种非挥发性存储器，其可有效地降低选择晶体管所承受到的应力。
为达上述目的，本发明提出一种非挥发性存储器，包括基底、浮置栅极晶体管、选择晶体管与应力释放晶体管。浮置栅极晶体管、选择晶体管与应力释放晶体管设置于基底上且彼此串接。应力释放晶体管位于浮置栅极晶体管与选择晶体管之间。
依照本发明的一实施例所述，在非挥发性存储器中，浮置栅极晶体管、选择晶体管与应力释放晶体管例如是通过共用掺杂区而进行串接。
依照本发明的一实施例所述，在非挥发性存储器中，浮置栅极晶体管包括浮置栅极、第一掺杂区、第二掺杂区与第一介电层。浮置栅极设置于基底上。第一掺杂区与第二掺杂区分别设置于浮置栅极两侧的基底中。第一介电层设置于浮置栅极与基底之间。选择晶体管包括选择栅极、第三掺杂区、第四掺杂区与第二介电层。选择栅极设置于基底上。第三掺杂区与第四掺杂区分别设置于选择栅极两侧的基底中。第二介电层设置于选择栅极与基底之间。应力释放晶体管包括应力释放栅极、第二掺杂区、第三掺杂区与第三介电层。应力释放栅极设置于基底上。第二掺杂区位于浮置栅极与应力释放栅极之间，且第三掺杂区位于选择栅极与应力释放栅极之间。第三介电层设置于应力释放栅极与基底之间。
依照本发明的一实施例所述，在非挥发性存储器中，应力释放栅极下方的通道长度例如是小于输入输出元件(I/Odevice)的设计规则(designrule)的最小通道长度。
依照本发明的一实施例所述，在非挥发性存储器中，第一介电层的厚度例如是大于第二介电层的厚度。
依照本发明的一实施例所述，在非挥发性存储器中，第三介电层的厚度例如是大于第二介电层的厚度。
依照本发明的一实施例所述，在非挥发性存储器中，第二掺杂区与第三掺杂区例如是浮置掺杂区。
依照本发明的一实施例所述，在非挥发性存储器中，第一掺杂区至第四掺杂区例如是相同的导电型。
依照本发明的一实施例所述，在非挥发性存储器中，还可包括至少一第一阱区，设置于基底中。第一掺杂区至第四掺杂区位于第一阱区中。
依照本发明的一实施例所述，在非挥发性存储器中，第一掺杂区至第四掺杂区的导电型例如是不同于第一阱区的导电型。
依照本发明的一实施例所述，在非挥发性存储器中，还可包括第一电容器与第二电容器。第一电容器、第二电容器与浮置栅极晶体管分离设置且彼此耦接。
依照本发明的一实施例所述，在非挥发性存储器中，第一电容器、第二电容器与浮置栅极晶体管例如是通过共用浮置栅极而进行耦接。
依照本发明的一实施例所述，在非挥发性存储器中，第一电容器包括浮置栅极、至少一第五掺杂区与第四介电层。第五掺杂区设置于浮置栅极两侧的基底中。第四介电层设置于浮置栅极与基底之间。第二电容器包括浮置栅极、至少一第六掺杂区与第五介电层。第六掺杂区设置于浮置栅极两侧的基底中。第五介电层设置于浮置栅极与基底之间。
依照本发明的一实施例所述，在非挥发性存储器中，第四介电层的厚度与第五介电层的厚度例如是分别大于第二介电层的厚度。
依照本发明的一实施例所述，在非挥发性存储器中，还可包括第二阱区与第三阱区。第二阱区设置于基底中。第五掺杂区位于第二阱区中。第三阱区设置于基底中。第六掺杂区位于第三阱区中。
依照本发明的一实施例所述，在非挥发性存储器中，当第一阱区、第二阱区与第三阱区中的相邻两个同为第一导电型时，第一阱区、第二阱区与第三阱区中的同为第一导电型的相邻两个彼此之间例如是分离设置。
依照本发明的一实施例所述，在非挥发性存储器中，在第一阱区、第二阱区与第三阱区中的同为第一导电型的相邻两个之间还可包括具有第二导电型的第四阱区，其中第二导电型与第一导电型为不同导电型。
依照本发明的一实施例所述，在非挥发性存储器中，当第一阱区、第二阱区与第三阱区中的相邻两个为不同导电型时，第一阱区、第二阱区与第三阱区中的不同导电型的相邻两个例如是分离设置或彼此连接。
依照本发明的一实施例所述，在非挥发性存储器中，第二电容器中的浮置栅极的面积例如是大于浮置栅极晶体管中的浮置栅极的面积与第一电容器中的浮置栅极的面积。
依照本发明的一实施例所述，在非挥发性存储器中，浮置栅极晶体管中的浮置栅极的面积例如是大于第一电容器中的浮置栅极的面积。
基于上述，在本发明所提出的非挥发性存储器，由于在浮置栅极晶体管与选择晶体管之间具有应力释放晶体管，因此在对非挥发性存储器进行程式化操作与抹除操作时，可降低选择晶体管所承受到的应力。如此一来，即便是在采用逻辑元件作为选择晶体管来达成低电力与高速操作的情况下，也不会使得选择晶体管产生氧化层击穿的问题。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1为本发明一实施例的非挥发性存储器的上视图；
图2A为沿着图1中I-I’剖面线的剖视图；
图2B为沿着图1中II-II’剖面线的剖视图；
图2C为沿着图1中III-III’剖面线的剖视图；
图3为本发明另一实施例的非挥发性存储器的上视图。
符号说明
10、20：非挥发性存储器
100：基底
102：浮置栅极晶体管
104：选择晶体管
106：应力释放晶体管
108：浮置栅极
110、112、118、120、140、142、146、148、151、152：掺杂区
114、122、126、134、144、150：介电层
116：选择栅极
124：应力释放栅极
128、154、156、158：阱区
130、132、162、164、166：接触窗
136、136a、138、138a：电容器
160：隔离结构
具体实施方式
图1为本发明一实施例的非挥发性存储器的上视图。在图1中，为了清楚描述非挥发性存储器的结构，省略绘示隔离结构与介电层。图2A为沿着图1中I-I’剖面线的剖视图。图2B为沿着图1中II-II’剖面线的剖视图。图2C为沿着图1中III-III’剖面线的剖视图。
请同时参照图1与图2B，非挥发性存储器10包括基底100、浮置栅极晶体管102、选择晶体管104与应力释放晶体管106。浮置栅极晶体管102、选择晶体管104与应力释放晶体管106设置于基底100上且彼此串接。应力释放晶体管106位于浮置栅极晶体管102与选择晶体管104之间，因此可通过应力释放晶体管106来降低在对非挥发性存储器10进行操作时选择晶体管104所承受的应力。浮置栅极晶体管102、选择晶体管104与应力释放晶体管106例如是通过共用掺杂区而进行串接。
浮置栅极晶体管102包括浮置栅极108、掺杂区110、掺杂区112与介电层114。浮置栅极108设置于基底100上。在进行程式化操作时，电子会进入浮置栅极晶体管102中的浮置栅极108进行存储。浮置栅极108的材料例如是掺杂多晶硅等导体材料。浮置栅极108的形成方法例如是化学气相沉积法。
掺杂区110与掺杂区112分别设置于浮置栅极108两侧的基底100中。掺杂区110与掺杂区112例如是相同的导电型，分别可为N型掺杂区或P型掺杂区。掺杂区110与掺杂区112的形成方法例如是离子注入法。
介电层114设置于浮置栅极108与基底100之间。介电层114的材料例如是氧化硅。介电层114的形成方法例如是热氧化法或化学气相沉积法。
选择晶体管104包括选择栅极116、掺杂区118、掺杂区120与介电层122。选择栅极116设置于基底100上。选择栅极116的材料例如是掺杂多晶硅等导体材料。选择栅极116的形成方法例如是化学气相沉积法。
掺杂区118与掺杂区120分别设置于选择栅极116两侧的基底100中。掺杂区118与掺杂区120例如是相同的导电型，分别可为N型掺杂区或P型掺杂区。掺杂区118与掺杂区120的形成方法例如是离子注入法。此外，掺杂区110、112、118、120例如是相同的导电型。
介电层122设置于选择栅极116与基底100之间。介电层114的厚度例如是大于介电层122的厚度。介电层122的材料例如是氧化硅。介电层122的形成方法例如是热氧化法或化学气相沉积法。
应力释放晶体管106包括应力释放栅极124、掺杂区112、掺杂区118与介电层126，可用以释放传送到选择晶体管104的部分应力，而降低选择晶体管104所承受的应力。应力释放栅极124设置于基底100上。应力释放栅极124下方的通道长度例如是小于输入输出元件的设计规则的最小通道长度，而在掺杂区112与掺杂区118之间产生短通道效应，进而可使得应力释放晶体管106的临界电压(thresholdvoltage，Vt)小于一般输入输出元件的临界电压。在一实施例中，应力释放晶体管106的临界电压可为0。应力释放栅极124的材料例如是掺杂多晶硅等导体材料。应力释放栅极124的形成方法例如是化学气相沉积法。
掺杂区112位于浮置栅极108与应力释放栅极124之间，而使得应力释放晶体管106与浮置栅极晶体管102可共用掺杂区112。此外，掺杂区118位于选择栅极116与应力释放栅极124之间，而使得应力释放晶体管106与选择晶体管104可共用掺杂区118。掺杂区112与掺杂区118例如是浮置掺杂区。
介电层126设置于应力释放栅极124与基底100之间。介电层126的厚度例如是大于介电层122的厚度。介电层126的材料例如是氧化硅。介电层126的形成方法例如是热氧化法或化学气相沉积法。
非挥发性存储器10还可包括至少一阱区128，设置于基底100中。掺杂区110、112、118、120位于阱区128中。阱区128可为N型阱区或P型阱区。阱区128的形成方法例如是离子注入法。掺杂区110、112、118、120的导电型例如是不同于阱区128的导电型。在此实施例中，非挥发性存储器10是以具有一个阱区128为例来进行说明，亦即浮置栅极晶体管102、选择晶体管104与应力释放晶体管106均位于同一个阱区128中，但本发明并不限于此。在其他实施例中，由于逻辑元件的阱区与输入输出元件的阱区也可分开制作，因此当采用逻辑元件作为选择晶体管104，且采用输入输出元件作为浮置栅极晶体管102与应力释放晶体管106时，选择晶体管104的阱区与浮置栅极晶体管102与应力释放晶体管106的阱区也可为不同阱区。
非挥发性存储器10还可包括接触窗130与接触窗132，设置于介电层134中，且分别连接至掺杂区110与掺杂区120，而分别将掺杂区110与掺杂区120耦接至外部电源或外部电路。接触窗130与接触窗132的材料例如是钨、铜或铝。接触窗130与接触窗132的形成方法例如是物理气相沉积法。
请同时参照图1、图2A至图2C，非挥发性存储器10还可包括电容器136与电容器138。电容器136、电容器138与浮置栅极晶体管102分离设置且彼此耦接。电容器136、电容器138与浮置栅极晶体管102例如是通过共用浮置栅极108而进行耦接。电容器138中的浮置栅极108的面积例如是大于浮置栅极晶体管102中的浮置栅极108的面积与电容器136中的浮置栅极108的面积。浮置栅极晶体管102中的浮置栅极108的面积例如是大于电容器136中的浮置栅极108的面积。
在此实施例中，电容器136与电容器138是以位于浮置栅极晶体管102的两侧为例来进行说明，然而本发明并不以此为限，只要电容器136、电容器138与浮置栅极晶体管102彼此耦接即属于本发明所保护的范围。举例来说，也可采用将浮置栅极晶体管102与电容器136设置于电容器138的两侧的配置方式。
电容器136包括浮置栅极108、掺杂区140、掺杂区142与介电层144。电容器136中的浮置栅极108可作为抹除栅极(erasegate)使用。在进行抹除操作时，电子可从电容器136中的浮置栅极108移出。
掺杂区140与掺杂区142设置于浮置栅极108两侧的基底100中。掺杂区140与掺杂区142可为相同或不同的导电型，分别可为N型掺杂区或P型掺杂区。掺杂区140与掺杂区142的形成方法例如是离子注入法。
介电层144设置于浮置栅极108与基底100之间。介电层144的厚度例如是大于介电层122的厚度。介电层144的材料例如是氧化硅。介电层144的形成方法例如是热氧化法或化学气相沉积法。
电容器138包括浮置栅极108、掺杂区146与介电层150。电容器138中的浮置栅极108可作为耦合栅极(couplinggate)使用。在对非挥发性存储器10进行操作时，电容器138中的浮置栅极108可用以提供正确的电压。
掺杂区146设置于浮置栅极108两侧的基底100中。在此实施例中，掺杂区146围绕电容器138的浮置栅极108，而位于浮置栅极108两侧。掺杂区146可为N型掺杂区或P型掺杂区。
介电层150设置于浮置栅极108与基底100之间。介电层150的厚度例如是大于介电层122的厚度。介电层150的材料例如是氧化硅。介电层150的形成方法例如是热氧化法或化学气相沉积法。
非挥发性存储器10还可包括阱区154与阱区156。阱区154设置于基底100中。掺杂区140与掺杂区142位于阱区154中。阱区156设置于基底100中。掺杂区146位于阱区156中。阱区154与阱区156分别可为N型阱区或P型阱区。阱区154与阱区156的形成方法例如是离子注入法。
当阱区128、阱区154与阱区156中的相邻两个同为第一导电型时，阱区128、阱区154与阱区156中的同为第一导电型的相邻两个彼此之间例如是分离设置。此外，非挥发性存储器10在阱区128、阱区154与阱区156中的同为第一导电型的相邻两个之间还可包括具有第二导电型的阱区158，其中第二导电型与第一导电型为不同导电型。当阱区128、阱区154与阱区156中的相邻两个为不同导电型时，阱区128、阱区154与阱区156中的不同导电型的相邻两个可为分离设置或彼此连接。在此实施例中，阱区128、阱区154与阱区156是以相同导电型为例来进行说明。
非挥发性存储器10还可包括隔离结构160。隔离结构160可设置于阱区128、阱区154与阱区156外部的基底100中。隔离结构160例如是浅沟渠隔离结构。隔离结构160的材料例如是氧化硅。
非挥发性存储器10还可包括接触窗162、接触窗164与接触窗166，设置于介电层134中，且分别连接至掺杂区140、掺杂区142与掺杂区146，而分别将掺杂区140、掺杂区142与掺杂区146耦接至外部电源或外部电路。接触窗162、接触窗164与接触窗166的材料例如是钨、铜或铝。接触窗162、接触窗164与接触窗166形成方法例如是物理气相沉积法。
图3为本发明另一实施例的非挥发性存储器的上视图。
请同时参照图1与图3，图3的非挥发性存储器20与图1的非挥发性存储器10的差异如下。非挥发性存储器10的电容器136包括两个掺杂区(140、142)，然而非挥发性存储器20的电容器136a仅具有设置于基底100中的单一个掺杂区148，且电容器136a的浮置栅极108的一端位于掺杂区148中。掺杂区148围绕电容器136a的浮置栅极108，而位于浮置栅极108两侧。此外，非挥发性存储器10的电容器138包括单一个掺杂区146，然而非挥发性存储器20的电容器138a包括掺杂区151、152。掺杂区151、152设置于电容器138a的浮置栅极108两侧的基底100中。在非挥发性存储器20与非挥发性存储器10中相同的构件使用相同的标号表示，故于此不再赘述。
由上述实施例可知，在此技术领域具有通常知识者可依照产品设计需求而调整电容器136、138、136a、138a的掺杂区的数量与型态。举例来说，可将非挥发性存储器10中具有两个掺杂区(140、142)的电容器136的设计变更为如同非挥发性存储器20中具有单一个掺杂区(148)的电容器136a的设计。此外，也可将非挥发性存储器20中具有单一个掺杂区(148)的电容器136a的设计变更为如同非挥发性存储器10中具有两个掺杂区(140、142)的电容器136的设计。
综上所述，在非挥发性存储器10中，由于在浮置栅极晶体管102与选择晶体管104之间具有应力释放晶体管106，因此在对非挥发性存储器10进行程式化操作与抹除操作时，可降低选择晶体管104所承受到的应力。如此一来，即便是在采用逻辑元件作为选择晶体管104来达成低电力与高速操作的情况下，也不会使得选择晶体管104产生氧化层击穿的问题。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种非挥发性存储器，包括：
基底；以及
浮置栅极晶体管、选择晶体管与应力释放晶体管，设置于所述基底上且彼此串接，其中所述应力释放晶体管位于所述浮置栅极晶体管与所述选择晶体管之间。
2.根据权利要求1所述的非挥发性存储器，其中所述浮置栅极晶体管、所述选择晶体管与所述应力释放晶体管通过共用掺杂区而进行串接。
3.根据权利要求1所述的非挥发性存储器，其中，
所述浮置栅极晶体管包括：
浮置栅极，设置于所述基底上；
第一掺杂区与第二掺杂区，分别设置于所述浮置栅极两侧的所述基底中；以及
第一介电层，设置于所述浮置栅极与所述基底之间；
所述选择晶体管包括：
选择栅极，设置于所述基底上；
第三掺杂区与第四掺杂区，分别设置于所述选择栅极两侧的所述基底中；以及
第二介电层，设置于所述选择栅极与所述基底之间；
所述应力释放晶体管包括：
应力释放栅极，设置于所述基底上；
所述第二掺杂区与所述第三掺杂区，其中所述第二掺杂区位于所述浮置栅极与所述应力释放栅极之间，且所述第三掺杂区位于所述选择栅极与所述应力释放栅极之间；以及
第三介电层，设置于所述应力释放栅极与所述基底之间。
4.根据权利要求3所述的非挥发性存储器，其中所述应力释放栅极下方的通道长度小于输入输出元件的设计规则的最小通道长度。
5.根据权利要求3所述的非挥发性存储器，其中所述第一介电层的厚度大于所述第二介电层的厚度。
6.根据权利要求3所述的非挥发性存储器，其中所述第三介电层的厚度大于所述第二介电层的厚度。
7.根据权利要求3所述的非挥发性存储器，其中所述第二掺杂区与所述第三掺杂区为浮置掺杂区。
8.根据权利要求3所述的非挥发性存储器，其中所述第一掺杂区至第四掺杂区为相同的导电型。
9.根据权利要求3所述的非挥发性存储器，还包括至少一第一阱区，设置于所述基底中，其中所述第一掺杂区至第四掺杂区位于所述至少一第一阱区中。
10.根据权利要求9所述的非挥发性存储器，其中所述第一掺杂区至第四掺杂区的导电型不同于所述至少一第一阱区的导电型。
11.根据权利要求9所述的非挥发性存储器，还包括第一电容器与第二电容器，其中所述第一电容器、所述第二电容器与所述浮置栅极晶体管分离设置且彼此耦接。
12.根据权利要求11所述的非挥发性存储器，其中所述第一电容器、所述第二电容器与所述浮置栅极晶体管通过共用所述浮置栅极而进行耦接。
13.根据权利要求11所述的非挥发性存储器，其中，
所述第一电容器包括：
所述浮置栅极；
至少一第五掺杂区，设置于所述浮置栅极两侧的所述基底中；以及
第四介电层，设置于所述浮置栅极与所述基底之间，
所述第二电容器包括：
所述浮置栅极；
至少一第六掺杂区，设置于所述浮置栅极两侧的所述基底中；以及
第五介电层，设置于所述浮置栅极与所述基底之间。
14.根据权利要求13所述的非挥发性存储器，其中所述第四介电层的厚度与所述第五介电层的厚度分别大于所述第二介电层的厚度。
15.根据权利要求13所述的非挥发性存储器，还包括：
第二阱区，设置于所述基底中，其中所述至少一第五掺杂区位于所述第二阱区中；以及
第三阱区，设置于所述基底中，其中所述至少一第六掺杂区位于所述第三阱区中。
16.根据权利要求15所述的非挥发性存储器，其中当所述至少一第一阱区、所述第二阱区与所述第三阱区中的相邻两个同为第一导电型时，所述至少一第一阱区、所述第二阱区与所述第三阱区中的同为所述第一导电型的相邻两个彼此之间分离设置。
17.根据权利要求16所述的非挥发性存储器，在所述至少一第一阱区、所述第二阱区与所述第三阱区中的同为所述第一导电型的相邻两个之间还包括具有第二导电型的第四阱区，其中所述第二导电型与所述第一导电型为不同导电型。
18.根据权利要求15所述的非挥发性存储器，其中当所述至少一第一阱区、所述第二阱区与所述第三阱区中的相邻两个为不同导电型时，所述至少一第一阱区、所述第二阱区与所述第三阱区中的不同导电型的相邻两个分离设置或彼此连接。
19.根据权利要求13所述的非挥发性存储器，其中所述第二电容器中的所述浮置栅极的面积大于所述浮置栅极晶体管中的所述浮置栅极的面积与所述第一电容器中的所述浮置栅极的面积。
20.根据权利要求13所述的非挥发性存储器，其中所述浮置栅极晶体管中的所述浮置栅极的面积大于所述第一电容器中的所述浮置栅极的面积。
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