CN105514112A - 一次可编程非挥发性存储器 - Google Patents

一次可编程非挥发性存储器 Download PDF

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CN105514112A
CN105514112A CN201510621185.2A CN201510621185A CN105514112A CN 105514112 A CN105514112 A CN 105514112A CN 201510621185 A CN201510621185 A CN 201510621185A CN 105514112 A CN105514112 A CN 105514112A
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volatile memory
programmable non
conductor layer
layer
connector
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徐德训
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eMemory Technology Inc
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eMemory Technology Inc
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Abstract

本发明公开一种一次可编程非挥发性存储器，包括基底、开关元件与熔丝结构。开关元件设置于基底上。熔丝结构包括导体层、间隙壁与插塞。导体层耦接至开关元件的端子。间隙壁设置于导体层的侧壁上。插塞设置于导体层上，且覆盖间隙壁。插塞与导体层的上表面的重叠部分的重叠面积小于插塞的上视面积。所述可编程非挥发性存储器可有效地降低烧断熔丝结构所需要的电流。

Description

一次可编程非挥发性存储器
技术领域
本发明涉及一种存储器，且特别是涉及一种一次可编程非挥发性存储器(onetimeprogrammablenon-volatilememory，OTPnon-volatilememory)。
背景技术
非挥发性存储器元件由于具有使存入的数据在断电后也不会消失的优点，所以已成为个人电脑和电子设备所广泛采用的一种存储器元件。
一般而言，非挥发性存储器可以区分为只读存储器(readonlymemory，ROM)、一次可编程存储器(OTPmemory)以及可重复读写存储器。
近年来在半导体集成电路装置中，一次可编程存储器成为不可欠缺的元件。一次可编程存储器可广泛地用在动态随机存取存储器(dynamicrandomaccessnemory，DRAM)或静态随机存取存储器(staticrandomaccessmemory，SRAM)的大容量的存储器中的备用(redundant)用途，模拟电路的校正(calibrating)用途或暗键等的码储存用途以及制造过程的经历等之类的管理用的资讯存储用的芯片辨认(ID)用途等。
一次可编程存储器可依使用者的需要，可利用电流将其内部的熔丝烧断(burnout)以写入所需的数据及程序。然而，如何有效地降低烧断熔丝所需要的电流为目前业界努力的目标。
发明内容
本发明的目的在于提供一种一次可编程非挥发性存储器，其可有效地降低烧断熔丝结构所需要的电流。
为达上述目的，本发明提出一种一次可编程非挥发性存储器，包括基底、开关元件与熔丝结构。开关元件设置于基底上。熔丝结构包括导体层、间隙壁与插塞。导体层耦接至开关元件的端子。间隙壁设置于导体层的侧壁上。插塞设置于导体层上，且覆盖间隙壁。插塞与导体层的上表面的重叠部分的重叠面积小于插塞的上视面积。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，开关元件例如是晶体管或二极管。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，晶体管例如是金属氧化物半场效晶体管(metaloxidesemiconductorfieldeffecttransistor，MOSFET)。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，金属氧化物半场效晶体管包括栅极、第一掺杂区、第二掺杂区与闸介电层。栅极设置于基底上。第一掺杂区与第二掺杂区分别设置于栅极两侧的基底中。第一掺杂区作为耦接至导体层的端子。闸介电层设置于栅极与基底之间。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，导体层与栅极例如是源自于同一层半导体材料层。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，导体层例如是通过内连线结构耦接到第一掺杂区。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，二极管例如是PN接面二极管或PIN(P-intrinsic-N)二极管。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，二极管包括P型半导体层与N型半导体层。N型半导体层设置于P型半导体层的一侧，且作为耦接至导体层的端子。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，导体层与N型半导体层例如是源自于同一层半导体材料层。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，还可包括本质层(intrinsiclayer)。本质层设置于P型半导体层与N型半导体层之间。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，本质层的材料例如是多晶硅。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，导体层例如是直接连接于N型半导体层。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，插塞可完全覆盖或部分覆盖间隙壁。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，重叠部分的导体层的宽度例如是小于插塞的宽度。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，重叠部分的导体层的宽度例如是符合导体层设计规则(designrule)的最小宽度。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，插塞的宽度例如是符合插塞设计规则的最小宽度。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，导体层的材料例如是掺杂多晶硅。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，其中插塞例如是接触窗插塞(contactplug)或介层窗插塞(viaplug)。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，其中插塞的材料例如是钨、铜、铝、金、银或其合金。
依照本发明的一实施例所述，在一次可编程非挥发性存储器中，其中还可包括隔离结构。隔离结构设置于基底中。导体层位于隔离结构上。
基于上述，在本所发明所提出的一次可编程非挥发性存储器中，由于插塞与导体层的上表面的重叠部分的重叠面积小于插塞的上视面积，所以在进行存储器的写入操作时，电流会集中在插塞与导体层的上表面的重叠部分，因此使用较小的电流即可将熔丝结构烧断，进而可有效地降低烧断熔丝结构所需要的电流。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1为本发明一实施例的一次可编程非挥发性存储器的上视图；
图2A为沿着图1中的I-I’剖面线的剖视图；
图2B为沿着图1中的II-II’剖面线的剖视图；
图3为本发明另一实施例的一次可编程非挥发性存储器的上视图；
图4为沿着图3中的III-III’剖面线的剖视图。
符号说明
10、20：一次可编程非挥发性存储器
100、200：基底
102、202：开关元件
104、204：熔丝结构
106：栅极
107、113、220：介电层
108、110：掺杂区
109、120、124、128、218：插塞
111、126、130：导线
112：栅介电层
114、118、212、216：间隙壁
116、214：导体层
122：内连线结构
132、222：隔离结构
206：P型半导体层
208：N型半导体层
210：本质层
R1、R2：重叠部分
W1、W2、W3、W4：宽度
具体实施方式
图1为本发明一实施例的一次可编程非挥发性存储器的上视图。在图1中，为了清楚描述一次可编程非挥发性存储器的结构，省略绘示隔离结构与介电层。图2A为沿着图1中的I-I’剖面线的剖视图。图2B为沿着图1中的II-II’剖面线的剖视图。
请同时参照图1、图2A与图2B，一次可编程非挥发性存储器10包括基底100、开关元件102与熔丝结构104。基底100例如是硅基底。
开关元件102设置于基底100上。开关元件102例如是晶体管或二极管。晶体管例如是金属氧化物半场效晶体管。二极管例如是PN接面二极管或PIN二极管。
在此实施例中，开关元件102是以金属氧化物半场效晶体管为例来进行说明，但本发明并不以此为限，只要具有开关功能的电子元件均属于本发明所要保护的范围。开关元件102包括栅极106、掺杂区108、掺杂区110与栅介电层112。栅极106设置于基底100上。栅极106的材料例如是掺杂多晶硅。掺杂区108与掺杂区110分别设置于栅极106两侧的基底100中，分别可作为源极与漏极使用。掺杂区108可通过位于介电层107中的插塞109与导线111而连接至外部电源或外部电路。介电层107的材料例如是氧化硅。插塞109的材料例如是钨、铜、铝、金、银或其合金。导线111的材料例如是铜、铝或钨。栅介电层112设置于栅极106与基底100之间。栅介电层112的材料例如是氧化硅。此外，开关元件102还可包括间隙壁114。间隙壁114设置于栅极106的侧壁上。间隙壁114的材料例如是氧化硅、氮化硅、介电层或复合介电层。
熔丝结构104包括导体层116、间隙壁118与插塞120。导体层116耦接至开关元件102的端子。在此实施例中，导体层116是以具有两端宽且中央窄的哑铃状为例来进行说明，但本发明并不以此为限。在其他实施例中，导体层116也可为具有均匀的宽度的矩形。导体层116与栅极106例如是源自于同一层半导体材料层。导体层116的材料例如是掺杂多晶硅。
在此实施例中，是以开关元件102的掺杂区110作为耦接至导体层116的端子为例来进行说明，亦即导体层116耦接至开关元件102的掺杂区110。导体层116例如是通过内连线结构122耦接到掺杂区110。举例来说，内连线结构122位于介电层107中，且可包括依序连接的插塞124、导线126与插塞128。如此一来，导体层116可通过插塞124、导线126与插塞128而耦接至掺杂区110。插塞124与插塞128的材料分别例如是钨、铜、铝、金、银或其合金。导线126的材料例如是铜、铝或钨。
间隙壁118设置于导体层116的侧壁上。间隙壁118与间隙壁114例如是源自于同一层间隙壁材料层。间隙壁118的材料例如是氧化硅、氮化硅、介电层或复合介电层。
插塞120设置于导体层116上，且覆盖间隙壁118。插塞120例如是位于介电层107中。插塞120与导体层116的上表面的重叠部分R1的重叠面积小于插塞120的上视面积。由此，在进行存储器的写入操作时，电流会集中在插塞120与导体层116的上表面的重叠部分R1，因此使用较小的电流即可将熔丝结构104烧断，可有效地降低烧断熔丝结构104所需要的电流。此外，插塞120可完全覆盖或部分覆盖间隙壁118。在此实施例中，插塞120是以完全覆盖间隙壁118为例来进行说明(请参照图2B)。插塞120可通过位于介电层107中的导线130而连接至外部电源或外部电路。导线130的材料例如是铜、铝或钨。
另外，重叠部分R1的导体层116的宽度W1例如是小于插塞120的宽度W2。插塞120例如是接触窗插塞或介层窗插塞。插塞120的材料例如是钨、铜、铝、金、银或其合金。
此外，重叠部分R1的导体层116的宽度W1例如是符合导体层116设计规则(designrule)的最小宽度，且插塞120的宽度W2例如是符合插塞120设计规则的最小宽度，因此可通过将线宽设为最小宽度而更进一步地降低烧断熔丝结构104所需要的电流。
另一方面，在其他实施例中，重叠部分R1的导体层116的宽度W1例如是比符合导体层116设计规则的最小宽度小10％。或者，插塞120的宽度W2例如是比符合插塞120设计规则的最小宽度小10％。换言之，导体层116的宽度W1与插塞120的宽度W2可设为小于设计规则的最小宽度。因此，更进一步地降低烧断熔丝结构104所需要的电流。
另外，一次可编程非挥发性存储器10还可包括隔离结构132。隔离结构132设置于基底100中，且导体层116例如是位于隔离结构132上方的介电层113上。隔离结构132例如是浅沟槽隔离结构。隔离结构132的材料例如是氧化硅。介电层113与栅介电层112例如是源自于同一层介电材料层。介电层113的材料例如是氧化硅。
基于上述实施例可知，在一次可编程非挥发性存储器10中，将插塞120与导体层116的上表面的重叠部分R1的重叠面积设为小于插塞120的上视面积，因此使用较小的电流即可将熔丝结构104烧断，可有效地降低烧断熔丝结构104所需要的电流。
图3为本发明另一实施例的一次可编程非挥发性存储器的上视图。在图3中，为了清楚描述一次可编程非挥发性存储器的结构，省略绘示隔离结构与介电层。图4为沿着图3中的III-III’剖面线的剖视图。
请同时参照图3与图4，一次可编程非挥发性存储器20包括基底200、开关元件202与熔丝结构204。基底200例如是硅基底。
在此实施例中，开关元件202是以二极管为例来进行说明，但本发明并不以此为限，只要具有开关功能的电子元件均属于本发明所要保护的范围。开关元件202包括P型半导体层206与N型半导体层208。P型半导体层206设置于基底200上。P型半导体层206的材料例如是掺杂多晶硅。N型半导体层208设置于P型半导体层206的一侧的基底200上。N型半导体层208的材料例如是掺杂多晶硅。此外，开关元件202还可包括本质层210。本质层210设置于P型半导体层206与N型半导体层208之间。本质层210的材料例如是多晶硅。另外，开关元件202还可包括间隙壁212。间隙壁212可设置于P型半导体层206、N型半导体层208与本质层210的侧壁上。间隙壁212的材料例如是氧化硅、氮化硅、介电层或复合介电层。
熔丝结构204包括导体层214、间隙壁216与插塞218。导体层214耦接至开关元件202的端子。在此实施例中，导体层214是以具有一端较宽的槌状为例来进行说明，但本发明并不以此为限。在其他实施例中，导体层214也可为具有均匀的宽度的矩形。导体层214与N型半导体层208例如是源自于同一层半导体材料层。导体层214的材料例如是掺杂多晶硅。
在此实施例中，是以开关元件202的N型半导体层208作为耦接至导体层214的端子为例来进行说明，亦即导体层214耦接至开关元件202的N型半导体层208。导体层214例如是直接连接于N型半导体层208。
间隙壁216设置于导体层214的侧壁上。间隙壁216与间隙壁212例如是源自于同一层间隙壁材料层。间隙壁216的材料例如是氧化硅、氮化硅、介电层或复合介电层。
插塞218设置于导体层214上，且覆盖间隙壁216。插塞218例如是位于介电层220中。介电层220的材料例如是氧化硅。插塞218与导体层214的上表面的重叠部分R2的重叠面积小于插塞218的上视面积。由此，在进行存储器的写入操作时，电流会集中在插塞218与导体层214的上表面的重叠部分R2，因此使用较小的电流即可将熔丝结构204烧断，可有效地降低烧断熔丝结构204所需要的电流。此外，插塞218可完全覆盖或部分覆盖间隙壁216。在此实施例中，插塞218是以完全覆盖间隙壁216为例来进行说明(请参照图4)。
重叠部分R2的导体层214的宽度W3例如是小于插塞218的宽度W4。插塞218例如是接触窗插塞或介层窗插塞。插塞218的材料例如是钨、铜、铝、金、银其合金。
此外，重叠部分R2的导体层214的宽度W3例如是符合导体层214设计规则(designrule)的最小宽度，且插塞218的宽度W4例如是符合插塞218设计规则的最小宽度，因此可通过将线宽设为最小宽度而更进一步地降低烧断熔丝结构204所需要的电流。
另一方面，在其他实施例中，重叠部分R2的导体层214的宽度W3例如是比符合导体层214设计规则的最小宽度小10％。或者，插塞218的宽度W4例如是比符合插塞218设计规则的最小宽度小10％。换言之，导体层214的宽度W3与插塞218的宽度W4可设为小于设计规则的最小宽度。因此，更进一步地降低烧断熔丝结构204所需要的电流。
另外，一次可编程非挥发性存储器20还可包括隔离结构222。隔离结构222设置于基底200中，且导体层214位于隔离结构222上。隔离结构222例如是浅沟槽隔离结构。隔离结构222的材料例如是氧化硅。
基于上述实施例可知，在一次可编程非挥发性存储器20中，将插塞218与导体层214的上表面的重叠部分R2的重叠面积设为小于插塞218的上视面积，因此使用较小的电流即可将熔丝结构204烧断，可有效地降低烧断熔丝结构204所需要的电流。
综上所述，上述实施例所提出的一次可编程非挥发性存储器可通过将插塞与导体层的上表面的重叠部分的重叠面积设小于插塞的上视面积，而可有效地降低烧断熔丝结构所需要的电流。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种一次可编程非挥发性存储器，包括：
基底；
开关元件，设置于所述基底上；以及
熔丝结构，包括：
导体层，耦接至所述开关元件的端子；
间隙壁，设置于所述导体层的侧壁上；以及
插塞，设置于所述导体层上，且覆盖所述间隙壁，其中所述插塞与所述导体层的上表面的重叠部分的重叠面积小于所述插塞的上视面积。
2.根据权利要求1所述的一次可编程非挥发性存储器，其中所述开关元件包括晶体管或二极管。
3.根据权利要求2所述的一次可编程非挥发性存储器，其中所述晶体管包括金属氧化物半场效晶体管。
4.根据权利要求3所述的一次可编程非挥发性存储器，其中金属氧化物半场效晶体管包括：
栅极，设置于所述基底上；
第一掺杂区与第二掺杂区，分别设置于所述栅极两侧的所述基底中，其中所述第一掺杂区作为耦接至所述导体层的所述端子；以及
栅介电层，设置于所述栅极与所述基底之间。
5.根据权利要求4所述的一次可编程非挥发性存储器，其中所述导体层与所述栅极源自于同一层半导体材料层。
6.根据权利要求4所述的一次可编程非挥发性存储器，其中所述导体层通过内连线结构耦接到所述第一掺杂区。
7.根据权利要求2所述的一次可编程非挥发性存储器，其中所述二极管包括PN接面二极管或PIN二极管。
8.根据权利要求2所述的一次可编程非挥发性存储器，其中所述二极管包括：
P型半导体层；以及
N型半导体层，设置于所述P型半导体层的一侧，且作为耦接至所述导体层的所述端子。
9.根据权利要求8所述的一次可编程非挥发性存储器，其中所述导体层与所述N型半导体层源自于同一层半导体材料层。
10.根据权利要求8所述的一次可编程非挥发性存储器，还包括本质层，设置于所述P型半导体层与所述N型半导体层之间。
11.根据权利要求10所述的一次可编程非挥发性存储器，其中所述本质层的材料包括多晶硅。
12.根据权利要求8所述的一次可编程非挥发性存储器，其中所述导体层直接连接于所述N型半导体层。
13.根据权利要求1所述的一次可编程非挥发性存储器，其中所述插塞完全覆盖或部分覆盖所述间隙壁。
14.根据权利要求1所述的一次可编程非挥发性存储器，其中所述重叠部分的所述导体层的宽度小于所述插塞的宽度。
15.根据权利要求14所述的一次可编程非挥发性存储器，其中所述重叠部分的所述导体层的宽度为符合导体层设计规则的最小宽度。
16.根据权利要求14所述的一次可编程非挥发性存储器，其中所述插塞的宽度为符合插塞设计规则的最小宽度。
17.根据权利要求1所述的一次可编程非挥发性存储器，其中所述导体层的材料包括掺杂多晶硅。
18.根据权利要求1所述的一次可编程非挥发性存储器，其中所述插塞包括接触窗插塞或介层窗插塞。
19.根据权利要求1所述的一次可编程非挥发性存储器，其中所述插塞的材料包括钨、铜、铝、金、银、或其合金。
20.根据权利要求1所述的一次可编程非挥发性存储器，还包括隔离结构，设置于所述基底中，其中所述导体层位于所述隔离结构上。
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