TWI575715B - 一次可程式非揮發性記憶體 - Google Patents

一次可程式非揮發性記憶體 Download PDF

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TWI575715B
TWI575715B TW104130070A TW104130070A TWI575715B TW I575715 B TWI575715 B TW I575715B TW 104130070 A TW104130070 A TW 104130070A TW 104130070 A TW104130070 A TW 104130070A TW I575715 B TWI575715 B TW I575715B
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volatile memory
conductor layer
plug
programmable non
time programmable
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TW104130070A
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TW201614812A (en
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徐德訓
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力旺電子股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
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    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
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    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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Description

一次可程式非揮發性記憶體
本發明是有關於一種記憶體，且特別是有關於一種一次可程式非揮發性記憶體(one time programmable non-volatile memory，OTP non-volatile memory)。
非揮發性記憶體元件由於具有使存入之資料在斷電後也不會消失之優點，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體元件。
一般而言，非揮發性記憶體可以區分為唯讀記憶體(read only memory，ROM)、一次可程式記憶體(OTP memory)以及可重覆讀寫記憶體。
近年來在半導體積體電路裝置中，一次可程式記憶體成為不可欠缺的元件。一次可程式記憶體可廣泛地用在動態隨機存取記憶體(dynamic random access nemory，DRAM)或靜態隨機存取記憶體(static random access memory，SRAM)之大容量的記憶體中的備用(redundant)用途，類比電路的校正(calibrating)用途或暗鍵等的碼儲存用途以及製造過程的經歴等之類的管理用的資訊記憶用之晶片辨認(ID)用途等。
一次可程式記憶體可依使用者的需要，可利用電流將其內部的熔絲燒斷(burn out)以寫入所需的資料及程式。然而，如何有效地降低燒斷熔絲所需要的電流為目前業界努力的目標。
本發明提供一種一次可程式非揮發性記憶體，其可有效地降低燒斷熔絲結構所需要的電流。
本發明提出一種一次可程式非揮發性記憶體，包括基底、開關元件與熔絲結構。開關元件設置於基底上。熔絲結構包括導體層、間隙壁與插塞。導體層耦接至開關元件的端子。間隙壁設置於導體層的側壁上。插塞設置於導體層上，且覆蓋間隙壁。插塞與導體層的上表面的重疊部分的重疊面積小於插塞的上視面積。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，開關元件例如是電晶體或二極體。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，電晶體例如是金氧半場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，金氧半場效電晶體包括閘極、第一摻雜區、第二摻雜區與閘介電層。閘極設置於基底上。第一摻雜區與第二摻雜區分別設置於閘極兩側的基底中。第一摻雜區作為耦接至導體層的端子。閘介電層設置於閘極與基底之間。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，導體層與閘極例如是源自於同一層半導體材料層。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，導體層例如是藉由內連線結構耦接到第一摻雜區。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，二極體例如是PN接面二極體或PIN(P-intrinsic-N)二極體。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，二極體包括P型半導體層與N型半導體層。N型半導體層設置於P型半導體層的一側，且作為耦接至導體層的端子。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，導體層與N型半導體層例如是源自於同一層半導體材料層。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，更可包括本質層(intrinsic layer)。本質層設置於P型半導體層與N型半導體層之間。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，本質層的材料例如是多晶矽。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，導體層例如是直接連接於N型半導體層。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，插塞可完全覆蓋或部分覆蓋間隙壁。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，重疊部分的導體層的寬度例如是小於插塞的寬度。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，重疊部分的導體層的寬度例如是符合導體層設計規則(design rule)的最小寬度。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，插塞的寬度例如是符合插塞設計規則的最小寬度。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，導體層的材料例如是摻雜多晶矽。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，其中插塞例如是接觸窗插塞(contact plug)或介層窗插塞(via plug)。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，其中插塞的材料例如是鎢、銅、鋁、金、銀或其合金。
依照本發明的一實施例所述，在一次可程式非揮發性記憶體中，其中更可包括隔離結構。隔離結構設置於基底中。導體層位於隔離結構上。
基於上述，在本所發明所提出的一次可程式非揮發性記憶體中，由於插塞與導體層的上表面的重疊部分的重疊面積小於插塞的上視面積，所以在進行記憶體的寫入操作時，電流會集中在插塞與導體層的上表面的重疊部分，因此使用較小的電流即可將熔絲結構燒斷，進而可有效地降低燒斷熔絲結構所需要的電流。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明一實施例的一次可程式非揮發性記憶體的上視圖。在圖1中，為了清楚描述一次可程式非揮發性記憶體的結構，省略繪示隔離結構與介電層。圖2A為沿著圖1中的I-I’剖面線的剖面圖。圖2B為沿著圖1中的II-II’剖面線的剖面圖。
請同時參照圖1、圖2A與圖2B，一次可程式非揮發性記憶體10包括基底100、開關元件102與熔絲結構104。基底100例如是矽基底。
開關元件102設置於基底100上。開關元件102例如是電晶體或二極體。電晶體例如是金氧半場效電晶體。二極體例如是PN接面二極體或PIN二極體。
在此實施例中，開關元件102是以金氧半場效電晶體為例來進行說明，但本發明並不以此為限，只要具有開關功能的電子元件均屬於本發明所要保護的範圍。開關元件102包括閘極106、摻雜區108、摻雜區110與閘介電層112。閘極106設置於基底100上。閘極106的材料例如是摻雜多晶矽。摻雜區108與摻雜區110分別設置於閘極106兩側的基底100中，分別可作為源極與汲極使用。摻雜區108可藉由位於介電層107中的插塞109與導線111而連接至外部電源或外部電路。介電層107的材料例如是氧化矽。插塞109的材料例如是鎢、銅、鋁、金、銀或其合金。導線111的材料例如是銅、鋁或鎢。閘介電層112設置於閘極106與基底100之間。閘介電層112的材料例如是氧化矽。此外，開關元件102更可包括間隙壁114。間隙壁114設置於閘極106的側壁上。間隙壁114的材料例如是氧化矽、氮化矽、介電層或複合介電層。
熔絲結構104包括導體層116、間隙壁118與插塞120。導體層116耦接至開關元件102的端子。在此實施例中，導體層116是以具有兩端寬且中央窄的啞鈴狀為例來進行說明，但本發明並不以此為限。在其他實施例中，導體層116亦可為具有均勻的寬度的矩形。導體層116與閘極106例如是源自於同一層半導體材料層。導體層116的材料例如是摻雜多晶矽。
在此實施例中，是以開關元件102的摻雜區110作為耦接至導體層116的端子為例來進行說明，亦即導體層116耦接至開關元件102的摻雜區110。導體層116例如是藉由內連線結構122耦接到摻雜區110。舉例來說，內連線結構122位於介電層107中，且可包括依序連接的插塞124、導線126與插塞128。如此一來，導體層116可藉由插塞124、導線126與插塞128而耦接至摻雜區110。插塞124與插塞128的材料分別例如是鎢、銅、鋁、金、銀或其合金。導線126的材料例如是銅、鋁或鎢。
間隙壁118設置於導體層116的側壁上。間隙壁118與間隙壁114例如是源自於同一層間隙壁材料層。間隙壁118的材料例如是氧化矽、氮化矽、介電層或複合介電層。
插塞120設置於導體層116上，且覆蓋間隙壁118。插塞120例如是位於介電層107中。插塞120與導體層116的上表面的重疊部分R1的重疊面積小於插塞120的上視面積。藉此，在進行記憶體的寫入操作時，電流會集中在插塞120與導體層116的上表面的重疊部分R1，因此使用較小的電流即可將熔絲結構104燒斷，可有效地降低燒斷熔絲結構104所需要的電流。此外，插塞120可完全覆蓋或部分覆蓋間隙壁118。在此實施例中，插塞120是以完全覆蓋間隙壁118為例來進行說明(請參照圖2B)。插塞120可藉由位於介電層107中的導線130而連接至外部電源或外部電路。導線130的材料例如是銅、鋁或鎢。
另外，重疊部分R1的導體層116的寬度W1例如是小於插塞120的寬度W2。插塞120例如是接觸窗插塞或介層窗插塞。插塞120的材料例如是鎢、銅、鋁、金、銀或其合金。
此外，重疊部分R1的導體層116的寬度W1例如是符合導體層116設計規則(design rule)的最小寬度，且插塞120的寬度W2例如是符合插塞120設計規則的最小寬度，因此可藉由將線寬設為最小寬度而更進一步地降低燒斷熔絲結構104所需要的電流。
另一方面，在其他實施例中，重疊部分R1的導體層116的寬度W1例如是比符合導體層116設計規則的最小寬度小10%。或者，插塞120的寬度W2例如是比符合插塞120設計規則的最小寬度小10%。換言之，導體層116的寬度W1與插塞120的寬度W2可設為小於設計規則的最小寬度。因此，更進一步地降低燒斷熔絲結構104所需要的電流。
另外，一次可程式非揮發性記憶體10更可包括隔離結構132。隔離結構132設置於基底100中，且導體層116例如是位於隔離結構132上方的介電層113上。隔離結構132例如是淺溝渠隔離結構。隔離結構132的材料例如是氧化矽。介電層113與閘介電層112例如是源自於同一層介電材料層。介電層113的材料例如是氧化矽。
基於上述實施例可知，在一次可程式非揮發性記憶體10中，將插塞120與導體層116的上表面的重疊部分R1的重疊面積設為小於插塞120的上視面積，因此使用較小的電流即可將熔絲結構104燒斷，可有效地降低燒斷熔絲結構104所需要的電流。
圖3為本發明另一實施例的一次可程式非揮發性記憶體的上視圖。在圖3中，為了清楚描述一次可程式非揮發性記憶體的結構，省略繪示隔離結構與介電層。圖4為沿著圖3中的III-III’剖面線的剖面圖。
請同時參照圖3與圖4，一次可程式非揮發性記憶體20包括基底200、開關元件202與熔絲結構204。基底200例如是矽基底。
在此實施例中，開關元件202是以二極體為例來進行說明，但本發明並不以此為限，只要具有開關功能的電子元件均屬於本發明所要保護的範圍。開關元件202包括P型半導體層206與N型半導體層208。P型半導體層206設置於基底200上。P型半導體層206的材料例如是摻雜多晶矽。N型半導體層208設置於P型半導體層206的一側的基底200上。N型半導體層208的材料例如是摻雜多晶矽。此外，開關元件202更可包括本質層210。本質層210設置於P型半導體層206與N型半導體層208之間。本質層210的材料例如是多晶矽。另外，開關元件202更可包括間隙壁212。間隙壁212可設置於P型半導體層206、N型半導體層208與本質層210的側壁上。間隙壁212的材料例如是氧化矽、氮化矽、介電層或複合介電層。
熔絲結構204包括導體層214、間隙壁216與插塞218。導體層214耦接至開關元件202的端子。在此實施例中，導體層214是以具有一端較寬的槌狀為例來進行說明，但本發明並不以此為限。在其他實施例中，導體層214亦可為具有均勻的寬度的矩形。導體層214與N型半導體層208例如是源自於同一層半導體材料層。導體層214的材料例如是摻雜多晶矽。
在此實施例中，是以開關元件202的N型半導體層208作為耦接至導體層214的端子為例來進行說明，亦即導體層214耦接至開關元件202的N型半導體層208。導體層214例如是直接連接於N型半導體層208。
間隙壁216設置於導體層214的側壁上。間隙壁216與間隙壁212例如是源自於同一層間隙壁材料層。間隙壁216的材料例如是氧化矽、氮化矽、介電層或複合介電層。
插塞218設置於導體層214上，且覆蓋間隙壁216。插塞218例如是位於介電層220中。介電層220的材料例如是氧化矽。插塞218與導體層214的上表面的重疊部分R2的重疊面積小於插塞218的上視面積。藉此，在進行記憶體的寫入操作時，電流會集中在插塞218與導體層214的上表面的重疊部分R2，因此使用較小的電流即可將熔絲結構204燒斷，可有效地降低燒斷熔絲結構204所需要的電流。此外，插塞218可完全覆蓋或部分覆蓋間隙壁216。在此實施例中，插塞218是以完全覆蓋間隙壁216為例來進行說明(請參照圖4)。
重疊部分R2的導體層214的寬度W3例如是小於插塞218的寬度W4。插塞218例如是接觸窗插塞或介層窗插塞。插塞218的材料例如是鎢、銅、鋁、金、銀其合金。
此外，重疊部分R2的導體層214的寬度W3例如是符合導體層214設計規則(design rule)的最小寬度，且插塞218的寬度W4例如是符合插塞218設計規則的最小寬度，因此可藉由將線寬設為最小寬度而更進一步地降低燒斷熔絲結構204所需要的電流。
另一方面，在其他實施例中，重疊部分R2的導體層214的寬度W3例如是比符合導體層214設計規則的最小寬度小10%。或者，插塞218的寬度W4例如是比符合插塞218設計規則的最小寬度小10%。換言之，導體層214的寬度W3與插塞218的寬度W4可設為小於設計規則的最小寬度。因此，更進一步地降低燒斷熔絲結構204所需要的電流。
另外，一次可程式非揮發性記憶體20更可包括隔離結構222。隔離結構222設置於基底200中，且導體層214位於隔離結構222上。隔離結構222例如是淺溝渠隔離結構。隔離結構222的材料例如是氧化矽。
基於上述實施例可知，在一次可程式非揮發性記憶體20中，將插塞218與導體層214的上表面的重疊部分R2的重疊面積設為小於插塞218的上視面積，因此使用較小的電流即可將熔絲結構204燒斷，可有效地降低燒斷熔絲結構204所需要的電流。
綜上所述，上述實施例所提出的一次可程式非揮發性記憶體可藉由將插塞與導體層的上表面的重疊部分的重疊面積設小於插塞的上視面積，而可有效地降低燒斷熔絲結構所需要的電流。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20‧‧‧一次可程式非揮發性記憶體 100、200‧‧‧基底 102、202‧‧‧開關元件 104、204‧‧‧熔絲結構 106‧‧‧閘極 107、113、220‧‧‧介電層 108、110‧‧‧摻雜區 109、120、124、128、218‧‧‧插塞 111、126、130‧‧‧導線 112‧‧‧閘介電層 114、118、212、216‧‧‧間隙壁 116、214‧‧‧導體層 122‧‧‧內連線結構 132、222‧‧‧隔離結構 206‧‧‧P型半導體層 208‧‧‧N型半導體層 210‧‧‧本質層 R1、R2‧‧‧重疊部分 W1、W2、W3、W4‧‧‧寬度
圖1為本發明一實施例的一次可程式非揮發性記憶體的上視圖。 圖2A為沿著圖1中的I-I’剖面線的剖面圖。 圖2B為沿著圖1中的II-II’剖面線的剖面圖。 圖3為本發明另一實施例的一次可程式非揮發性記憶體的上視圖。 圖4為沿著圖3中的III-III’剖面線的剖面圖。
100‧‧‧基底
104‧‧‧熔絲結構
107、113‧‧‧介電層
116‧‧‧導體層
118‧‧‧間隙壁
120‧‧‧插塞
130‧‧‧導線
132‧‧‧隔離結構
R1‧‧‧重疊部分
W1、W2‧‧‧寬度

Claims (20)

  1. 一種一次可程式非揮發性記憶體，包括：一基底；一開關元件，設置於該基底上；以及一熔絲結構，包括：一導體層，耦接至該開關元件的一端子；一間隙壁，設置於該導體層的側壁上；以及一插塞，設置於該導體層上，且覆蓋該間隙壁，其中該插塞與該導體層的上表面的一重疊部分的一重疊面積小於該插塞的上視面積，且該重疊部分的該導體層的寬度小於該插塞的寬度。
  2. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該開關元件包括一電晶體或一二極體。
  3. 如申請專利範圍第2項所述的一次可程式非揮發性記憶體，其中該電晶體包括一金氧半場效電晶體。
  4. 如申請專利範圍第3項所述的一次可程式非揮發性記憶體，其中金氧半場效電晶體包括：一閘極，設置於該基底上；一第一摻雜區與一第二摻雜區，分別設置於該閘極兩側的該基底中，其中該第一摻雜區作為耦接至該導體層的該端子；以及一閘介電層，設置於該閘極與該基底之間。
  5. 如申請專利範圍第4項所述的一次可程式非揮發性記憶體，其中該導體層與該閘極源自於同一層半導體材料層。
  6. 如申請專利範圍第4項所述的一次可程式非揮發性記憶體，其中該導體層藉由內連線結構耦接到該第一摻雜區。
  7. 如申請專利範圍第2項所述的一次可程式非揮發性記憶體，其中該二極體包括一PN接面二極體或一PIN二極體。
  8. 如申請專利範圍第2項所述的一次可程式非揮發性記憶體，其中該二極體包括：一P型半導體層；以及一N型半導體層，設置於該P型半導體層的一側，且作為耦接至該導體層的該端子。
  9. 如申請專利範圍第8項所述的一次可程式非揮發性記憶體，其中該導體層與該N型半導體層源自於同一層半導體材料層。
  10. 如申請專利範圍第8項所述的一次可程式非揮發性記憶體，更包括一本質層，設置於該P型半導體層與該N型半導體層之間。
  11. 如申請專利範圍第10項所述的一次可程式非揮發性記憶體，其中該本質層的材料包括多晶矽。
  12. 如申請專利範圍第8項所述的一次可程式非揮發性記憶體，其中該導體層直接連接於該N型半導體層。
  13. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該插塞完全覆蓋或部分覆蓋該間隙壁。
  14. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該重疊部分的該導體層的寬度為符合導體層設計規則的最小寬度。
  15. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該插塞的寬度為符合插塞設計規則的最小寬度。
  16. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該導體層的材料包括摻雜多晶矽。
  17. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該插塞包括接觸窗插塞或介層窗插塞。
  18. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，其中該插塞的材料包括鎢、銅、鋁、金、銀、或其合金。
  19. 如申請專利範圍第1項所述的一次可程式非揮發性記憶體，更包括一隔離結構，設置於該基底中，其中該導體層位於該隔離結構上。
  20. 一種一次可程式非揮發性記憶體，包括：一基底；一開關元件，設置於該基底上，其中該開關元件為一二極體，且該二極體包括：一P型半導體層；以及一N型半導體層，設置於該P型半導體層的一側，且作為耦接至該導體層的該端子；以及一熔絲結構，包括： 一導體層，耦接至該開關元件的一端子；一間隙壁，設置於該導體層的側壁上；以及一插塞，設置於該導體層上，且覆蓋該間隙壁，其中該插塞與該導體層的上表面的一重疊部分的一重疊面積小於該插塞的上視面積。
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