CN103370773A - 使用氧化硅多层结构的减少的图案化负载 - Google Patents

使用氧化硅多层结构的减少的图案化负载 Download PDF

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CN103370773A
CN103370773A CN2012800088609A CN201280008860A CN103370773A CN 103370773 A CN103370773 A CN 103370773A CN 2012800088609 A CN2012800088609 A CN 2012800088609A CN 201280008860 A CN201280008860 A CN 201280008860A CN 103370773 A CN103370773 A CN 103370773A
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bdeas
oxygen
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S·巴蒂亚
P·E·吉
S·文卡特拉马
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Abstract

本发明揭示的各方面有关于在图案化基板上沉积共形氧化硅多层的方法。所述共形氧化硅多层各自通过沉积多个子层而形成。子层是通过以下步骤沉积的：将双（二乙基胺基）硅烷(BIS(DIETHYLAMINO)SILANE,BDEAS)与含氧前驱物流入处理腔室，使得在整个图案化基板表面上达成相对均匀的介电质生长速率。在形成子层后可接着有等离子体处理，以进一步改善共形度并且减少共形氧化硅多层膜的湿蚀刻速率。根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖减少，同时仍适合用于非牺牲性的应用。

Description

使用氧化硅多层结构的减少的图案化负载
对相关申请的交互援引
本申请是2011年10月3日提交申请的、名称为“REDUCED PATTERNLOADING USING SILICON OXIDE MULTI-LAYERS”的美国专利申请第13/251,621号的PCT申请，并且本申请相关于且主张2011年3月4日提交申请的、名称为“REDUCED PATTERN LOADING USING SILICON OXIDEMULTI-LAYERS”的美国临时专利申请第61/449,148号的权益，以上两件美国专利申请在此通过援引而并入本文以用于各种用途。
发明背景
通过气体的化学反应在基板上形成介电层是现代化半导体元件的制造中的主要步骤之一。这些沉积工艺包括化学气相沉积（CVD）以及等离子体增强化学气相沉积（PECVD），该PECVD使用等离子体结合传统CVD技术。CVD与PECVD介电层能用做半导体器件中的不同层。例如，介电层可用做为器件中的导电接线之间或互连件之间的金属间介电层。或者，介电层可用做为阻挡层、蚀刻停止物或间隔物，以及其他层。
用于诸如阻挡层与间隔物的应用的介电层一般被沉积覆于图案化基板中的特征结构上，所述特征结构例如为水平互连件（用于后续形成的接线）、垂直互连件（通孔）、栅极堆迭等。较佳地，该沉积提供共形层。然而，经常难以实现共形沉积，因为形成覆于特征结构上的阻挡层可能具有表面缺陷，所述表面缺陷包括不均等的厚度。沉积期间，阻挡层材料可能会过度成块（overloaf），即沉积过多材料于通孔的肩部上且沉积太少材料于通孔的基部中，因而形成看起来像是一块面包的侧边的形状。在极端的情况中，通孔的肩部可能会合而形成接合、密封的表面，且该表面横越通孔的顶部。整个晶片上的膜厚度的不均匀性可能负面地影响一个器件至另一器件的驱动电流的改善。仅仅调变工艺参数无法显著地改善阶梯覆盖率以及图案化负载的问题。
栅极堆迭上方的共形层的沉积也是一项挑战，该共形层的沉积是为了提供后续经蚀刻而形成间隔物的层。虽然已经研发出使用高温低压的常规CVD沉积用于间隔物的氮化硅层与氧化硅层的方法，然而当半导体器件几何大小持续缩小时，此类技术的热预算会变得过高。氮化硅与氧化硅沉积的PECVD工艺可在较低的温度下执行，但阶梯覆盖率与图案化负载结果不如以高温低压CVD所获得的阶梯覆盖率与图案化负载结果那么理想。
因此，需要有将介电膜沉积覆于图案化基板中的特征结构上的更加共形的方法。
发明概述
本发明揭示的诸方面有关于在图案化基板上沉积共形氧化硅多层的方法。该共形氧化硅多层各自通过沉积多个子层而形成。子层是通过以下步骤沉积的：将双（二乙基胺基）硅烷(BIS(DIETHYLAMINO)SILANE,BDEAS)与含氧前驱物流入处理腔室，使得在整个图案化基板表面上达成相对均匀的介电质生长速率。在形成子层后可接着有等离子体处理，以进一步改善共形度并且减少共形氧化硅多层膜的湿蚀刻速率。根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖减少，同时仍适合用于非牺牲性的应用。
本发明的诸实施例包括用于在处理腔室的基板处理区域中形成共形氧化硅多层于图案化基板上的方法。该图案化基板具有致密的图案化区域与稀疏的图案化区域。该方法包含多个依序的步骤：(1)执行化学气相沉积的第一循环，包含以下操作：将BDEAS流进基板处理区域，将第一含氧前驱物流进基板处理区域，以及由所述BDEAS与所述含氧前驱物通过化学气相沉积在该图案化基板上形成所述共形氧化硅多层的第一共形氧化硅子层。该方法进一步包括：(2)从所述基板处理区域移除未反应以及部分反应的前驱物。该方法进一步包括：(3)执行化学气相沉积的第二循环，包含以下操作：将BDEAS流进基板处理区域，将第二含氧前驱物流进基板处理区域，以及由所述BDEAS与所述含氧前驱物通过化学气相沉积在该图案化基板上形成所述共形氧化硅多层的第二共形氧化硅子层。该第一共形氧化硅子层的厚度为约
Figure BDA00003665148500021
或更少。
另外的实施例与特征，部分在随后的说明书中提出，而部分对于本领域技术人员而言在详阅此说明书后可易于了解，或者可通过实践所揭示的实施例而得以了解。通过在说明书中描述的设备、结合物与方法，可了解与获得所揭示的实施例的特征与优点。
附图简要说明
通过参考说明书的其余部份及附图，可进一步了解所揭示的实施例的本质与优点。
图1是根据所揭示的实施例的共形氧化硅沉积工艺的流程图。
图2是根据所揭示的实施例沉积的共形氧化硅的湿蚀刻速率比值（WERR）的图表。
图3图示根据本发明的实施例的基板处理系统。
图4A图示根据本发明的实施例的半导体处理腔室的简化示意图。
图4B图示与处理腔室相关的气体平板与供应线路的简化示意图。
发明的详细描述
本发明所揭示的诸方面有关于在图案化基板上沉积共形氧化硅多层的方法。该共形氧化硅多层各自通过沉积多个子层而形成。子层是通过以下步骤沉积的：将双（二乙基胺基）硅烷(BIS(DIETHYLAMINO)SILANE,BDEAS)与含氧前驱物流入处理腔室，使得在整个图案化基板表面上达成相对均匀的介电质生长速率。在形成子层后可接着有等离子体处理，以进一步改善共形度并且减少共形氧化硅多层膜的湿蚀刻速率。根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖减少，同时仍适合用于非牺牲性的应用。
本发明的实施例是针对在基板的图案化表面上形成氧化硅的方法。次大气压CVD（SACVD）与相关工艺涉及将含硅前驱物与氧化前驱物流进处理腔室而在基板上形成氧化硅。含硅前驱物可包括TEOS，且氧化前驱物可包括臭氧（O3）、氧气（O2）及/或氧自由基。发明人已经发现，结合使用BDEAS作为含硅前驱物来形成氧化硅多层减少了沉积的氧化硅的图案化负载效应（PLE）。
在不使权利要求的涵盖范围受限于可能（或可能不）完全正确的假设性机制的情况下，描述可能在形成共形氧化硅多层期间发生的效应仍是有所帮助的。BDEAS比TEOS与其他替代性的含硅前驱物更具反应性，但更加依赖于含氧前驱物的存在，这是由于BDEAS内缺乏氧所造成。BDEAS与氧气（O2）的结合倾向在表面处或在接近表面处反应，造成沉积速率大致上与暴露的表面的面积成正比。此表现可能是在此所报告的期望共形度的肇因。当化学反应进行，接近表面的面积内的化学物种随着时间改变。发明人已经发现，氧化硅膜随着沉积的进行而变得较不共形。为了再度获得有利的限制于表面的反应，可从基板处理区域移除已经反应与部分反应的化学物种，且可重新启动沉积。周期性地移除反应过的物种可导致生长工艺更加均匀地受到表面反应支配，使得图案化基板的较高的表面积的区域相对于较低的表面积区域接收额外的沉积。额外的沉积造成在整个图案化基板（具有高特征结构密度区和相对开放区二者）上有相对恒定的膜厚。
为了较佳地了解与认识本发明，现在参考图1，该图是根据所揭示的实施例的共形氧化硅沉积工艺的流程图。该工艺起始于图案化基板传送进入基板处理区域时（操作110）。在操作120，BDEAS与含氧前驱物流进该区域，且在操作130，形成氧化硅的共形层。一些实施例中，含氧前驱物包含分子氧（O2）。其他实施例中，含氧前驱物包含分子氧（O2）与臭氧（O3）二者。在所揭示的实施例中，BDEAS的流速可低于每分钟4克（g/min）、3g/min、2g/min、1g/min或500mg/min的其中之一，以使未结合到共形的氧化硅膜中的BDEAS的消耗减少。BDEAS的流速在所揭示的实施例中可大于100mg/min、200mg/min、300mg/min、500mg/min与800mg/min的其中之一，以维持共形氧化硅膜具有有生产效益的生长速度。额外的实施例由所述上限之一结合所述下限之一而得。可藉由将相对惰性的载气（例如氮气（N2））通过BDEAS的流体供应器而起泡，并且将氮气与BDEAS的组合物运送到基板处理区域，而引发BDEAS流动。氮气或类似气体的流速可以是标准状态下每分钟数十升（数十slm）。在多个实施例中，基本上在操作115期间不施加等离子体功率至基板处理区域，因为前驱物以较佳的限于表面的方式反应，无需等离子体激发。
未反应与部分反应的前驱物生成并且在图案化基板附近徘徊，因而抑制了高度共形的生长，尤其是沉积的氧化硅子层的超出一定厚度的高度共形生长。从基板处理区域移除未反应与部分反应的前驱物（操作120），以使未来的沉积循环得以更加共形。视情况任选的等离子体处理（操作125）可用于在额外沉积前使共形氧化硅层致密化。一些实施例中，不使用视情况任选的等离子体处理。一旦达成期望的氧化硅厚度，可从基板处理区域移除图案化基板（操作130）。在操作127决定终结或持续沉积额外子层。倘若期望额外的沉积或因某应用而需要额外的沉积，则再度开始沉积（操作115）。所揭示的实施例中，共形氧化硅多层的形成可涉及两个、三个、四个、五个（或更多个）共形子层的形成。
等离子体处理（操作125）可跟随所述多个子层沉积的其中一些或各个子层沉积（操作115），或可在子层沉积后无等离子体处理。在此每一子层沉积可指化学气相沉积的一个“循环”。两个循环的结合沉积可描述为第一沉积循环与第二沉积循环。取决于结合的沉积所需的共形度及/或厚度，可使用额外的沉积循环。等离子体处理涉及在移除未反应与部分反应的前驱物（操作120）之后或期间将等离子体处理气体导入基板处理区域。揭示的实施例中，等离子体处理气体包含氩气、氦气、臭氧或氮气（N2）的其中的一种或多种。也可使用其他气体。视情况加入等离子体处理（操作125）作用为在移除基板或进行额外沉积之前先致密化子层。已发现等离子体处理对于较薄的子层更为有效。在运用等离子体处理的情况下，本文在等离子体处理之后描述子层厚度。在本发明的实施例中，子层厚度可低于或约
Figure BDA00003665148500051
低于或约
Figure BDA00003665148500052
或者是低于或约
Figure BDA00003665148500053
对基板处理区域施加等离子体功率，故可将该等离子体描述为本地式（local）。本发明的实施例中，对于300mm直径的圆形基板而言，等离子体功率可大于300瓦、介于300瓦与1500瓦之间或在400瓦与1000瓦之间。对于具有用于沉积的不同暴露面积的基板而言，需要适当修正。数百千赫（例如350kHz）的等离子体频率显现具有比高频（13.6MHz）更为减少的效应。本发明的实施例中，等离子体激发频率大于或约为5MHz或约为13.6MHz。微波频率也可致密化共形的氧化硅子层。
形成氧化硅的特性同样取决于氧气（O2）与BDEAS的流速。从低的数值增加氧气（O2）流速造成沉积速率增加。氧气流速的阈值之后，抵达沉积速率的平稳段（plateau）。在所揭示的实施例中，氧气（O2）的流速可低于标准状态下每分钟40升（40slm）、30slm、25slm、20slm或15slm的其中之一，以增加氧气的有效使用，因而使未结合到共形的氧化硅膜中的氧气消耗减少。在揭示的实施例中，氧气（O2）的流速可大于5slm、10slm、15slm、20slm与25slm的其中之一，以维持共形氧化硅膜具生产效益的生长速率。额外的实施例由所述上限之一结合所述下限之一而得。
对臭氧（O3）的依赖具有不同的特质。相对低浓度的臭氧促进生长速率，同时通过确保表面驻留的沉积反应而维持共形度。高速臭氧流非期望地增加图案化负载效应（PLE）。在本发明的一些实施例中，基本上无臭氧流进基板处理区域。当运用臭氧时，臭氧的流速伴随分子氧，但本文所给的流速仅包括贡献给总流速的臭氧。臭氧（O3）的流速可低于1slm、500sccm、300sccm、200sccm、150sccm、100sccm与70sccm的其中之一，以避免相对高的图案化负载效应。臭氧流速愈低，图案化负载效应愈少。前驱物的受到限制的流有时称为扼流（choked flow）。在此情况中，臭氧的扼流可实质上将反应限定在更接近图案化基板表面处或在图案化基板表面上，因而促使均匀的沉积而无论局部暴露的图案区密度如何。
在所揭示的实施例中，如前文所述的O3、O2与BDEAS的流动是并流的（concurrent）。如在此所用的流速在工艺期间并非必然为恒定。可用不同顺序启动及终结不同前驱物的流速，且可变化所述流速的量值。就此而言，并流并非意味所有三个气流一起启动及终结。如在此所用的并流意味着沉积期间存在一段时间，在该段时间内所有三个气流为非零。在所揭示的实施例中，在沉积工艺的历时中，所有三个前驱物流为非零。除非另外指定，否则依工艺期间所用的大约峰值流速来给定在此所指的质量流速量值。在此所指的流速量值是针对一对300mm直径晶片（面积大约1400cm2）的一个侧面上的沉积。对于不同数目的晶片、较大或较小的晶片、双面沉积或替代的几何形状晶片（例如矩形晶片）上的沉积而言，需要基于沉积面积做适当修正。
沉积各氧化硅子层期间在基板处理区域中的压力可低于SACVD与HARP工艺（例如600Torr），这是由于BDEAS的反应性所造成。形成共形氧化硅子层期间的压力在所揭示的实施例中可低于350Torr、300Torr、250Torr、200Torr或150Torr的其中之一，以减少反应失控的风险。在所揭示的实施例中，该压力可大于50Torr、100Torr、150Torr或200Torr之一，以维持有生产效益的生长速率。额外的实施例由所述上限之一结合所述下限之一而得。
在多个实施例中，基板温度低于阈值，也确保与氧化硅子层沉积相关的反应在图案化基板的表面附近或表面上进行。在所揭示的实施例中，沉积共形氧化硅层期间的基板温度低于400℃、375℃、350℃、325℃与300℃之一。在多个实施例中，沉积期间无等离子体存在于基板处理区域中。根据实施例，在无损沉积工艺的优点的情况下，可施加少量ac及/或dc电压到基板处理区域。此类激发不应视为背离可能记载在某些权利要求中的“基本上”无等离子体的范畴或“基本上”不具无等离子体的工艺的范畴。
供应臭氧与TEOS的扼流也形成共形的氧化硅层。然而，藉此形成的膜拥有较大的孔隙度与高湿蚀刻速率。使用BDEAS形成的共形氧化硅多层具有较大的密度以及相较而言较低的湿蚀刻速率。在所揭示的实施例中，根据所揭示的实施例形成的氧化硅多层的湿蚀刻速率拥有多个湿蚀刻速率（使用1%的HF溶液），这些湿蚀刻速率低于热生长氧化硅层的湿蚀刻速率的6倍、5倍、4倍、3倍或2.5倍的其中一。在此呈现的所揭示的实施例中生长的共形氧化硅膜的较大的密度以及较小的湿蚀刻速率能使共形氧化硅膜（或该氧化硅膜的多个部分）并入最终完成的器件中。较多孔的膜（诸如在低基板温度下以扼流的臭氧与TEOS生长的那些膜）大体上必须被移除，这是由于较多孔的膜的较不具弹性的结构所造成。因而，使用BDEAS与臭氧生长的材料于后续处理期间可留在图案化基板上。
移除未反应与部分反应的前驱物期间（操作120），可终结BDEAS的流动，以使沉积反应副产物得以从处理区域移除。在本发明的实施例中，在移除未反应与部分反应的前驱物期间（操作120）或之后，减少腔室中的压力。减少的压力确保副产物浓度被减少到足以回复后续沉积的子层的共形度。或者，可将等离子体处理气体流入基板处理区域，以替换掉未反应及部分反应的前驱物。在本发明的实施例中，不论移除方法如何，基板处理区域内的BDEAS的分压可被减少至流入BDEAS与含氧前驱物的操作期间BDEAS分压的约10%或更低、约5%或更低，或者约3%或更低。存在于基板处理区域中的BDEAS的分压是驻留在接近表面区域中的未反应与部分反应的前驱物的浓度指标。
在所揭示的实施例中，在一个、数个、或每个氧化硅子层的等离子体处理期间（操作125）在基板处理区域中的压力可低于50Torr、20Torr、10Torr或8Torr。在所揭示的实施例中，该压力可大于1Torr、2Torr、3Torr或4Torr之一者。额外的实施例由所述上限之一结合所述下限之一而得。
图2是根据所揭示的实施例沉积的共形氧化硅的湿蚀刻速率比值（WERR）之图表。在无中间插入的等离子体处理（操作125）的情况下形成共形氧化硅多层，该多层中每一子层被测得为约
Figure BDA00003665148500071
湿蚀刻速率比值测得为14.30。所述测量中每一测量的湿蚀刻速率比值是通过比较共形氧化硅多层的蚀刻速率并且除以热生长氧化硅的湿蚀刻速率而决定的。热生长氧化硅为非常高密度形式的氧化硅，具有在氢氟酸溶液中最低的已知蚀刻速率。在这些试验中，使用1%的氢氟酸溶液蚀刻氧化硅多层。
还用中间插入的等离子体处理（由氮气（N2）形成）来生长共形氧化硅多层，且该共形氧化硅多层长成具有
Figure BDA00003665148500072
厚度的子层。WERR测得为4.41。据发现，类似方式制备的具有子层（各子层为
Figure BDA00003665148500073
厚）的共形氧化硅多层膜具有较大的WERR，该WERR为5.72。此发现证实等离子体处理在处理穿透深度上有极限。较薄的子层比较厚的子层更完整地被致密化。以臭氧、氦气与氩气的等离子体处理气体形成另三对共形氧化硅多层。以臭氧与氦气等离子体处理的这两对多层彼此在WERR上类似。氩气等离子体产生WERR较低的膜，而氮等离子体相较而言得到WERR较高的膜。较佳实施例中，等离子体处理气体包含氩气。大体而言，等离子体处理气体可包含这些示例性气体的组合，但也可包含其他气体，因为看来化学反应性并未扮演主要角色。
通过从在稀疏图案化区域与致密图案化区域中的垂直特征结构比较共形氧化硅多层的水平生长，而量化图案化负载。示例性的致密图案化区域可具有比稀疏图案化区域更大量的特征结构，以在相同的面积（由图案化基板上方观看）内建立较大的暴露表面。在揭示的实施例中，致密图案化区域可具有一暴露的垂直面积，该致密图案化区域的该暴露的垂直面积比稀疏图案化区域的暴露的垂直面积大一倍数（multiplicative factor），该倍数大于2、3、5、10或20的其中之一。在本发明的实施例中，致密图案化区域中的共形氧化硅多层的厚度可在稀疏图案化区域中的共形氧化硅多层的厚度的20%、15%、10%、5%与3%的其中之一内。可在垂直表面上测量各区域中的厚度，在此情况中，生长是水平方向。或者，可在各区域内的水平表面上测量厚度，则生长可在垂直方向上。全文中所用的“垂直”与“水平”用语包括实质上垂直与实质上水平的方向，这些方向可能（或可能不）偏离理论的垂直及水平高达约10度。
示例性基板处理系统
可施行本发明实施例的沉积腔室可包括次大气压化学气相沉积（SACVD）腔室，更大体而言，包括容许在相对高压下操作而无须应用等离子体激发的沉积腔室。可施行本发明实施例的CVD系统的特定示例包括CENTURAULTIMA
Figure BDA00003665148500081
SACVD腔室/系统，与PRODUCER
Figure BDA00003665148500082
HARP、eHARP及SACVD腔室/系统，这些腔室/系统可购自美国加州圣克拉拉市的应用材料公司。
沉积系统的实施例可结合至用于生产积体电路芯片的较大型制造系统中。图3图示一个根据所揭示的实施例的沉积、烘烤及固化腔室的此类系统300。在该图中，一对FOUP（前开式晶片盒）302供给基板（例如直径300mm的晶片），所述基板是由自动机械臂304接收并且在放进基板处理腔室308a-f中的一个腔室之前，放进低压固持区域306。第二自动机械臂310可用于将基板晶片从固持区域306传输到基板处理腔室308a-f以及反向传输。
基板处理腔室308a-f可包括用于沉积、退火、固化及/或蚀刻基板晶片上的介电膜的一或多个系统部件。在一配置方式中，两对处理腔室（例如308c-d及308e-f）可用于沉积介电材料于基板上，而第三对处理腔室（例如308a-b）可用于以等离子体处理所沉积的介电质。在另一配置方式中，相同的两对处理腔室（例如308c-d及308e-f）可经配置以沉积及等离子体处理基板上的所沉积的介电膜，同时第三对腔室（例如308a-b）可用于UV或电子束固化沉积的膜。在又一配置方式中，所有三对腔室（例如308a-f）可经配置以沉积及固化基板上的介电膜。在再一配置方式中，两对处理腔室（例如308c-d与308e-f）可用于沉积及UV或电子束固化介电质，同时第三对处理腔室（例如308a-b）可用于退火介电膜。任何一或多个所述工艺可在与所揭示的实施例中所示的制造系统分开的腔室中执行。
图4A图示基板处理系统300内的示例性基板处理腔室的简化示意图。此示例性基板处理腔室410适合执行各种半导体处理步骤，所述步骤可包括CVD工艺以及其他工艺，诸如回流、驱入(drive-in)、清洁、蚀刻与吸气(gettering)工艺。多重步骤的工艺亦可在单一基板上执行，而无须将基板移出腔室。系统的代表性主要部件包括腔室内部415（接收来自气体运送系统489的工艺气体和其他气体）、泵送系统488、远端等离子体系统(RPS)455及系统控制器453。这些与其他部件在下文中予以描述以使人了解本发明。
基板处理腔室410包括封围组件412，该组件容纳具有气体反应区域416的腔室内部415。气体分配板420设在气体反应区域416上方，以将反应性气体与其他气体（诸如净化气体）散布穿过气体分配板420中的穿透孔洞至安置在垂直上可移动的加热器425上的基板（图中未示），该加热器425也可指基板支撑底座。垂直可移动的加热器425能够可控地在下方位置（例如可加载或卸载基板之处）与处理位置（紧邻气体分配板420，如虚线413所指）之间移动，或移动至其他位置，用于诸如蚀刻或清洁工艺之类的其他目的。中心板（图中未示）包括用于提供基板位置的信息的传感器。
气体分配板420可为美国专利第6,793,733号中所述的各种样式。这些板改善基板处气体支出的非均匀性，且特别有利于改变气体浓度比率的沉积工艺。一些示例中，所述板与垂直可移动的加热器425（或可移动的基板支撑底座）结合运作，使得当比率在一个方向上重度不对称时（例如，当含硅气体的浓度相较于含氧化剂气体浓度为很小时）使沉积气体在离基板较远处释放，而在浓度改变时（例如，当混合物中含硅气体的浓度较高时）将沉积气体在较靠近基板处释放。在其他示例中，气体分配板的流孔（orifice)被设计成提供气体更均匀的混合。
垂直可移动的加热器425包括电阻式加热元件（图中未示），该元件被包纳在陶瓷中。陶瓷保护该加热元件免受潜在的腐蚀性腔室环境，并且使得该加热器达到高达约800℃的温度。在示例性实施例中，垂直可移动的加热器425在腔室内部415暴露的所有表面是由陶瓷材料制成，诸如氧化铝（Al2O3或铝土）或氮化铝。
反应性气体与载气通过工艺气体供应线路443供应至气体混合箱（也称为气体混合区块）427，在气体混合箱427处反应性气体与载气较佳为一起混合并且被运送到气体分配板420。气体混合区块427较佳为双重输入混合区块，该混合区块耦接工艺气体供应线路443以及清洁/蚀刻气体导管447。闸阀428操作以容许来自清洁/蚀刻气体导管447的气体或等离子体至气体混合区块427或封住该气体或等离子体。清洁/蚀刻气体导管447接收来自远端等离子体系统（RPS455）的气体，该RPS455具有输入线路457以接收输入气体。沉积处理期间，供应到气体分配板420的气体朝基板表面（如箭号421所指）通气，在该基板表面处气体可在整个基板表面上均匀地径向分配，通常是以层流的形式。
净化气体可经由气体分配板420及/或穿过封围组件412的壁（较佳是底部）的进入通口或管（图中未示）运送进入腔室内部415。净化气体从进入通口向上流动经由垂直上可移动的加热器425并且至环状泵送通道440。排放系统随后排放气体（如箭号422所指）进入环状泵送通道440并且经由排放线路460到泵送系统488，该泵送系统488包括一或多个真空泵。排放气体以及所输送的粒子，以由节流阀系统463控制的速率，从环状泵送通道440经由排放线路460抽出。
RPS455能够产生等离子体以用于所选择的应用，该应用诸如为腔室清洁或从工艺基板蚀刻掉原生的氧化物或残余物。在RPS455中由前驱物（通过输入线路457供应）产生的等离子体物种被经由清洁/蚀刻气体导管447输送，以穿过气体分配板420发送到气体反应区域416。用于清洁应用的前驱物气体可包括氟、氯及其他反应元素。通过选择在RPS455中使用的适当的沉积前驱物气体，RPS455也可适于沉积等离子体增强CVD膜。
系统控制器453控制沉积系统的活动及操作参数。处理器451执行系统控制软件，诸如储存在耦接到处理器451的存储器452中的计算机程序。存储器452一般由静态随机访问存储器（高速缓冲存储器）、动态随机访问存储器（DRAM）及硬盘驱动器的组合构成，但当然存储器452也可由诸如固态存储设备之类的其他类型存储器所构成。除了这些存储装置外，在较佳实施例中的基板处理腔室510包括可移除储存媒体驱动器、USB端口及插卡框架（图中未示）。
处理器451根据系统控制软件操作，该软件经编程以根据在此所揭示的方法操作装置。例如，指令集可指示时序、气体混合、腔室压力、腔室温度、等离子体功率等级、基座位置以及特定工艺的其他参数。所述指令，较佳是通过搭载模拟或数字信号的直接电缆（该直接电缆传送源自输入输出1/O模组450的信号），被传送到适当的硬件。其他计算机程序，诸如储存在其他存储器（包括例如USB随身碟、软盘或另一插在磁碟机或其他适当驱动机器中的计算机程序产品）的计算机程序，也可用于操作处理器451以将基板处理腔室410配置用于各种用途。
处理器451可具有插卡框架（图中未示），该插卡框架含有单板计算机、模拟和数字输入/输出板、接口板及步进马达控制器板。半导体处理系统300的各部件符合Versa Modular European(VME)标准，该标准定义电路板、接口卡插件箱(card cage)以及连结器的规格与类型。VME标准还定义具有16比特数据总线和24比特地址总线的总线结构。
可使用由系统控制器执行的计算机程序产品实施用于在图案化基板上沉积共形氧化硅多层的工艺或者用于清洁腔室的工艺。计算机程序代码可以任何常规的计算机可读的编程语言来编写，例如68000汇编语言、C、C++、Pascal、Fortran或其他语言。使用常规的文本编辑器将适合的程序代码编成单一文件或多个文件，并且储存或实现于计算机可使用媒介（如计算机的存储器系统）。倘若编入的编码文本是高阶语言，则编译代码，而所得的编译器代码随后与预先编译的Microsoft
Figure BDA00003665148500111
库例程的对象代码相链接。为了执行该被链接且被编译的对象代码，系统使用者调用该对象代码，使计算机系统将该代码载入存储器中。CPU随后读取并且执行该代码，以操作程序中所标识的任务。
使用者与控制器之间的介面是通过平板接触感应监视器。在较佳实施例中，使用两个监视器，一个安装在清洁室壁中以供操作者使用，另一个在壁后以供维修技术人员使用。两个监视器可同时显示相同信息，该实例中，一次仅有一个监视器接受输入。为了选择特定的屏幕或功能，操作者接触该接触感应监视器的指定的区域。被接触区域改变该接触区域的高亮色彩，或显示新的菜单或屏幕，以确认操作者和接触感应监视器之间的沟通。可使用其他装置取代接触感应监视器，或者是除了接触感应监视器之外可使用其他装置以让使用者与系统控制器沟通，所述其他装置例如为键盘、鼠标或其他指示或通信元件。
在此揭示的实施例依赖于直接电缆与单一处理器451。也可能有包含多核心处理器、分布式控制下的多处理器、及系统控制器与受控对象之间无线通信的替代性实施例。
图4B图示与基板处理腔室410有关的气体供应平板480的简化示意图。如前文所论及，所示的半导体处理系统300的部份包括具有垂直上可移动的加热器425的基板处理腔室410、具有来自工艺气体供应线路443与清洁/蚀刻气体导管447的输入的气体混合区块427、以及具有输入线路457的RPS455。如前文所提，气体混合区块427经配置用于将沉积气体（多种）与清洁气体（多种）或其他气体（多种）混合，并经由工艺气体供应线路443与输入线路457注射至腔室内部415。
RPS455一体式地位于并且装设在基板处理腔室410下方，而清洁/蚀刻气体导管447并排靠于基板处理腔室410且延伸至闸阀428与气体混合区块427，该气体混合区块427位于基板处理腔室410上方。等离子体功率生成器411与臭氧发生器459位于清洁室的远端。来自气体供应平板480的供应线路483与485提供反应性气体至工艺气体供应线路443。气体供应平板480包括来自气体或液体源490的线路，所述源490提供工艺气体以供所选择的应用。气体供应平板480具有混合系统493，该混合系统493在所选择的气体流至气体混合区块427之前混合所述气体。在一些实施例中，气体混合系统493包括液体注射系统，以气化一或多种反应液体，诸如BDEAS、正硅酸乙酯（tetraethylorthosilicate,TEOS）、硼酸三乙酯（triethylborate,TEB）及磷酸三乙酯（triethylphosphate,TEPO）。来自液体的蒸气通常与载气（诸如氦）结合。用于工艺气体的供应线路可包括：(i)关闭阀495，能用于通过自动或手动的方式关闭工艺气体进入供应线路485或输入线路457的流动；以及(ii)液体流量计（LFM）401，或其他类型的控制器，以测量经由供应线路的气体或液体的流动。
作为一示例，包括做为硅源的BDEAS的混合物可与气体混合系统493在沉积工艺中一并使用，以用于形成氧化硅膜。诸如磷及硼之类的掺杂剂源可包括TEPO与TEB，TEPO与TEB也可被导至气体混合系统493。运送到气体混合系统493的前驱物在室温与室内压力下可为液体，且可通过常规的汽锅型式或起泡器类型的热箱气化。或者，可使用液体注射系统，并且该液体注射系统提供对被导入气体混合系统的反应液体的体积的较大的控制。液体一般以细微喷雾或烟雾形式在被运送到加热气体供应线路485而至气体混合区块与腔室之前注入载气流。氧（O2）通过供应线路483流至腔室，与来自加热气体供应线路485的反应气体在靠近腔室处或腔室中结合。当然，应了解也可使用其他掺杂剂、硅、氧与添加性前驱物的源。虽然供应线路485在图中图示为单个的气体供应线路，然而供应线路485可实际上包含多重线路，所述线路相隔以在前驱物流进腔室内部415前阻绝交互的前驱物反应。
在此所使用的“基板”可为具有（或不具有）形成于该基板上的层的支撑基板。该支撑基板可为绝缘体、或有各种掺杂浓度及掺杂分布曲线的半导体，且可例如为用在集成电路制造上的类型的半导体基板。“氧化硅”层可包括少数浓度的其他元素组份（诸如氮、氢、碳及类似元素）。气体可为两种或更多种气体的结合。全文中所用的术语沟槽（trench）与间隙（gap）绝无暗示经蚀刻的几何形貌必须具有大的水平深宽比。由表面上方所视，间隙可显现圆形、椭圆形、矩形、矩形或各种其他形状。间隙也可为两个柱状物之间的区域，在该情况中，间隙不实体上与其他间隙相隔。如在此所使用，共形层是指表面上的大体上均匀的材料层，该材料层与表面有相同形状，即该层的表面与被覆盖的表面大体上平行。本领域技术人员将认知到沉积的材料可能不会100%共形，而因此该用语“大体上”容许可接受的容差。
通过上述数个实施例的说明，本领域技术人员应知可使用多种修改例、替代架构与等效例，而不背离所揭示的实施例的精神。此外，说明书中不对多种已知的工艺与元件做描述，以避免不必要地混淆了本发明。故，上述说明不应被视为对本发明范畴加以限制。
当提供一数值范围时，除非文本中另外清楚指明，应知还具体揭示介于该范围的上下限值之间各个区间值，数值精度为下限值单位的十分之一。还涵盖了在所陈述数值或陈述范围中的一个区间值与陈述范围中任何另一陈述数值或另一区间值之间的每个较小范围。这些较小范围的上限值与下限值可独立地被包含或排除于该范围中，且在满足该陈述范围中的任何被特别予以排除的极限值的前提下，其中在该较小范围内包含任一个极限值、包含两个极限值，或不含极限值的各范围也涵盖于本发明内。当所陈述的范围包括一个或两个极限值，则同样包括了所包括的极限值中的任一个或两个被排除在外的范围。
说明书与所附权利要求中所使用的单数形式“一”与“该”等用语也包括复数形式，除非上下文中另外清楚指明。因此，举例而言，“一种工艺”所指的包括多个这类工艺，而“该介电材料”所指的包括一或多种介电材料以及本领域技术人员所熟知的该介电材料的等效例。
同样，此说明书与下述权利要求中的“包括”、“包含”、“含有”、“含”以及“具有”等用语旨在说明存在所陈述的特征、整体、部件或步骤，但这些用语并不排除存在或增加一或多种其他特征、整体、部件、步骤、动作或群组。

Claims (20)

1.一种用于在处理腔室的基板处理区域中在图案化基板上形成共形氧化硅多层的方法，其中所述图案化基板具有致密图案化区域与稀疏图案化区域，所述方法包含以下依序的步骤：
执行化学气相沉积的第一循环，包含以下操作：
将BDEAS流进所述基板处理区域；
将第一含氧前驱物流进所述基板处理区域，以及
由所述BDEAS与所述第一含氧前驱物通过化学气相沉积在所述图案化基板上形成所述共形氧化硅多层的第一共形氧化硅子层；
从该基板处理区域移除未反应以及部分反应的前驱物；以及
执行化学气相沉积的第二循环，包含以下操作：
将BDEAS流进所述基板处理区域；
将第二含氧前驱物流进所述基板处理区域；以及
由所述BDEAS与所述第二含氧前驱物通过化学气相沉积在所述图案化基板上形成所述共形氧化硅多层的第二共形氧化硅子层；
其中所述第一共形氧化硅子层的厚度为约或更少。
2.如权利要求1所述的方法，其中将所述第一与第二含氧前驱物流进所述基板处理区域包含以下步骤：将分子氧流进所述基板处理区域。
3.如权利要求2所述的方法，其中所述第一与第二含氧前驱物基本上由分子氧（O2）构成。
4.如权利要求2所述的方法，其中所述第一与第二含氧前驱物基本上不含臭氧（O3）。
5.如权利要求1所述的方法，其中流进所述第一与第二含氧前驱物包含以下步骤：将分子氧与臭氧流进所述基板处理区域。
6.如权利要求5所述的方法，其中所述臭氧的流速低于约300sccm。
7.如权利要求1所述的方法，其中流进BDEAS与流进所述第一含氧前驱物的所述操作是并流的。
8.如权利要求1所述的方法，其中在所述致密图案化区域中的所述共形氧化硅多层的第一厚度是在所述稀疏图案化区域中的第二厚度的一共形度百分比内，且所述共形度百分比为约10%。
9.如权利要求8所述的方法，其中所述第一与第二厚度是在所述图案化基板的实质上垂直的表面上测得的。
10.如权利要求8所述的方法，其中所述致密与稀疏图案化区域中的所述共形氧化硅多层的所述两个厚度是在所述图案化基板的实质上水平的表面上测得的。
11.如权利要求1所述的方法，其中在所述致密图案化区域中的所述共形氧化硅多层的第一厚度是在所述稀疏图案化区域中的第二厚度的一共形度百分比内，且所述共形度百分比为约3%。
12.如权利要求1所述的方法，其中流进BDEAS的所述操作包含以下步骤：以大约100mg/min或更大的流速流进BDEAS。
13.如权利要求1所述的方法，进一步包含以下步骤：在执行所述第一循环后且在执行化学气相沉积的所述第二循环前，以等离子体处理所述第一共形氧化硅子层。
14.如权利要求13所述的方法，其中所述等离子体是由氩气、氦气、臭氧或氮气（N2）的至少一种所形成。
15.如权利要求13所述的方法，其中所述等离子体是通过使用约为5MHz或更大的频率与约为300瓦或更大的功率形成的。
16.如权利要求1所述的方法，其中在形成所述第一共形氧化硅子层期间所述基板处理区域中的压力为约350Torr或更低。
17.如权利要求1所述的方法，其中在形成所述第一共形氧化硅子层期间所述图案化基板的温度为约400℃或更低。
18.如权利要求1所述的方法，其中所述第一共形氧化硅子层的所述厚度大约
Figure FDA00003665148400031
或更小。
19.如权利要求1所述的方法，其中所述致密图案化区域中沉积前的平均的经暴露实质垂直面积超过所述稀疏图案化区域的沉积前的平均的经暴露实质垂直面积达一倍数，所述倍数为约2。
20.如权利要求1所述的方法，进一步包含操作：在化学气相沉积的所述第一循环期间将携带所述BDEAS的载气流进所述基板处理区域。
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