CN102136490A - 半导体装置以及使用它的电力变换装置 - Google Patents

半导体装置以及使用它的电力变换装置 Download PDF

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CN102136490A
CN102136490A CN2010105800927A CN201010580092A CN102136490A CN 102136490 A CN102136490 A CN 102136490A CN 2010105800927 A CN2010105800927 A CN 2010105800927A CN 201010580092 A CN201010580092 A CN 201010580092A CN 102136490 A CN102136490 A CN 102136490A
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semiconductor layer
layer
semiconductor device
semiconductor
groove
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CN102136490B (zh
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渡边聪
森睦宏
新井大夏
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Hitachi Power Semiconductor Device Ltd
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Hitachi Ltd
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Abstract

本发明的课题是提供一种半导体装置以及使用它的电力变换装置，能够保持低损失和高耐压，同时能够提高接通期间中的dv/dt的基于栅极驱动电路的控制性。为解决上述课题，在宽度宽的沟槽(423)的侧壁上设置栅极(401)，由此，因为栅极(401)被栅极绝缘膜(402)和成为层间膜的厚的绝缘膜(403)覆盖，所以栅极的寄生电容小，而且没有浮动p层，因此栅极的电位不变动，能够提高dv/dt的控制性，能够同时兼顾低损失和低噪声。

Description

半导体装置以及使用它的电力变换装置
技术领域
本发明涉及半导体装置以及使用它的电力变换装置，特别涉及适合具有沟槽绝缘栅结构的绝缘栅双极晶体管(Insulated Gate Bipolar Transistor：下面简称IGBT)的半导体装置以及使用它的电力变换装置。
背景技术
IGBT是通过在栅极施加的电压来控制在集电极和发射极之间流过的电流的开关元件。由于IGBT能够控制的功率从数十瓦到数十万瓦，另外开关频率也是从数十赫兹到超过数百千赫的很宽的范围，因而从家用空调机和微波炉等小功率设备到铁道和炼铁厂的逆变器等大功率设备中广泛使用。
在IGBT中，为了使这些电力设备的高效化而要求低损失化，要求降低导通损失和开关损失。同时为防止EMC噪声和误动作、电动机的绝缘损坏等问题，要求能够根据应用的规范控制dv/dt。
在日本特开2000-307116号公报中，如图23所示，公开了改变沟槽栅极的排列间距的结构的IGBT。图23的IGBT的特点在于，在沟槽栅极的间隔较宽的部位不形成p沟道层106，而是设置浮动p层105。
通过形成这样的结构，由于电流仅在沟槽栅极的间隔狭窄的部分流过，所以能够抑制短路时流过的过电流，能够提高元件的抗破坏能力。另外，因为空穴电流的一部分经由浮动p层105流入发射极114，因而发射极114附近的空穴浓度增加，还具有降低导通电压的效果。并且，还具有减缓浮动p层105和n-漂移层104形成的pn结对沟槽栅极施加的电场的效果。
专利文献1：日本特开2000-307116号公报
专利文献2：日本特开2004-39838号公报
专利文献3：日本特开平5-243561号公报
专利文献4：日本特开2009-200103号公报
非专利文献1：Y.Onozawa，et at.，Proc.19th ISPSD，pp13-16，2007
但是，在图23表示的IGBT中，在接通IGBT时，有时发生IGBT或者对臂的二极管的输出电压的时间变化率dv/dt的控制性降低的问题。图24表示接通时的集电极-发射极间电压的计算波形的特性图。如该图所示，存在即使改变栅极电阻dvce/dt也不变化无法控制的期间。
其理由考虑如下。即当IGBT接通时，在图23中的浮动p层105中过渡流入空穴，浮动p层105的电位升高。此时，经由栅极绝缘膜110的寄生电容，在栅极109上流过位移电流，栅极电位升高，因而由MOSFET结构的互导gm和栅极-发射极间电压的时间变化率dvce/dt的积决定的集电极电流的时间变化率dic/dt增加，开关速度加速。过渡流入浮动p层105的空穴的量主要由半导体内部的结构决定，难于通过外部的栅极电阻控制。
因此，无法用外部的栅极电阻控制被加速的dic/dt，结果，发生无法用栅极电阻控制IGBT与对臂的二极管的电压的时间变化率dv/dt的期间。
为抑制通过该浮动p层105的影响引起的栅极电位升高，公开了以下的方法。
在专利文献2中，如图25所示，经由电阻201电气连接浮动p层105与发射极114，抑制浮动p层105的电位升高。
由此从浮动p层105流入栅极109的位移电流减少，抑制栅极电位的升高，结果，能够提高IGBT与对臂的二极管的dv/dt的控制性。
如图26所示，在专利文献3中公开了通过设置宽度大的沟槽栅极，促进来自沟槽栅极的电子的注入来降低损失的方法。虽然在专利文献3中未明示，但是因为不使用浮动p层而是在沟槽栅极底保持耐压，所以不存在由浮动p层的影响引起的栅极电位的变动，能够提高dv/dt的控制性。
如图27所示，在专利文献4中公开了通过在沟槽的侧壁上形成栅极301，在栅极301间填充绝缘层302，降低栅极绝缘膜的寄生电容。由于栅极绝缘膜的寄生电容减低，因而能够提高栅极电压，能够提高dv/dt的控制性。
如图28所示，在非专利文献1中公开了通过对每个单元朝向与沟槽平行的内侧方向交互配置与发射极电气连接的p基极层106，不使用浮动p层来保持耐压。由于不使用浮动p层，因而没有浮动p层的影响引起的栅极电位的变动，能够提高dv/dt的控制性。
但是，在IGBT中，在要求保持低损失和高耐压的同时，要求提高接通切换期间的dv/dt的基于栅极驱动电路的控制性。对于该课题，可知在上述文献的结构中具有以下的改进点。
在专利文献2的场合，虽然越是减小浮动p层105与发射极114之间的电阻201的电阻值，dv/dt的控制性越高，但是因为在接通状态下注入的空穴电流的一部分经由电阻201流出到发射极114，所以促进电子的注入的效果降低，导通电压上升，损失增加。反之，当增大电阻201的电阻值时，存在导通电压的上升变小，但是dv/dt的控制性降低的问题。
在专利文献3的场合，因为设置有宽度大的沟槽栅极，栅极的寄生电容大，所以IGBT的反馈电容大，具有开关损失和栅极驱动电路的功率增大的问题。
在专利文献4的场合，当为了促进电子的注入而增大沟槽的宽度时，在侧壁上形成的栅极301的底部的电场增大，具有耐压、可靠性降低的问题。
在非专利文献1的场合，因为间隔设置p基极层106，所以施加在栅极109上的电场增大，具有耐压、可靠性降低的问题。
发明内容
本发明是鉴于以上问题点而作出的，其目的在于提供一种半导体装置以及使用它的电力变换装置，其能够保持低损失和高耐压，同时能够提高接通切换期间中的dv/dt的基于栅极驱动电路的控制性。
为实现上述目的，本发明的半导体装置特征在于，具有：第一导电型的第一半导体层；在该第一半导体层的表面附近形成的第二导电型的第二半导体层；与所述第一半导体层邻接，在与所述第二半导体层相反一侧的表面附近形成的第二导电型的第三半导体层；在该第三半导体层的上部选择性地设置的第一导电型的第四半导体层；贯穿该第四半导体层和所述第三半导体层到达所述第一半导体层的沟槽；沿该沟槽的内壁设置的栅极绝缘层；在所述沟槽内设置的绝缘层；在所述栅极绝缘层的内侧空间中填充的第一导电层；以及设置在所述绝缘层的表面上的第二导电层，所述第一导电层具有在所述沟槽内夹有所述绝缘层和第二导电层而被分割的剖面结构，或者比不形成该沟槽的区域的宽度b宽地形成所述沟槽的宽度a，并且在所述宽度a宽的所述沟槽的侧壁上设置所述第一导电层。
另外，本发明的电力变换装置具有：一对输入端子；在该输入端子间连接的，串联连接多个半导体开关元件的多条串联连接电路；以及与该多条串联连接电路的各串联连接点连接的多个输出端子，通过所述多个半导体开关元件进行接通、断开，来进行电力的变换，其特征为所述多个半导体开关元件中的各个半导体开关元件是上述的半导体装置。
根据本发明的半导体装置以及使用它的电力变换装置，能够保持低损失和高耐压，同时具有能够提高接通期间中的dv/dt的基于栅极驱动电路的控制性的效果。
附图说明
图1是表示本发明的半导体装置的实施例1的IGBT的截面图。
图2是表示本发明的半导体装置的实施例1的IGBT与专利文献1中公开的IGBT的反馈电容的集电极电压依存性的特性图。
图3是表示本发明的半导体装置的实施例1的IGBT接通时的集电极-发射极间电压的计算波形的特性图。
图4是表示本发明的半导体装置的实施例1的IGBT的制造工序的图。
图5是表示本发明的半导体装置的实施例2的IGBT的截面图。
图6是实施例2中的IGBT的终结区域的截面图。
图7是表示本发明的半导体装置的实施例3的IGBT的截面图。
图8是表示本发明的半导体装置的实施例4的IGBT的截面图。
图9是表示本发明的半导体装置的实施例4的其他例的IGBT的截面图。
图10是表示本发明的半导体装置的实施例4的其他例的IGBT的截面图。
图11是表示本发明的半导体装置的实施例5的IGBT的截面图。
图12是表示本发明的半导体装置的实施例5的其他例的IGBT的截面图。
图13是表示本发明的半导体装置的实施例5的其他例的IGBT的截面图。
图14是表示本发明的半导体装置的实施例6的IGBT的截面图。
图15是表示本发明的半导体装置的实施例7的IGBT的截面图。
图16是表示本发明的半导体装置的实施例7的其他例的IGBT的截面图。
图17是表示本发明的半导体装置的实施例7的其他例的IGBT的截面图。
图18是表示本发明的半导体装置的实施例7的其他例的IGBT的截面图。
图19是表示本发明的半导体装置的实施例7的其他例的IGBT的截面图。
图20是表示本发明的半导体装置的实施例8的IGBT的截面图。
图21是表示本发明的半导体装置的实施例9的IGBT的截面图。
图22是表示本发明的电力变换装置的一个实施例的电路图。
图23是表示专利文献1中公开的现有技术的IGBT的截面图。
图24是表示专利文献1中公开的现有技术的IGBT接通时的集电极-发射机间电压的计算波形的特性图。
图25是表示专利文献2中公开的现有技术的IGBT的截面图。
图26是表示专利文献3中公开的现有技术的IGBT的截面图。
图27是表示专利文献4中公开的现有技术的IGBT的截面图。
图28是剖开一部分表示非专利文献1中公开的现有技术的IGBT的立体图。
图29是用于说明实施例2的层间膜的厚度的根据的特性图。
图中：
100集电极，101集电极端子，102p集电极层，103n缓冲层，104n-漂移层，105浮动p层，106p沟道层，107n发射极层，108p接触层，109、301、401栅极，110、402、栅极绝缘膜，113、302、403、407、417绝缘膜，114、404发射极，115栅极端子，116、119发射极端子，201电阻，405、408、409、413、415、418、419、420、422p层，410、414、416、421n层，411、412多晶硅电极，423、424、425沟槽，426绝缘膜，501、502光致抗蚀剂，601栅极驱动电路，602IGBT，603二极管，604、605输入端子，606、607、608输出端子
具体实施方式
下面根据图示的实施例详细说明本发明的半导体装置。
(实施例1)
图1表示本发明的半导体装置的实施例1的IGBT的截面构造。
该图表示的IGBT大体由下列部分构成：作为第一导电型的第一半导体层的n-漂移层104；在该n-漂移层104的表面附近形成的、相反侧与集电极10接触的作为第二导电型的第二半导体层的p集电极层102；与n-漂移层104邻接、在与p集电极层102相反一侧的表面附近形成的作为第二导电型的第三半导体层的p沟道层106；在该p沟道层106的上部选择性地设置的作为第一导电型的第四半导体层的n发射极层107；贯穿该n发射极层107和p沟道层106到达n-漂移层104的沟槽423；沿该沟槽423的内壁设置的栅极绝缘膜402；在沟槽423内设置的绝缘膜403；在栅极绝缘膜402的内侧空间中填充的作为第一导电层的栅极401；在绝缘膜403的表面上设置的、一部分在沟槽423内向n-漂移层104侧突出的作为第二导电层的发射极电极404；在p集电极层102与n-漂移层104之间形成的n缓冲层103；以及在p沟道层106内形成的p接触层108。此外，101是集电极端子，115是栅极端子，116是发射极端子。
另外，在本实施例的IGBT中，n-漂移层104成为在沟槽423内隔着绝缘膜403和发射极404而被分割的剖面结构。另外，沟槽423的宽度a比不形成沟槽的区域的宽度b宽，图1中有a＞b的关系，在宽度宽的沟槽423的侧壁设置有栅极401。另外，栅极401由于被栅极绝缘膜402和成为层间膜的厚的绝缘膜403(例如栅极绝缘膜402为100nm左右，绝缘膜(层间膜)403为1000nm左右)覆盖，所以栅极的寄生电容与图23表示的现有技术的IGBT相比能够大幅减低。即，现有技术的IGBT的栅极的两侧被薄的栅极绝缘膜覆盖，而在本实施例的结构中，由于一侧被栅极绝缘膜402覆盖，一侧被厚的层间膜(绝缘膜403)覆盖，所以厚的层间膜一侧的寄生电容减低。因为位移电流为(寄生电容)×(浮动p层的电位变化)，当寄生电容小时位移电流也小，能够控制栅极电位的上升，所以能够提高dv/dt的控制性。
图2是表示本发明的实施例1的IGBT与现有技术的IGBT的反馈电容的集电极电压依存性的计算结果的图。栅极的寄生电容是IGBT的反馈电容成分，通过减低寄生电容反馈电容减低。从该图可明显看出，本发明的实施例1的IGBT与现有技术的IGBT相比反馈电容降低到1/4左右。
并且，本发明的实施例1的IGBT因为未设置在现有技术的IGBT中设置的浮动p层，所以不存在浮动p层的影响引起的电位变动，能够提高dv/dt的控制性。另外，关于由于不设置浮动p层而担心的耐压和可靠性的降低，因为发射极404在沟槽423内向n-漂移层104侧突出设置(划分配置)，所以发射极404作为减缓对栅极401的角部施加的电场的场板发挥作用，因而能够防止耐压和可靠性降低。
图3表示本发明的实施例1的IGBT接通时的集电极-发射极间电压的计算波形。从该图可明显看出，在本发明的实施例1的IGBT中，与图24表示的现有技术的IGBT不同，通过改变栅极电阻，能够控制集电极-发射极间电压的dvce/dt。
图4(a)～(k)是表示本发明的实施例1的IGBT的制造工序的一例的图。首先对图4(a)表示的n-漂移层104如图4(b)所示，用光致抗蚀剂501进行图形成型，如图4(c)所示，通过各向异性蚀刻形成宽度宽的沟槽423。接着如图4(d)所示，形成栅极绝缘膜402，如图4(e)所示，堆积作为栅极401的材料的多晶硅，当通过各向异性蚀刻进行回蚀时，如图4(f)所示，由多晶硅组成的栅极401作为侧墙形成在沟槽423的侧壁上。接着如图4(g)所示，用光致抗蚀剂502进行图形成型，打入p型、n型离子，如图4(h)所示，形成p沟道层106以及n发射极层107。接着如图4(i)所示，堆积绝缘膜403，如图4(j)所示，开通接触孔，形成p接触层108。最后，如图4(k)所示，形成发射极404以及集电极端子101、缓冲层103、p集电极层102、集电极100，结束。
此外，在本实施例中，在表面的工序后形成背面的集电极端子101和p集电极层102，但是也可以使用在最初就形成了集电极端子101和p集电极层102的硅基板(エピ基板)。
如上所述，在本发明的实施例1的IGBT中，由于在宽度宽的沟槽423的侧壁上设置有栅极401，因而降低了栅极的寄生电容，能够提高接通期间的dv/dt的基于栅极驱动电路的控制性。
(实施例2)
图5是表示本发明的实施例2的IGBT的截面构造的图。实施例2表示的IGBT的特征为：通过使绝缘膜407比周边区域(未图示：芯片的周边区域)的绝缘膜403(参照图6)更薄，能够提高由发射极404实现的场板效应，能够进一步提高耐压程度。如图所示，栅极401的角部(与栅极401的下侧的发射极404接近的角部)和发射极404的端部(最接近栅极401的角部)越近，场板效应越高，越能提高IGBT的耐高压程度。
但是，在由图6所示的深的p层405(比浮动p层、沟道层深)和浮动电极406构成的IGBT的周边区域中，当绝缘膜403变薄(与绝缘膜407相同程度)时，层间膜中的电场升高，周边区域的耐压降低。因此，在本实施例2中，通过使IGBT的主动区域(图5的区域)的绝缘膜407比周边区域的绝缘膜403更薄，具有主动区域、周边区域都能够保持高耐压的效果。即，因为在主动区域做成薄的绝缘膜407耐压得到提高，在周边区域作为厚的绝缘膜403耐压得到提高，所以在两个区域中改变层间膜的厚度是本实施例的特征。
作为具体的绝缘膜407的厚度，希望为300nm～1000nm左右，希望绝缘膜403在1000nm以上。即，如图29所示，氧化膜(绝缘膜407)的厚度在300nm～1000nm之间耐压连续提高，厚度在300nm以下耐压大体饱和。另外，当把氧化膜做得过薄时，因为在此次打入离子时杂质会扩散到层间膜的基础的Si层，所以希望为300nm左右。
(实施例3)
图7是表示本发明的实施例3的IGBT的截面构造的图。实施例3的IGBT的特征为，沟槽424阶梯状地成为两级，发射极404的n-漂移层104一侧的端部设置在栅极401的角部以下。
通过做成实施例3这样的结构，施加在栅极401的角部上的电场在发射极404的n-漂移层104一侧端部或沟槽424的角部分散，由于与实施例2同样的理由，能够进一步提高耐压。
(实施例4)
图8到图10是表示本发明的实施例4的IGBT的截面构造的图。实施例4的IGBT的特征为，通过在沟槽423下方插入p层，由于空乏层从p层延伸，能够减缓沟槽角部的电场，所以能够减缓栅极401的角部的电场，进一步提高耐压。图8中，在沟槽423的下方一部分插入p层408，在图9中插入p层409以便覆盖栅极401的角部，图10中在p层409内插入n层410。图10的n层410防止接通时向浮动p层409流入的空穴。即，通过在p层的内部设置n层，空穴不会进入n层中，所以能够减低进入浮动层的空穴，可以具有抑制浮动p层的电位升高的效果。
(实施例5)
图11到图13是表示本发明的实施例5的IGBT的截面构造的图。实施例5的IGBT的特征为，通过在p沟道层106的下侧设置p层418，减缓栅极401的角部的电场，能够进一步提高耐压。图11中，在p沟道层下方插入p层418，图12中插入搭在p沟道层106的两侧的栅极401上的p层419，图13中插入搭在一侧的栅极401上的p层420。
(实施例6)
图14是表示本发明的实施例6的IGBT的截面构造的图。实施例6的IGBT的特征为，在沟槽423之上形成由绝缘膜426和多晶硅电极411形成的电容。多晶硅电极411与发射极404连接，在接通时流过沟槽423的下部的空穴电流的一部分用于对上述电容充电，具有能够抑制沟槽423的下部的电位升高，减低栅极电位升高的效果。另外，多晶硅电极411作为场板发挥作用，还具有减缓栅极401的角部的电场，能够实现高耐压的效果。
(实施例7)
图15到图19是表示本发明的实施例7的IGBT的截面构造的图。图15中，与栅极401同样，在沟槽425的侧壁上形成多晶硅电极412，通过在发射极404上连接由栅极绝缘膜402和多晶硅电极412形成的电容，具有能够降低接通时的栅极电位升高的效果。图16通过在多晶硅电极412之间设置p层413，减缓施加在多晶硅电极412的角部的电场，能够实现高耐压化。图17通过在p层413内设置n层414，防止接通时向浮动的p层413内流入的空穴，具有抑制浮动p层的电位升高的效果。图18中设置p层415以便覆盖多晶硅电极412的角部，能够实现高耐压化。另外，图19通过在p层415内设置n层416，防止接通时向浮动的p层415内流入的空穴，具有抑制浮动p层的电位升高的效果。
(实施例8)
图20是表示本发明的实施例8的IGBT的截面构造的图。实施例8的特征为，在p沟道层106的下方插入n层421。该n层421对于要流入发射极404的空穴成为壁垒，所以发射极附近的空穴浓度增加，能够进一步减低导通电压。
(实施例9)
图21是表示本发明的实施例9的IGBT的截面构造的图。实施例9的特征为，在n层421的下方还插入p层422。在实施例8的结构中，可以认为越是提高n层421的载流子浓度，对于空穴的壁垒越高，导通电压的降低效果越高，但是在关断时在n层421中的电场强度增强，耐压降低。
像本实施例这样，因为通过在n层421的下方追加p层422，能够减缓n层421中的电场强度，即使提高载流子浓度，也能够保持耐压，所以能够进一步减低导通电压。
(实施例10)
图22是表示采用在上述各实施例中说明的IGBT的电力变换装置的电路图。
图22的实施例表示逆变器的电路图，601是栅极驱动电路，602是IGBT，603是二极管，604、605是输入端子，从606到608是输出端子，构成在逆变电路中应用在本实施例1到9中说明的IGBT的电力变换装置。
通过在电力变换装置中应用在上述各实施例中说明的IGBT，能够实现电力变换装置的低损失化和高可靠化。
此外，在本实施例中说明了逆变器电路，但是对于变换器或斩波器等其他的电力变换装置也能得到同样的效果。

Claims (25)

1.一种半导体装置，具有：第一导电型的第一半导体层；在该第一半导体层的表面附近形成的第二导电型的第二半导体层；与所述第一半导体层邻接，在与所述第二半导体层相反一侧的表面附近形成的第二导电型的第三半导体层；在该第三半导体层的上部选择性地设置的第一导电型的第四半导体层；贯穿该第四半导体层和所述第三半导体层到达所述第一半导体层的沟槽；沿该沟槽的内壁设置的栅极绝缘层；在所述沟槽内设置的绝缘层；在所述栅极绝缘层的内侧空间中填充的第一导电层；以及设置在所述绝缘层的表面上的第二导电层，所述半导体装置的特征在于，
所述第一导电层具有在所述沟槽内隔着所述绝缘层和第二导电层而被分割的剖面结构。
2.一种半导体装置，具有：第一导电型的第一半导体层；在该第一半导体层的表面附近形成的第二导电型的第二半导体层；与所述第一半导体层邻接，在与所述第二半导体层相反侧的表面附近形成的第二导电型的第三半导体层；在该第三半导体层的上部选择性地设置的第一导电型的第四半导体层；贯穿该第四半导体层和所述第三半导体层到达所述第一半导体层的沟槽；沿该沟槽的内壁设置的栅极绝缘层；在所述沟槽内设置的绝缘层；在所述栅极绝缘层的内侧空间中填充的第一导电层；以及在所述绝缘层的表面上设置的第二导电层，所述半导体装置的特征在于，
所述第二导电层至少在所述沟槽内一部分向所述第一半导体层侧突出。
3.根据权利要求1或2所述的半导体装置，其特征在于，
比不形成所述沟槽的区域的宽度b宽地形成所述沟槽的宽度a。
4.根据权利要求3所述的半导体装置，其特征在于，
在所述宽度a宽的所述沟槽的侧壁上设置所述第一导电层。
5.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
所述第一导电层被所述栅极绝缘层和所述绝缘层覆盖。
6.根据权利要求5所述的半导体装置，其特征在于，
比所述栅极绝缘层厚地形成所述绝缘层。
7.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
比所述半导体装置的周边区域的绝缘层薄地形成所述半导体装置的主动区域的绝缘层。
8.根据权利要求7所述的半导体装置，其特征在于，
所述半导体装置的主动区域的绝缘层的厚度为300nm～1000nm。
9.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
所述沟槽为阶梯状，而且形成为两级。
10.根据权利要求9所述的半导体装置，其特征在于，
以所述阶梯状形成为两级的沟槽内的所述第二导电层的所述第一半导体层侧端部位于比所述第一导电层的所述第一半导体层侧端部靠近第一半导体层侧的位置。
11.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
在所述沟槽的所述第一半导体层侧设置有第二导电型的第五半导体层。
12.根据权利要求11所述的半导体装置，其特征在于，
设置所述第五半导体层，使其覆盖所述第一导电层的所述第一半导体层侧端部。
13.根据权利要求11或12所述的半导体装置，其特征在于，
在所述第五半导体层内设置有第一导电型的第六半导体层。
14.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
在所述第三导电层的所述第一半导体层侧设置有第二导电型的第七半导体层。
15.根据权利要求14所述的半导体装置，其特征在于，
所述第七半导体层的至少一部分搭在位于所述第三半导体层的两侧的所述第一导电层的所述第一半导体层侧端部上。
16.根据权利要求14所述的半导体装置，其特征在于，
所述第七半导体层形成两层，各个所述第七半导体层的至少一部分搭在位于所述第三半导体层的两侧的各个所述第一导电层的所述第一半导体层侧端部上。
17.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
在所述沟槽内形成有由绝缘膜和第三导电层形成的电容。
18.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
在所述沟槽的侧壁的一部分上形成第三导电层，在所述第二导电层上连接了由该第三导电层和所述栅极绝缘层形成的电容。
19.根据权利要求18所述的半导体装置，其特征在于，
在所述第三导电层之间设置有第二导电型的第八半导体层。
20.根据权利要求19所述的半导体装置，其特征在于，
在与所述第八半导体层的所述第一半导体层侧相反的一侧设置有第一导电型的第九半导体层。
21.根据权利要求19所述的半导体装置，其特征在于，
设置所述第八半导体层，使其覆盖所述第三导电层的所述第一半导体层侧端部。
22.根据权利要求20所述的半导体装置，其特征在于，
比所述沟槽的所述第一半导体层侧端部向所述第一半导体层侧突出地设置有所述第九半导体层。
23.根据权利要求1、2、4的任何一项所述的半导体装置，其特征在于，
在所述第三半导体层的所述第一半导体层侧设置有第一导电型的第十半导体层。
24.根据权利要求23所述的半导体装置，其特征在于，
在所述第十半导体层的所述第一半导体层侧，还设置有第二导电型的第十一半导体层。
25.一种电力变换装置，具有：一对输入端子；在该输入端子间连接的，串联连接多个半导体开关元件的多条串联连接电路；以及与该多条串联连接电路的各串联连接点连接的多个输出端子，通过所述多个半导体开关元件进行接通、断开，来进行电力的变换，所述电力变换装置的特征在于，
所述多个半导体开关元件中的各个半导体开关元件是权利要求1到24的任何一项所述的半导体装置。
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