JP5462020B2 - 電力用半導体素子 - Google Patents
電力用半導体素子 Download PDFInfo
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- JP5462020B2 JP5462020B2 JP2010031023A JP2010031023A JP5462020B2 JP 5462020 B2 JP5462020 B2 JP 5462020B2 JP 2010031023 A JP2010031023 A JP 2010031023A JP 2010031023 A JP2010031023 A JP 2010031023A JP 5462020 B2 JP5462020 B2 JP 5462020B2
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- 239000004065 semiconductor Substances 0.000 title claims description 149
- 239000012535 impurity Substances 0.000 claims description 94
- 230000015556 catabolic process Effects 0.000 description 30
- 230000004048 modification Effects 0.000 description 29
- 238000012986 modification Methods 0.000 description 29
- 238000010586 diagram Methods 0.000 description 28
- 239000000758 substrate Substances 0.000 description 15
- 238000009826 distribution Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 230000005684 electric field Effects 0.000 description 10
- 230000008859 change Effects 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 7
- 230000012010 growth Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000000737 periodic effect Effects 0.000 description 5
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Description
図1は、本発明の第1の実施の形態に係るパワーMOSFETのユニットセルを模式的に示す断面図である。
図9は、本発明の第2の実施形態に係るパワーMOSFETのユニットセルの断面とpピラー層の不純物濃度を示す模式図である。
図11は、本発明の第3の実施の形態に係るパワーMOSFETのユニットセルの断面を示す模式図である。図中に示す断面構造は、例えば、図5に示すメッシュ状に配置されたpピラー層およびnピラー層を有するSJ構造を、図1に示すMOSFETに適用した素子の断面を示すものである。また、図中に示された断面図は、図1に示された断面に直交するA−A断面(図5参照)を示している。
図14は、本発明の第4の実施形態に係るパワーMOSFETの断面とSJ構造の不純物分布を示す模式図である。図中に示すpベース層5が形成されている部分の構造は、前述した第1の実施形態および第2の実施形態に示した構造と同じである。本実施形態では、図の中央に示すガードリング層12が、ゲートパッド13(ゲート引き出し電極)周辺に形成されている。ガードリング層12をpベース層5よりも深く形成することにより、隣接するnピラー層3で発生するホールの排出が速やかに行われ、ゲートパッド13の周辺のアバランシェ耐量を高くしている。
図16は、本発明の第5の実施形態に係るパワーMOSFETの断面を示す模式図である。本実施形態は、素子終端部を含めた素子構造に関するものである。
図18は、第6の実施形態に係るパワーMOSFETの構造を模式的に示す断面図である。図18に示すパワーMOSFETは、ゲート絶縁膜8の厚さを一定としたプレナーゲート構造を有している。前述した図1に示すパワーMOSFETでは、pベース層5の間のゲート電極9の中央部において、ゲート絶縁膜8が厚く設けられるテラスゲート構造が用いられている。本実施形態に係るパワーMOSFETは、ゲート電極の構造がプレナーゲート構造である点で、図1に示すパワーMOSFETと異なり、他の構成は同じである。
図20は、第7の実施形態に係る電力用半導体素子を構成する半導体層の平面配置を示す模式図であり、pピラー層4およびpベース層5の配置を示している。本実施形態では、同図中に示すように、ドット状のpピラー層4とpベース層5が、それぞれ所定の周期で格子状に配置されている。また、同図中にB−Bで示される断面は、例えば、図18に示す断面構造とすることができる。pベース層5の表面には、nソース層6が設けられ、さらに、pベース層の下には、pピラー層4aが配置されている。
図24は、第8の実施形態に係るパワーMOSFETのゲート電極9と表面nピラー層11および表面pピラー層10との関係を模式的に示す平面図である。
図26は、第9の実施形態に係るパワーMOSFETの構造を模式的に示す断面図である。本実施形態に係るパワーMOSFETは、図8に示すパワーMOSFETと同じテラスゲート構造を有し、2つのpベース層5の間に多数のpピラー層4とnピラー層3を備えている。一方、本実施形態に係るパワーMOSFETでは、2つのpベース層5の間に設けられたゲート電極9の中央部において、表面pピラー層10に接続するpピラー層4のドレイン層2側の端と、ドレイン層2と、の間の間隔が、pベース層5が表面に設けられたpピラー層4のドレイン層2側の端と、ドレイン層2と、の間の間隔よりも広くなっている。すなわち、表面pピラー層10からドレイン層2に向かう方向のpピラー層4の深さが浅くなっている。
2 n+ドレイン層
3 nピラー層
4 pピラー層
5 pベース層
6 nソース層
7 ソース電極
8 ゲート絶縁膜
9 ゲート電極
10 表面pピラー層
11 表面nピラー層
12 ガードリング層
21 半導体基板
Claims (5)
- 第1導電型の第2の半導体層と、
第1の方向において前記第2の半導体層と交互に位置するように設けられた第2導電型の複数の第3の半導体層と、
前記複数の第3の半導体層のうちの一部の第3の半導体層上に設けられた第2導電型の複数の第4の半導体層と、
前記複数の第4の半導体層上に選択的に設けられた第1導電型の第5の半導体層と、
前記第1の方向において隣接する2つの前記第4の半導体層間において、前記第2及び第3の半導体層の上に設けられ、前記第1の方向に直交する第2の方向に交互に配置された第2導電型の第6の半導体層及び第1導電型の第7の半導体層と、
前記第2の半導体層に電気的に接続された第1の主電極と、
前記第4の半導体層、前記第6の半導体層、及び前記第7の半導体層の上に絶縁膜を介して設けられた制御電極と、
前記第5の半導体層に電気的に接続された第2の主電極と、
を備え、
前記第6の半導体層は、前記2つの第4の半導体層の少なくともいずれか一方に接続され、さらに前記2つの第4の半導体層の間に設けられた少なくとも1つの第3の半導体層に接続され、
前記第6の半導体層に接続された前記第3の半導体層の不純物濃度は、前記第4の半導体層に接続された前記第3の半導体層の不純物濃度よりも高いことを特徴とする電力用半導体素子。 - 前記第6の半導体層に接続された前記第3の半導体層上の前記絶縁膜は、前記複数の第4の半導体層上の前記絶縁膜よりも厚いことを特徴とする請求項1記載の電力用半導体素子。
- 前記制御電極の中心部の直下において、前記第7の半導体層の不純物濃度は、前記第6の半導体層の不純物濃度よりも高いことを特徴とする請求項1または2のいずれかに記載の電力用半導体素子。
- 前記交互に設けられた前記第6の半導体層及び前記第7の半導体層の配置の周期の幅は、前記交互に設けられた前記第2の半導体層及び前記複数の第3の半導体層のそれぞれの配置の周期の幅よりも狭いことを特徴とする請求項1〜3のいずれか1つに記載の電力用半導体素子。
- 前記複数の第3の半導体層のそれぞれの不純物濃度は、
前記第2の主電極の側において、隣接する前記第2の半導体層の不純物濃度よりも高く、
前記第1の主電極の側において、隣接する前記第2の半導体層の不純物濃度よりも低く、
前記複数の第3の半導体層のそれぞれの不純物濃度と、隣接する前記第2の半導体層の不純物濃度と、の差は、前記第4の半導体層の下において大きく、前記第6の半導体層の下において小さいことを特徴とする請求項1〜4のいずれか1つに記載の電力用半導体素子。
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JP5680460B2 (ja) * | 2011-03-23 | 2015-03-04 | 株式会社東芝 | 電力用半導体装置 |
WO2014013888A1 (ja) * | 2012-07-19 | 2014-01-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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WO2017094144A1 (ja) * | 2015-12-02 | 2017-06-08 | サンケン電気株式会社 | 半導体装置 |
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