JP2012064899A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000605 extraction Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 18
- 230000001681 protective effect Effects 0.000 description 12
- 239000012790 adhesive layer Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Abstract
【解決手段】半導体装置100は、第1導電形の第1の半導体領域2と、前記第1の半導体領域の表面に選択的に設けられた第2導電形の第2の半導体領域3と、に電気的に接続された主電極12と、前記第1の半導体領域との間に第1の絶縁膜を介して設けられた制御電極7と、前記制御電極に電気的に接続された引き出し電極13と、前記主電極および前記引き出し電極の上に設けられた第2の絶縁膜15と、前記第2の絶縁膜に形成された複数のコンタクトホール15aの内部に設けられ、前記引き出し電極に電気的に接続された複数のコンタクト電極21と、を備え、前記第2の絶縁膜により前記主電極から電気的に絶縁された制御端子が、前記複数のコンタクト電極に電気的に接続されている。
【選択図】図1
Description
半導体装置100は、例えば、縦型のプレーナMOSFETである。図1に示すように、主電極であるソース電極12と、ドレイン電極17と、の間でオン電流が流れる素子部10において、n+ドレイン層16の上に設けられたn形ドリフト層2と、n形ドリフト層2の表面に設けられたp形ベース領域3と、p形ベース領域3の表面に設けられたn形ソース領域4と、を有している。p形ベース領域3の上には、第1の絶縁膜であるゲート絶縁膜6を介して制御電極であるゲート電極7が設けられている。
そして、絶縁性保護膜15には、ゲート引き出し電極13に連通する複数のコンタクトホール15aが設けられている。コンタクトホール15aの内部には、ゲート引き出し電極13に接続されたコンタクト電極21が設けられている。さらに、コンタクト電極21の上には、金属を含む接着材からなる導電性の接着層23が設けられ、ゲート端子25の接続部25aと、コンタクト電極21と、の間を接続している。
フィールドプレート12aは、素子部10と終端部20との境界に設けられたガードリング18と組み合わされて機能し、終端部における耐圧を向上させる。
図2(a)に示すように、半導体装置100は、ドレイン端子26にボンディングされた半導体チップ90の表面に、ゲート端子25とソース端子27がボンディングされた構成を有している。ゲート端子25の接続部25aと、ソース端子27の接続部27aは、それぞれ平板状の形状を有しており、所謂ダイレクトリード接続が設けられている。ドレイン端子26と半導体チップ90の裏面は、ドレイン電極17を介して電気的に接続される。
一方、ソース端子27の接続部27aも、同じように接着層23を介して半導体チップ90の表面に接続することができる。そして、ソース端子27とソース電極12との間は、電気的に接続される。
図3(a)は、n形ドリフト層2の表面にゲート絶縁膜6となる絶縁膜6aを形成し、ゲート電極となる導電層7aを形成した状態を模式的に示す断面図である。
続いて、図3(c)に示すように、ゲート電極7の表面に絶縁膜31を形成する。例えば、ポリシリコンの表面を熱酸化してSiO2膜を形成することができる。
例えば、ゲート電極7をマスクとして、n形ドリフト層2の表面にp形不純物をイオン注入し、その後、熱処理を施してp形不純物を拡散させることができる。p形不純物としてボロン(B)を用いることができる。
例えば、n形不純物である砒素(As)およびp形不純物であるBを、それぞれ選択的にイオン注入することにより、n形ソース領域4およびp+コンタクト領域5を形成することができる。
図5(a)に示すように、層間絶縁膜33の上に、開口41aを有するレジストマスク41を形成する。続いて、例えば、ドライエッチング法を用いて、層間絶縁膜33をエッチングする。
図6(a)に示すように、開口33aおよび33bが形成された層間絶縁膜33の上に電極メタル36が形成される。例えば、スパッタ法を用いてアルミニウム(Al)膜を形成することができる。
このように、本実施形態に係る半導体装置100の製造方法では、ソース電極12とゲート引き出し電極13とを、p形ベース領域3、n形ソース領域4およびゲート電極7の上に同時に形成することができる。
絶縁性保護膜15は、半導体チップ90の表面を保護するとともに、ゲート端子25とソース電極12との間に介在し、両者を絶縁する。絶縁性保護膜15として、例えば、ポリイミド膜を用いることができる。
コンタクト電極21は、例えば、ニッケル(Ni)電極であり、メッキ法を用いて形成することができる。
接着層23には、例えば、ゲート端子25およびソース端子27を接着するためのハンダ材を用いることができる。
例えば、接着層23がハンダ材である場合、Niを用いたコンタクト電極21は、ハンダのマイグレーションを防ぐバリア層として機能する。さらに、図8中に示すように、コンタクト電極21をゲート引き出し電極13の内側に接触するように形成することにより、コンタクト電極21と絶縁性保護膜15との界面を伝って進入するハンダ材を、ゲート引き出し電極13の表面で止めることが可能となる。
半導体装置200は、ゲート端子25の接続部25aおよびソース端子27の接続部27aを、金属バンプ42を用いてコンタクト電極21に接続した点において、半導体装置100と相違する。金属バンプ42には、例えば、ハンダボールを用いることができる。
そして、コンタクトホール15aおよび15bの開口上に位置した金属バンプ42の上から、ゲート端子25の接続部25aと、ソース端子27の接続部27aと、を熱圧着させることにより、半導体チップ90の表面に接続することができる。
Claims (5)
- 第1導電形の第1の半導体領域と、前記第1の半導体領域の表面に選択的に設けられた第2導電形の第2の半導体領域と、に電気的に接続された主電極と、
前記第1の半導体領域との間に第1の絶縁膜を介して設けられた制御電極と、
前記制御電極に電気的に接続された引き出し電極と、
前記主電極および前記引き出し電極の上に設けられた第2の絶縁膜と、
前記第2の絶縁膜に形成された複数のコンタクトホールの内部に設けられ、前記引き出し電極に電気的に接続された複数のコンタクト電極と、
前記主電極のうちの前記第1の半導体領域の上と前記第2の半導体領域の上と前記制御電極の上とに設けられた部分と、前記引き出し電極と、を覆い、前記複数のコンタクト電極に電気的に接続され、前記第2の絶縁膜により前記主電極から電気的に絶縁された制御端子と、
を備えたことを特徴とする半導体装置。 - 前記コンタクト電極と前記制御端子との間に設けられた金属を含む接続材をさらに備えたことを特徴とする請求項1記載の半導体装置。
- 前記接続材は、ハンダ材または金属バンプであることを特徴とする請求項2記載の半導体装置。
- 前記引き出し電極の総面積は、前記制御端子に覆われた前記主電極の一部の面積よりも狭いことを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。
- 第1導電形の第1の半導体領域と、前記第1の半導体領域の表面に選択的に設けられた第2導電形の第2の半導体領域と、に電気的に接続された主電極と、
前記第1の半導体領域との間に第1の絶縁膜を介して設けられた制御電極と、
前記制御電極に電気的に接続された引き出し電極と、
前記主電極および前記引き出し電極の上に設けられた第2の絶縁膜と、
前記主電極の一部および前記引き出し電極を覆って制御端子がボンディングされる領域において、前記第2の絶縁膜に形成された複数のコンタクトホールの内部に設けられ、前記制御端子と前記引き出し電極とを電気的に接続する複数のコンタクト電極と、
を有する半導体装置の製造方法であって、
前記第1の半導体領域、前記第2の半導体領域および前記制御電極の上に、前記主電極および前記引き出し電極となる金属膜を同時に形成することを特徴とする半導体装置の製造方法。
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JP2019047045A (ja) * | 2017-09-05 | 2019-03-22 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
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JP2017059636A (ja) * | 2015-09-15 | 2017-03-23 | 三菱電機株式会社 | 半導体装置の製造方法 |
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