WO2014156791A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2014156791A1 WO2014156791A1 PCT/JP2014/057208 JP2014057208W WO2014156791A1 WO 2014156791 A1 WO2014156791 A1 WO 2014156791A1 JP 2014057208 W JP2014057208 W JP 2014057208W WO 2014156791 A1 WO2014156791 A1 WO 2014156791A1
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Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
- SiC-MOSFET an insulated gate field effect transistor
- SiC-MOSFET a semiconductor device using a silicon carbide (SiC) semiconductor.
- the front surface element structure of the SiC-MOSFET is a MOS gate (insulated gate made of metal-oxide film-semiconductor) in which a silicon dioxide (SiO 2 ) film is formed as a gate insulating film on the front surface side of the SiC substrate.
- MOS gate insulated gate made of metal-oxide film-semiconductor
- SiO 2 silicon dioxide
- a structure including a structure, a PSG (Phospho Silicate Glass) that is an interlayer insulating film, and an aluminum (Al) electrode that is a front surface electrode is representative.
- FIG. 16 is a cross-sectional view showing a configuration of a conventional SiC-MOSFET.
- the conventional SiC-MOSFET has a p base region 103, n on the front surface side of an epitaxial substrate formed by depositing an n ⁇ epitaxial layer 102 on the front surface of the SiC substrate 101.
- a MOS gate structure including a ++ source region 105, a p + contact region 106, a gate oxide film 108 and a gate electrode 109, an interlayer insulating film 110, and an aluminum-silicon (Al—Si) electrode 113 are provided.
- Interlayer insulating film 110 has a source contact hole that selectively exposes n ++ source region 105 and p + contact region 106.
- the Al—Si electrode 113 is provided so as to cover the front surface of the substrate in the active region, and is electrically connected to the n ++ source region 105 and the p + contact region 106 exposed in the source contact hole of the interlayer insulating film 110. Connected.
- the Al—Si electrode 113 is electrically insulated from the gate electrode 109 by the interlayer insulating film 110.
- Reference numeral 104 denotes a p epitaxial layer, and reference numeral 107 denotes an n return region.
- Reference numeral 111 denotes a titanium nitride (TiN) film, and reference numeral 112 denotes a nickel (Ni) film.
- a contact metal film 114 and a back electrode 115 are sequentially laminated on the back surface of the epitaxial substrate, that is, the back surface of the SiC substrate 101.
- Such a SiC-MOSFET is mounted on a package, and a bonding wire (not shown) made of aluminum is electrically connected to an external connection terminal by ultrasonic vibration on an Al-Si electrode 113 which is a front surface electrode.
- a bonding wire made of aluminum is electrically connected to an external connection terminal by ultrasonic vibration on an Al-Si electrode 113 which is a front surface electrode.
- a step of bringing the material to be plated into contact with an electroless gold plating solution from which gold ions have been removed and an electroless gold plating solution containing gold ions are brought into contact As a method of forming a metal film on the surface of the front electrode, a step of bringing the material to be plated into contact with an electroless gold plating solution from which gold ions have been removed and an electroless gold plating solution containing gold ions are brought into contact.
- the method of performing a process continuously is proposed (for example, refer the following patent document 1).
- the conductive portion formed on the surface of the substrate body is plated, and a Ni film mainly composed of Ni and an Au film mainly composed of gold (Au) are sequentially formed.
- a method of performing post-treatment to remove the Ni compound adhering to the surface of the Au coating see, for example, Patent Document 2 below).
- a first metal film made of Ni—P (phosphorus) is formed by plating on the metal film, and then a second metal film mainly composed of Au is formed on the first metal film.
- the first Ni plating solution is prepared such that the P content in the first metal coating is 3 wt% or more and 6 wt% or less, and the P content in the first metal coating is A second Ni plating solution having a rate exceeding 6% by weight and not more than 9% by weight is prepared, and the first metal film of the first layer is formed on the surface of the metal film using the first Ni plating solution.
- a method of forming the first metal film of the second layer using the second plating solution is proposed (for example, see Patent Document 3 below).
- the conventional SiC-MOSFET has a problem that when a negative voltage is applied to the gate electrode, the gate threshold voltage Vth greatly decreases from a desired set value.
- the case where a negative voltage is applied to the gate electrode is, for example, a case where the gate potential is made negative with respect to the source potential in order to reliably turn off.
- a bias temperature stress test (bias temperature (hereinafter referred to as BT temperature) is set to 200 ° C., a voltage applied to the gate electrode is set to ⁇ 20 V, and a processing time is set to 10 minutes ( (Hereinafter referred to as BT test), it has been confirmed that the gate threshold voltage Vth is about 8 V lower than before the negative voltage application (before the BT test).
- the gate threshold voltage Vth decreases, the MOSFET does not operate as a normal MOSFET, for example, when the positive voltage is not applied to the gate electrode, the source and drain become conductive (hereinafter referred to as normally-on). For this reason, there is a problem that the reliability required for a normal semiconductor device using a silicon (Si) semiconductor cannot be obtained.
- the present invention provides a semiconductor device and a semiconductor device manufacturing method capable of suppressing a decrease in gate threshold voltage in a semiconductor device using a silicon carbide semiconductor in order to solve the above-described problems caused by the prior art. For the purpose.
- a semiconductor device manufacturing method has the following characteristics. First, the 1st process of forming the insulated gate structure which consists of a gate insulating film and a gate electrode on the front surface of a silicon carbide substrate is performed. Next, a second step of forming a front surface electrode made of aluminum or an aluminum alloy, which is insulated from the gate electrode by an interlayer insulating film, is performed on the front surface of the silicon carbide substrate. Next, two or more layers of metal films made of nickel, nickel alloy, copper, palladium, titanium, platinum, gold or silver, or metal films made of these metals are laminated on the surface of the front electrode. A third step of forming a metal laminated film is performed. After the third step, a fourth step of annealing in a nitrogen gas atmosphere, a mixed gas atmosphere containing nitrogen, a vacuum atmosphere, or an argon gas atmosphere is performed.
- a nitrogen gas atmosphere, a mixed gas atmosphere containing nitrogen, a vacuum atmosphere, or an argon gas atmosphere is annealed.
- the method further includes a fifth step of performing the steps.
- the annealing temperature in the fifth step is higher than the annealing temperature in the fourth step.
- the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, the annealing temperature in the fifth step is 350 ° C. or higher.
- the annealing temperature in the fourth step is 150 ° C. or higher and 450 ° C. or lower.
- the annealing temperature in the fourth step is 300 ° C. or higher and 420 ° C. or lower.
- a semiconductor device has the following characteristics.
- An insulating gate structure including a gate insulating film and a gate electrode is provided on the front surface of the silicon carbide substrate.
- a front surface electrode insulated from the gate electrode by an interlayer insulating film is provided on the front surface of the silicon carbide substrate.
- the front surface electrode is made of aluminum or an aluminum alloy.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, a range of 90% or less of the surface of the front surface electrode is covered with the metal film or the metal laminated film.
- a metal film is formed on the surface of the front surface electrode, and the gate electrode is gated by applying a negative voltage to the gate electrode by annealing in a nitrogen atmosphere or the like. There exists an effect that it can control that threshold voltage falls.
- FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment
- 2 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to a first embodiment
- FIG. 6 is a characteristic diagram showing a gate threshold voltage of the semiconductor device according to Example 1
- FIG. 10 is a characteristic diagram illustrating a relationship between the thickness of the first metal film of the semiconductor device according to Example 2 and the gate threshold voltage decrease amount.
- 10 is a chart showing electroless NiP plating treatment conditions of Example 3.
- FIG. 10 is a characteristic diagram illustrating a relationship between a pre-plating process and a gate threshold voltage drop amount in a first metal film of a semiconductor device according to Example 3
- 6 is a chart showing electroless Cu plating conditions of Example 4.
- FIG. 10 is a characteristic diagram showing the relationship between the constituent material of the first metal film of the semiconductor device according to Example 4 and the gate threshold voltage.
- FIG. 12 is a characteristic diagram showing the relationship between the area ratio of the first metal film of the semiconductor devices according to Examples 5 and 9 and the gate threshold voltage drop amount.
- FIG. 10 is a plan view illustrating an arrangement of a first metal film of a semiconductor device according to Example 5;
- FIG. 10 is a characteristic diagram showing the relationship between the annealing atmosphere of the semiconductor device according to Example 6 and the gate threshold voltage drop amount;
- FIG. 10 is a characteristic diagram showing the relationship between the annealing temperature and annealing time of the semiconductor device according to Example 7-1 and the gate threshold voltage drop amount.
- FIG. 12 is a characteristic diagram showing the relationship between the annealing temperature and annealing time of the semiconductor device according to Example 7-2 and the gate threshold voltage drop amount.
- 6 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to a second embodiment
- FIG. 10 is a characteristic diagram showing the gate threshold voltage drop amount of the semiconductor device according to Example 8; It is sectional drawing which shows the structure of the conventional SiC-MOSFET.
- FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment.
- the semiconductor device according to the first embodiment is an epitaxial substrate formed by depositing an n ⁇ epitaxial layer 2 serving as an n ⁇ drift layer on the front surface of an SiC substrate 1 serving as an n drain region.
- SiC-MOSFET fabricated (manufactured) using A p base region 3 is selectively provided in a surface layer on the front surface side (n ⁇ epitaxial layer 2 side) of the epitaxial substrate.
- a p epitaxial layer 4 is deposited from the portion of n ⁇ epitaxial layer 2 sandwiched between adjacent p base regions 3 to p base region 3.
- an n ++ source region 5, a p + contact region 6 and an n return region 7 are selectively provided inside the p epitaxial layer 4, an n ++ source region 5, a p + contact region 6 and an n return region 7 are selectively provided.
- the n ++ source region 5 and the p + contact region 6 are arranged in a portion of the p epitaxial layer 4 facing the p base region 3, penetrates the p epitaxial layer 4 in the depth direction, and reaches the p base region 3.
- the n-back region 7 is arranged in a portion of the p epitaxial layer 4 not facing the p base region 3, penetrates the p epitaxial layer 4 in the depth direction, and n in a portion sandwiched between adjacent p base regions 3. - reach the epitaxial layer 2.
- n Uchikaeshi region 7, on the opposite side with respect to the p + contact region 6 side of the n ++ source regions 5 are arranged apart from the n ++ source regions 5.
- a gate electrode 9 is provided via a gate insulating film 8 from the surface of the portion of the p epitaxial layer 4 sandwiched between the n ++ source region 5 and the n return region 7 to the surface of the n return region 7. .
- the gate insulating film 8 is made of, for example, silicon dioxide (SiO 2 ) or nitrous oxide (N 2 O).
- the gate electrode 9 is made of, for example, polysilicon (poly-Si).
- the gate electrode 9 is covered with an interlayer insulating film 10 such as PSG. Interlayer insulating film 10 has a source contact hole that selectively exposes n ++ source region 5 and p + contact region 6.
- a titanium nitride (TiN) film 11 is provided on the surface of the interlayer insulating film 10. An end portion of the TiN film 11 extends on the surface of the n ++ source region 5 exposed in the source contact hole of the interlayer insulating film 10.
- a nickel (Ni) film 12 is provided on the surfaces of the n ++ source region 5 and the p + contact region 6 exposed in the source contact hole of the interlayer insulating film 10. The end of the Ni film 12 extends on the surface of the portion of the TiN film 11 that covers the interlayer insulating film 10.
- a front surface electrode 13 as a source electrode is provided so as to cover the entire front surface of the epitaxial substrate in the active region.
- An active region is a region through which current flows when in an on state.
- the front surface electrode 13 is provided so as to be embedded in the source contact hole of the interlayer insulating film 10, and is electrically connected to the n ++ source region 5 and the p + contact region 6 through the Ni film 12. Is done.
- a gate pad (not shown) is selectively provided on the front surface of the epitaxial substrate in the active region, and the front surface electrode 13 is separated from the gate pad and on the epitaxial substrate in the active region.
- the front surface is arranged so as to almost cover the portion other than the gate pad.
- the front electrode 13 is made of, for example, aluminum (Al), aluminum containing 1% of silicon (Al-1% Si), or aluminum containing 0.5% of copper (Cu) (Al-0. It is made of an Al alloy such as 5% Cu).
- the first metal film 21 is provided in a region of 10% or more of the surface of the front electrode 13. That is, the first metal film 21 covers a region of 10% or more of the surface area (hereinafter simply referred to as the surface area) S1 on the surface of the front electrode 13 opposite to the SiC substrate side. Thereby, it is possible to suppress the gate threshold voltage Vth from being lowered and to maintain a state where the source and the drain are not conducted when the positive voltage is not applied to the gate electrode 9 (hereinafter, normally off). .
- the ratio of the surface area of the first metal film 21 to the surface area S1 of the front electrode 13 (that is, the contact area with the front electrode 13) S2 ( S2 / S1, hereinafter, the area ratio of the first metal film 21) Is larger, the effect of suppressing the reduction of the gate threshold voltage Vth is increased, which is preferable.
- the area ratio of the first metal film 21 is preferably in the range of 60% to 90%, for example.
- the area ratio of the first metal film 21 is preferably in the range of 60% to 90%, for example.
- the first metal film 21 may be a metal plating film formed by an electrolytic plating process or an electroless plating process, or may be a metal film formed by a sputtering method or a vapor deposition method.
- the first metal film 21 is, for example, a Ni film, a Ni alloy (such as nickel-phosphorus (NiP) or nickel-boron (NiB)) film, a Cu film, a palladium (Pd) film, or titanium (Ti).
- a film, a platinum (Pt) film, a gold (Au) film, or a silver (Ag) film may be used, or a metal laminated film formed by laminating two or more of these metal films.
- the first metal film 21 may be a Ni film, a Ni alloy film, a Cu film, a Ti film, or a metal laminated film formed by laminating two or more of these metal films.
- the reason is as follows, for example.
- a lead frame (not shown) using copper as a base material is soldered to the first metal film 21.
- the first metal film 21 is melted into the melted solder (solder erosion), whereby the thickness of the first metal film 21 is reduced, or the solder and the front electrode 13 are in contact with each other.
- the adhesion force with a lead frame using copper as a base material may be reduced.
- the thickness of the first metal film 21 it is preferable to increase the thickness of the first metal film 21 to, for example, about 2 ⁇ m or more in consideration of the occurrence of solder erosion. This is because the first metal film 21 can be formed in a short time or at low cost when forming the thick first metal film 21 in this way.
- a second metal film 22 such as a gold (Au) film may be provided on the surface of the first metal film 21.
- the region between them and the breakdown voltage structure are protected by a passivation film such as a polyimide film.
- the breakdown voltage structure is a region that is disposed so as to surround the active region, and that holds the breakdown voltage by relaxing the electric field of the active region.
- a contact metal film 14 in which a Ni film and a Ti film are sequentially laminated is provided, and an ohmic contact with the SiC substrate 1 serving as an n drain region is formed. Yes.
- a back electrode 15 formed by sequentially laminating a Ti film, a Ni film, and an Au film is provided.
- FIG. 2 is a flowchart illustrating an outline of the method for manufacturing the semiconductor device according to the first embodiment.
- the front surface electrode 13 and the gate pad are formed by patterning the Al layer into a predetermined shape by photolithography.
- a passivation film (not shown) such as polyimide is deposited (formed) on the front surface of the epitaxial substrate (step S14), and a source pad contact hole for selectively exposing the surface of the front surface electrode 13 and Then, a gate pad contact hole exposing the surface of the gate pad is formed.
- the front electrode 13 is exposed by the corresponding surface area S1.
- heat treatment (curing) for improving the strength of the passivation film is performed at a temperature of 350 ° C. for 1 hour, for example (step S15).
- the back electrode 15 is formed on the surface of the contact metal film 14 by sequentially laminating a Ti film, a Ni film, and an Au film by, for example, a sputtering method or a vapor deposition method (step S16).
- a Ni plating film for example, is formed as the first metal film 21 on the surface of the front electrode 13 exposed in the source pad contact hole of the passivation film by electroless plating (step S17).
- a pre-plating process is performed by a general method, and the front electrode 13 and the first metal film are formed. Adhesion with 21 may be improved.
- the first metal film 21 is not limited to electroless plating, and may be formed by electrolytic plating, sputtering, or vapor deposition.
- the source pad contact hole of the passivation film only needs to be formed before the process of step S17.
- annealing is performed in, for example, a nitrogen (N 2 ) gas atmosphere, a mixed gas atmosphere containing N 2 (eg, N 2 gas + argon (Ar) gas), a vacuum atmosphere, or an Ar gas atmosphere (step S18).
- N 2 nitrogen
- Ar argon
- the annealing temperature in step S18 is preferably low enough that the structure of the first metal film 21 does not change, and may be, for example, 150 ° C. or higher and 450 ° C. or lower.
- the annealing temperature in step S18 is not less than 300 ° C. and not more than 420 ° C., although it depends on the BT test conditions.
- the annealing time in step S18 may be, for example, 0.5 hours or more and 6 hours or less. Preferably, the annealing time in step S18 is not less than 1 hour and not more than 3 hours depending on the BT test conditions. By setting the annealing temperature and the annealing time within such a range, the effect of suppressing the decrease in the gate threshold voltage Vth can be enhanced. Through the above steps, the SiC-MOSFET shown in FIG. 1 is completed.
- the steps S17 and S18 may be performed on a general SiC chip having a configuration formed by the steps S13 to S16.
- the exposed area of the front electrode 13 exposed in the source pad contact hole of the passivation film is about 46% with respect to the surface area S1 of the front electrode 13.
- the opening width of the source pad contact hole is adjusted before the step S17, so that the exposed area of the front electrode 13 is increased. Increase or decrease. Specifically, the exposed area of the front electrode 13 is reduced by selectively covering the front electrode 13 with an insulating film, or the opening width of the source pad contact hole is increased by patterning the passivation film. Therefore, the exposed area of the front electrode 13 may be increased.
- FIG. 3 is a characteristic diagram illustrating the gate threshold voltage of the semiconductor device according to the first embodiment.
- an SiC-MOSFET was manufactured (hereinafter referred to as Example 1).
- a NiP plating film is formed as the first metal film 21 by the electroless NiP plating process in the process of step S17, and the N 2 atmosphere is annealed in the process of step S18 (with plating and with annealing).
- Comparative Example 1 an SiC-MOSFET that was not annealed after forming the first metal film was fabricated.
- steps S13 to S17 of the semiconductor device manufacturing method according to the first embodiment are performed in the same manner as in Example 1, and step S18 is not performed (with plating and without annealing).
- a SiC-MOSFET having no first metal film was fabricated (hereinafter referred to as Comparative Example 2).
- steps S13 to S16 of the method for manufacturing a semiconductor device according to the first embodiment are performed in the same manner as in Example 1, and steps S17 and S18 are not performed (no plating or annealing).
- Example 1 and Comparative Examples 1 and 2 after applying a negative voltage to the gate electrode by a bias temperature stress test (BT test), the gate threshold voltage Vth was measured.
- the result is shown in FIG.
- the BT test conditions were a bias temperature (hereinafter referred to as BT temperature) of 200 ° C., a voltage applied to the gate electrode of ⁇ 20 V, and a processing time of 10 minutes.
- the measurement conditions for the gate threshold voltage Vth were a drain current Id and a drain-source voltage Vds of 25 mA and 10 V, respectively, at room temperature.
- BT temperature bias temperature
- Vds drain-source voltage
- FIG. 4 is a characteristic diagram showing the relationship between the thickness of the first metal film of the semiconductor device according to Example 2 and the gate threshold voltage drop.
- Example 2 a plurality of SiC-MOSFETs having different thicknesses of the first metal film 21 were produced (hereinafter referred to as Example 2).
- Example 2 three samples were prepared in which the thickness of the first metal film 21 was 1 ⁇ m, 4.5 ⁇ m, and 10 ⁇ m, respectively.
- the configuration other than the film thickness of the first metal film 21 of Example 2 is the same as that of Example 1.
- Example 2 the gate threshold voltage Vth before the BT test (before applying a negative voltage to the gate electrode) and the gate threshold voltage Vth after the BT test (after applying the negative voltage to the gate electrode) A difference (hereinafter referred to as a gate threshold voltage drop amount) ⁇ Vth was calculated. The result is shown in FIG.
- the BT test conditions and the gate threshold voltage Vth measurement conditions are the same as in Example 1.
- FIG. 4 shows the gate threshold voltage drop amount ⁇ Vth of Comparative Example 2 (no plating / annealing) as a comparison.
- the gate threshold voltage drop amount ⁇ Vth in Example 2 is substantially equal regardless of the thickness of the first metal film 21 and is smaller than the gate threshold voltage drop amount ⁇ Vth in Comparative Example 2. It was confirmed to be small. Therefore, it was confirmed that the variation (decrease) in the gate threshold voltage Vth of the semiconductor device according to the present invention does not depend on the thickness of the first metal film 21.
- FIG. 5 is a table showing electroless NiP plating conditions for Example 3.
- FIG. 6 is a characteristic diagram illustrating the relationship between the pre-plating process and the gate threshold voltage decrease in the first metal film of the semiconductor device according to the third example.
- Example 3 a plurality of SiC-MOSFETs in which a part of the plating pretreatment process was omitted were manufactured (hereinafter referred to as Example 3).
- Example 3 three samples were prepared in which Step S18 was performed without performing Step S17 after finishing the plating pretreatment at different timings.
- steps S13 to S16 were performed as in Example 1.
- degreasing treatment was performed at a temperature of 50 ° C. for 5 minutes to remove oily dirt and foreign matter adhering to the surface of the front electrode 13 and clean the surface.
- etching was performed for 2.5 minutes at room temperature (RT: 20 ° C.) using an acid solution, and the natural oxide film on the surface of the front electrode 13 was removed.
- RT room temperature
- the pre-plating process is completed at this stage (indicated by arrow A in FIG. 5 and indicated as (A) in FIG. 6 after etching), and then all the processes are performed by annealing in step S18. finished.
- step S18 acid cleaning (desmut treatment) was performed at room temperature for 40 seconds using a nitric acid (HNO 3 ) solution to remove deposits (smut) generated by the etching treatment.
- HNO 3 nitric acid
- the pre-plating process is completed at this stage (indicated by arrow B in FIG. 5 and after acid cleaning (B) in FIG. 6), and then all the processes are performed by annealing in step S18.
- a zincate is performed at room temperature for 40 seconds to replace Al on the surface of the front electrode 13 with zinc (Zn), and a Zn film having a desired crystal grain size on the surface of the front electrode 13 Was generated.
- the third sample is subjected to all the pre-plating processes up to this stage (indicated by an arrow C in FIG. 5 and indicated as (C) in FIG. 6), and then annealed in step S18. Ended.
- Step S17 an electroless NiP plating process is performed at a temperature of 80 ° C. for 27 minutes (Step S17), the Zn film is replaced with Ni, and Ni is continuously deposited on the surface of the front electrode 13, A NiP plating film was formed as the first metal film 21.
- a second metal film 22 was formed on the surface of the first metal film 21 by substitution Au plating treatment.
- the fourth sample was subjected to all the processes up to this stage (indicated by arrow D in FIG. 5 and indicated as (D) after plating in FIG. 6), and then annealed in step S18 to finish the process.
- the gate threshold voltage drop amount ⁇ Vth was calculated for these four samples. The result is shown in FIG.
- step S18 The process conditions in step S18, the BT test conditions, and the gate threshold voltage Vth measurement conditions are the same as in the first embodiment.
- FIG. 6 shows the gate threshold voltage drop amount ⁇ Vth of Comparative Example 2 (no plating / no annealing).
- the sample after plating (D) has the effect of suppressing the decrease in the gate threshold voltage Vth as in Example 1.
- the gate threshold voltage drop ⁇ Vth of the sample after etching (A), after acid cleaning (B), and after zincate (C) is as large as the gate threshold voltage drop ⁇ Vth of Comparative Example 2. It was confirmed that the same effect as the sample after plating (D) was not obtained. Thereby, it was confirmed that the variation of the gate threshold voltage Vth of the semiconductor device according to the present invention does not depend on the pretreatment for plating.
- Example 4 Next, the relationship between the constituent material of the first metal film 21 and the gate threshold voltage drop amount ⁇ Vth will be described.
- FIG. 7 is a chart showing electroless Cu plating conditions of Example 4.
- FIG. 8 is a characteristic diagram showing the relationship between the constituent material of the first metal film of the semiconductor device according to Example 4 and the gate threshold voltage.
- a SiC-MOSFET having a Cu plating film as the first metal film 21 was produced (hereinafter referred to as Example 4).
- steps S13 to S16 were performed in the same manner as in Example 1.
- cleaning, etching, acid cleaning, and zincate (hereinafter referred to as first zincate) were performed as plating pretreatments.
- the etching conditions at this time were 50 ° C. for 50 seconds, and the acid cleaning conditions were 21 ° C. for 30 seconds.
- acid cleaning was performed again using a nitric acid solution at a temperature of 21 ° C. for 60 seconds, and the Zn film formed on the surface of the front electrode 13 was removed.
- a second zincate was performed at a temperature of 21 ° C. for 45 seconds, and a Zn film was formed on the surface of the front electrode 13 again.
- Step S17 an electroless Cu plating process is performed at a temperature of 60 ° C. for 60 minutes (Step S17), the Zn film is replaced with Cu, and Cu is continuously deposited on the surface of the front electrode 13; A Cu plating film was formed as the first metal film 21.
- Example 4 was produced by performing annealing of Step S18.
- the gate threshold voltage Vth before and after the BT test was measured. The result is shown in FIG.
- the process conditions in step S18, the BT test conditions, and the gate threshold voltage Vth measurement conditions are the same as in the first embodiment.
- Example 8 shows, for comparison, the gate threshold voltage Vth before and after the BT test of Example 3 after plating (D) in which a NiP plating film was formed as the first metal film 21, and the above Comparative Example 2 (no plating / And the gate threshold voltage Vth before and after the BT test.
- Example 4 has a smaller gate threshold voltage drop amount ⁇ Vth than Comparative Example 2, and the effect of suppressing the reduction of the gate threshold voltage Vth is obtained as in Example 3. Was confirmed. Thereby, it was confirmed that the variation of the gate threshold voltage Vth of the semiconductor device according to the present invention does not depend on the constituent material of the first metal film 21.
- FIG. 9 is a characteristic diagram showing the relationship between the area ratio of the first metal film of the semiconductor devices according to Examples 5 and 9 and the gate threshold voltage drop amount.
- FIG. 10 is a plan view illustrating the arrangement of the first metal film of the semiconductor device according to the fifth embodiment.
- a plurality of SiC-MOSFETs having an area ratio of the first metal film 21 of 10% or more were manufactured (hereinafter referred to as Example 5).
- samples were prepared in which the area ratio of the first metal film 21 was 10%, 20%, 30%, 46%, 74%, and 90%.
- a plurality of SiC chips having a configuration formed by the steps S13 to S16 were prepared. As shown in FIG. 10B, in this SiC chip, the exposed area of the front surface electrode 13 exposed to the source pad contact hole 23a of the passivation film 23 is 46 relative to the surface area S1 of the front surface electrode 13. %.
- Reference numeral 24 denotes a gate pad
- reference numeral 31 denotes an active region
- reference numeral 32 denotes a breakdown voltage structure. Therefore, in each SiC chip, the opening width of the source pad contact hole 23a is changed in order to obtain the above-described area ratio of the first metal film 21.
- the gate threshold voltage drop amount ⁇ Vth was calculated. The result is shown in FIG. 10A.
- FIG. 9 shows the gate threshold voltage drop amount ⁇ Vth of Comparative Example 2 (no plating and no annealing) as the area ratio of the first metal film 21 being 0%.
- the gate threshold voltage drop amount ⁇ Vth of Example 5 is smaller than the gate threshold voltage drop amount ⁇ Vth of Comparative Example 2 and the area ratio of the first metal film 21 is increased. It was confirmed that the gate threshold voltage drop amount ⁇ Vth can be reduced.
- the relationship between the area ratio of the first metal film 21 and the gate threshold voltage decrease amount ⁇ Vth is set such that the area ratio of the first metal film 21 is x and the gate threshold voltage decrease amount ⁇ Vth is When y, it is expressed by the following (1) (curve indicated by reference numeral 41 in FIG. 9).
- FIG. 11 is a characteristic diagram illustrating the relationship between the annealing atmosphere of the semiconductor device according to Example 6 and the gate threshold voltage drop amount.
- Example 6 a plurality of SiC-MOSFETs were manufactured by changing the annealing atmosphere in step S18 in various ways (hereinafter referred to as Example 6). Specifically, as Example 6, three samples were prepared that were annealed in step S18 in an N 2 gas atmosphere, a vacuum atmosphere, and an Ar atmosphere.
- the configuration of the sample annealed in the N 2 gas atmosphere is the same as that of the first embodiment.
- the configuration of the sample annealed in a vacuum atmosphere or an Ar atmosphere other than the atmosphere in the annealing in step S18 is the same as that in the first embodiment.
- gate threshold voltage fall amount (DELTA) Vth was computed, respectively.
- FIG. 11 shows, for comparison, a gate threshold voltage drop amount ⁇ Vth of a sample (hereinafter referred to as Comparative Example 3) in which the annealing atmosphere in Step S18 is a hydrogen (H 2 ) atmosphere, and Comparative Example 1 (plating).
- the gate threshold voltage drop amount ⁇ Vth with and without annealing is shown.
- the sample annealed in the N 2 gas atmosphere had the smallest gate threshold voltage drop amount ⁇ Vth. Therefore, it is preferable to perform the annealing in step S18 in an N 2 gas atmosphere or a mixed gas atmosphere containing N 2 .
- the sample annealed in the vacuum atmosphere or Ar gas atmosphere has a larger gate threshold voltage drop ⁇ Vth than the sample annealed in the N 2 gas atmosphere. Since the productivity can be improved as compared with annealing in an Ar gas atmosphere, the annealing in step S18 may be performed in a vacuum atmosphere or an Ar gas atmosphere.
- FIG. 12 is a characteristic diagram showing the relationship between the annealing temperature and annealing time of the semiconductor device according to Example 7-1 and the gate threshold voltage drop amount.
- FIG. 13 is a characteristic diagram showing the relationship between the annealing temperature and annealing time of the semiconductor device according to Example 7-2 and the gate threshold voltage drop amount.
- a plurality of SiC-MOSFETs were manufactured by changing the annealing temperature and annealing time in step S18 variously (hereinafter referred to as Example 7).
- Example 7-1 a plurality of samples were prepared in which the annealing temperature in step S18 was in the range of 280 ° C. to 450 ° C. and the annealing time was 0.5 hours to 6 hours, and the gate The threshold voltage drop amount ⁇ Vth was calculated.
- the BT test conditions of Example 7-1 are the same as those of Example 1. The result is shown in FIG.
- Example 7-2 a plurality of samples were prepared in which the annealing temperature in step S18 was in the range of 280 ° C. to 330 ° C., and the annealing time was in the range of 0.5 hours to 6 hours, The threshold voltage drop amount ⁇ Vth was calculated.
- the BT temperature was 150 ° C.
- the voltage applied to the gate electrode was ⁇ 10 V
- the treatment time was 10 minutes. The result is shown in FIG.
- the gate threshold voltage comparable to the other combinations based on the gate threshold voltage drop amount ⁇ Vth in the other combinations of annealing temperature and annealing time in the figure. Since it is clear that the decrease amount ⁇ Vth can be obtained, the gate threshold voltage decrease amount ⁇ Vth is not calculated.
- the configuration other than the annealing temperature and annealing time in step S18 of Examples 7-1 and 7-2 is the same as that of Example 1.
- the gate threshold voltage Vth is lowered more than before by setting the annealing temperature within the range of 150 ° C. or more and 450 ° C. or less and the annealing time being 0.5 hour or more and 6 hours or less. It was confirmed that it can be suppressed.
- the gate threshold voltage drop amount ⁇ Vth is smaller than ⁇ 4 V, which is a voltage value at which normally-on, for example.
- the gate threshold voltage drop amount ⁇ Vth is preferably smaller than ⁇ 0.03V, for example. That is, it is preferable that the annealing temperature is in the range of 300 ° C. or higher and 420 ° C. or lower and the annealing time is in the range of 1 hour or longer and 3 hours or shorter, as shown in FIGS. Thereby, the gate threshold voltage drop amount ⁇ Vth can be suppressed to such an extent that normally-off can be maintained.
- the first metal film is formed on the surface of the front surface electrode, and further annealed in an N 2 atmosphere or the like.
- the first metal film is formed on the surface of the front electrode, thereby suppressing the decrease in the gate threshold voltage. Therefore, for example, even when an SiC chip (SiC substrate) having a MOSFET element structure is obtained, the effect of suppressing the decrease in the gate threshold voltage can be obtained by applying the present invention.
- the exposed area of the front electrode is increased or decreased by increasing the opening width of the source pad contact hole or covering the surface of the front electrode with the insulating film.
- the area ratio of the metal film can be adjusted. For this reason, for example, even when an SiC chip having a MOSFET element structure is obtained, the first metal film can be easily made to have a desired area ratio.
- FIG. 14 is a flowchart illustrating an outline of a method of manufacturing a semiconductor device according to the second embodiment.
- the manufacturing method of the semiconductor device according to the second embodiment is different from the manufacturing method of the semiconductor device according to the first embodiment in that after forming the front electrode 13 (step S13), a passivation film is formed (step S13).
- the first annealing (step S19) is performed before S14).
- the annealing temperature of the first annealing is higher than the annealing temperature of annealing in step S18 (hereinafter referred to as second annealing), and may be, for example, 350 ° C. or higher. Conditions other than the annealing temperature of the first annealing may be the same as those of the second annealing.
- FIG. 15 is a characteristic diagram illustrating the gate threshold voltage drop amount of the semiconductor device according to Working Example 8.
- a SiC-MOSFET was manufactured according to the method for manufacturing a semiconductor device according to the second embodiment (hereinafter referred to as Example 8).
- Example 8 is the same as Example 1 except that the first annealing of Step S19 is performed. That is, in Example 8, the first annealing is performed after the formation of the front electrode 13, and the second annealing is performed after the formation of the first metal film 21.
- Example 8 the gate threshold voltage drop amount ⁇ Vth was calculated.
- the result is shown in FIG. FIG. 15 also shows the gate threshold voltage drop amount ⁇ Vth of Example 1 in which only the second annealing was performed. From the results shown in FIG. 15, it was confirmed that by performing both the first annealing and the second annealing, the gate threshold voltage decrease amount ⁇ Vth after applying a negative voltage to the gate electrode can be further reduced. .
- Example 9 Next, the relationship between the area ratio of the first metal film 21 and the gate threshold voltage drop amount ⁇ Vth will be described.
- a plurality of Examples 9-1 and 9-2 in which the area ratio of the first metal film 21 was 46% or more were manufactured.
- samples in which the area ratio of the first metal film 21 was 46%, 74%, and 90% were prepared.
- the first annealing was performed at a temperature of 350 ° C. for 1 hour.
- the second annealing was performed at a temperature of 300 ° C. for 3 hours.
- the method for adjusting the area ratio of the first metal film 21 is the same as in the fifth embodiment.
- the gate threshold voltage drop amount ⁇ Vth was calculated for Examples 9-1 and 9-2. The result is shown in FIG.
- the BT test conditions of Example 9-1 were such that the BT temperature was 200 ° C. and the voltage applied to the gate electrode was ⁇ 20V.
- the BT test conditions of Example 9-2 were a BT temperature of 175 ° C. and a voltage applied to the gate electrode of ⁇ 10V.
- the measurement conditions for the gate threshold voltage Vth are the same as in the first embodiment.
- Example 9 the gate threshold voltage drop amount ⁇ Vth is reduced as the area ratio of the first metal film 21 is increased. It was confirmed that for example, in Example 9-1, the relationship between the area ratio of the first metal film 21 and the gate threshold voltage decrease amount ⁇ Vth is represented by x as the area ratio of the first metal film 21. When ⁇ Vth is y, it is expressed by the following (2) (curve indicated by reference numeral 42 in FIG. 9).
- Example 9-2 the relationship between the area ratio of the first metal film 21 and the gate threshold voltage decrease amount ⁇ Vth is set such that the area ratio of the first metal film 21 is x, and the gate threshold voltage decrease amount is When ⁇ Vth is y, it is expressed by the following (3) (curve indicated by reference numeral 43 in FIG. 9).
- the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
- the MOSFET is configured using the SiC substrate serving as the n drain region, but the MOSFET may be configured using the SiC substrate serving as the n ⁇ drift layer.
- the SiC-MOSFET has been described as an example.
- the present invention is not limited to the above-described embodiment, and can be applied to, for example, a MOS semiconductor device having a MOS gate structure such as an IGBT.
- the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a MOS type semiconductor device using an SiC semiconductor.
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Abstract
Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図1に示すように、実施の形態1にかかる半導体装置は、nドレイン領域となるSiC基板1のおもて面上にn-ドリフト層となるn-エピタキシャル層2を堆積してなるエピタキシャル基板を用いて作製(製造)されたSiC-MOSFETである。エピタキシャル基板のおもて面側(n-エピタキシャル層2側)の表面層には、pベース領域3が選択的に設けられている。また、エピタキシャル基板のおもて面上には、n-エピタキシャル層2の、隣り合うpベース領域3に挟まれた部分からpベース領域3にわたってpエピタキシャル層4が堆積されている。
次に、実施例1にかかる半導体装置のゲートしきい値電圧Vthについて説明する。図3は、実施例1にかかる半導体装置のゲートしきい値電圧について示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、SiC-MOSFETを作製した(以下、実施例1とする)。実施例1は、ステップS17の工程において無電解NiPめっき処理により第1金属膜21としてNiPめっき膜を形成し、ステップS18の工程においてN2雰囲気のアニールを行っている(めっきあり・アニールあり)。第1金属膜21の面積比率(=S2/S1)を46%とした。
次に、第1金属膜21の膜厚とゲートしきい値電圧低下量ΔVthとの関係について説明する。図4は、実施例2にかかる半導体装置の第1金属膜の膜厚とゲートしきい値電圧低下量との関係を示す特性図である。上述した実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21の膜厚の異なる複数のSiC-MOSFETを作製した(以下、実施例2とする)。具体的には、実施例2として、第1金属膜21の膜厚がそれぞれ1μm、4.5μmおよび10μmの3つの試料を用意した。実施例2の第1金属膜21の膜厚以外の構成は、実施例1と同様である。
次に、めっき前処理とゲートしきい値電圧低下量ΔVthとの関係について説明する。図5は、実施例3の無電解NiPめっき処理条件を示す図表である。図6は、実施例3にかかる半導体装置の第1金属膜におけるめっき前処理とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、めっき前処理工程の一部の工程を省略した複数のSiC-MOSFETを作製した(以下、実施例3とする)。具体的には、実施例3として、めっき前処理を異なるタイミングで終了した後、ステップS17の工程を行わずにステップS18を行った3つの試料を用意した。
次に、第1金属膜21の構成材料とゲートしきい値電圧低下量ΔVthとの関係について説明する。図7は、実施例4の無電解Cuめっき処理条件を示す図表である。図8は、実施例4にかかる半導体装置の第1金属膜の構成材料とゲートしきい値電圧との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21としてCuめっき膜を形成したSiC-MOSFETを作製した(以下、実施例4とする)。
次に、第1金属膜21の面積比率とゲートしきい値電圧低下量ΔVthとの関係について説明する。図9は、実施例5,9にかかる半導体装置の第1金属膜の面積比率とゲートしきい値電圧低下量との関係を示す特性図である。図10は、実施例5にかかる半導体装置の第1金属膜の配置を示す平面図である。実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21の面積比率を10%以上とした複数のSiC-MOSFETを作製した(以下、実施例5とする)。具体的には、実施例5として、第1金属膜21の面積比率を10%、20%、30%、46%、74%および90%とした各試料を用意した。
次に、ステップS18のアニールの雰囲気とゲートしきい値電圧低下量ΔVthとの関係について説明する。図11は、実施例6にかかる半導体装置のアニールの雰囲気とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがって、ステップS18のアニールの雰囲気を種々変更して複数のSiC-MOSFETを作製した(以下、実施例6とする)。具体的には、実施例6として、N2ガス雰囲気、真空雰囲気およびAr雰囲気においてステップS18のアニールを行った3つの試料を用意した。
次に、ステップS18のアニール温度およびアニール時間とゲートしきい値電圧低下量ΔVthとの関係について説明する。図12は、実施例7-1にかかる半導体装置のアニール温度およびアニール時間とゲートしきい値電圧低下量との関係を示す特性図である。図13は、実施例7-2にかかる半導体装置のアニール温度およびアニール時間とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがって、ステップS18のアニール温度およびアニール時間を種々変更して複数のSiC-MOSFETを作製した(以下、実施例7とする)。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図14は、実施の形態2にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、おもて面電極13を形成した(ステップS13)後、パッシベーション膜を形成する(ステップS14)前に、第1アニール(ステップS19)を行う点である。第1アニールのアニール温度は、ステップS18のアニール(以下、第2アニールとする)のアニール温度よりも高く、例えば350℃以上であってもよい。第1アニールのアニール温度以外の条件は、第2アニールと同様であってもよい。
次に、実施例8にかかる半導体装置のゲートしきい値電圧低下量ΔVthについて説明する。図15は、実施例8にかかる半導体装置のゲートしきい値電圧低下量について示す特性図である。実施の形態2にかかる半導体装置の製造方法にしたがい、SiC-MOSFETを作製した(以下、実施例8とする)。実施例8は、ステップS19の第1アニールを行う以外は実施例1と同様である。すなわち、実施例8においては、おもて面電極13の形成後に第1アニールを行い、かつ第1金属膜21の形成後に第2アニールを行っている。
次に、第1金属膜21の面積比率とゲートしきい値電圧低下量ΔVthとの関係について説明する。実施の形態2にかかる半導体装置の製造方法にしたがい、第1金属膜21の面積比率を46%以上とした複数の実施例9-1,9-2を作製した。具体的には、実施例9-1,9-2として、第1金属膜21の面積比率を46%、74%および90%とした各試料を用意した。第1アニールは、350℃の温度で1時間とした。第2アニールは、300℃の温度で3時間とした。第1金属膜21の面積比率の調整方法は実施例5と同様である。
2 n-エピタキシャル層
3 pベース領域
4 pエピタキシャル層
5 n++ソース領域
6 p+コンタクト領域
7 n打ち返し領域
8 ゲート絶縁膜
9 ゲート電極
10 層間絶縁膜
11 TiN膜
12 Ni膜
13 おもて面電極
14 コンタクト金属膜
15 裏面電極
21 第1金属膜
22 第2金属膜
23 パッシベーション膜
23a ソースパッドコンタクトホール
25 絶縁膜
S1 おもて面電極の表面積
S2 第1金属膜の表面積
Claims (9)
- 炭化珪素基板のおもて面にゲート絶縁膜およびゲート電極からなる絶縁ゲート構造を形成する第1工程と、
前記炭化珪素基板のおもて面に、層間絶縁膜によって前記ゲート電極と絶縁された、アルミニウムまたはアルミニウム合金からなるおもて面電極を形成する第2工程と、
前記おもて面電極の表面に、ニッケル、ニッケル合金、銅、パラジウム、チタン、白金、金または銀からなる金属膜、または、これらの金属からなる金属膜を2層以上積層してなる金属積層膜を形成する第3工程と、
前記第3工程後、窒素ガス雰囲気、窒素を含む混合ガス雰囲気、真空雰囲気またはアルゴンガス雰囲気のアニールを行う第4工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第2工程後、前記第3工程前に、窒素ガス雰囲気、窒素を含む混合ガス雰囲気、真空雰囲気またはアルゴンガス雰囲気のアニールを行う第5工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5工程のアニール温度は、前記第4工程のアニール温度よりも高いことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第5工程のアニール温度は、350℃以上であることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第4工程のアニール温度は、150℃以上450℃以下であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第4工程のアニール温度は、300℃以上420℃以下であることを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記第3工程では、前記おもて面電極の表面の60%以上90%以下の範囲を覆う前記金属膜または前記金属積層膜を形成することを特徴とする請求項1~6のいずれか一つに記載の半導体装置の製造方法。
- 炭化珪素基板のおもて面に設けられたゲート絶縁膜およびゲート電極からなる絶縁ゲート構造と、
前記炭化珪素基板のおもて面に設けられ、層間絶縁膜によって前記ゲート電極と絶縁された、アルミニウムまたはアルミニウム合金からなるおもて面電極と、
前記おもて面電極の表面に、前記おもて面電極の表面の60%以上の範囲を覆うように設けられた、ニッケル、ニッケル合金、銅、パラジウム、チタン、白金、金または銀からなる金属膜、または、これらの金属からなる金属膜を2層以上積層してなる金属積層膜と、
を備えることを特徴とする半導体装置。 - 前記おもて面電極の表面の90%以下の範囲は、前記金属膜または前記金属積層膜によって覆われていることを特徴とする請求項8に記載の半導体装置。
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CN105009295B (zh) | 2017-10-10 |
US10355089B2 (en) | 2019-07-16 |
DE112014001741T8 (de) | 2016-02-18 |
JP6350713B2 (ja) | 2018-07-04 |
JP6480860B2 (ja) | 2019-03-13 |
CN105009295A (zh) | 2015-10-28 |
JPWO2014156791A1 (ja) | 2017-02-16 |
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