WO2020208995A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020208995A1
WO2020208995A1 PCT/JP2020/010569 JP2020010569W WO2020208995A1 WO 2020208995 A1 WO2020208995 A1 WO 2020208995A1 JP 2020010569 W JP2020010569 W JP 2020010569W WO 2020208995 A1 WO2020208995 A1 WO 2020208995A1
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Prior art keywords
film
main surface
region
semiconductor substrate
semiconductor device
Prior art date
Application number
PCT/JP2020/010569
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English (en)
French (fr)
Inventor
光彦 酒井
Original Assignee
住友電気工業株式会社
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Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP2021513524A priority Critical patent/JP7439825B2/ja
Priority to US17/601,134 priority patent/US20220181279A1/en
Publication of WO2020208995A1 publication Critical patent/WO2020208995A1/ja

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Definitions

  • Patent Document 1 Patent No. 6239214 describes a semiconductor device.
  • the semiconductor device described in Patent Document 1 includes a semiconductor substrate formed of single crystal silicon carbide (SiC), an aluminum (Al) electrode formed on the semiconductor substrate and having an upper surface, and an upper surface of the aluminum electrode. It has a polyimide film having an opening that covers the peripheral edge and exposes the upper surface of the aluminum electrode, and a copper (Cu) film formed on the upper surface of the aluminum electrode that is exposed from the opening of the polyimide film.
  • the reliability of the polyimide film deteriorates due to the diffusion of copper in the copper film into the polyimide film. Therefore, in the semiconductor device described in Patent Document 1, the copper film is formed so as to be separated from the polyimide film, so that the diffusion of copper into the polyimide film is prevented.
  • the semiconductor device of the present disclosure has a semiconductor substrate having a first main surface, a first surface facing the first main surface, and a second surface opposite to the first surface, and is a semiconductor substrate.
  • a passivation film having an aluminum electrode arranged above and an opening that covers the periphery of the second surface and exposes a part of the second surface, and a passivation film separated from the passivation film on the second surface exposed from the opening. It includes an arranged copper film and a metal film arranged on a second surface exposed from between the passivation film and the copper film.
  • the metal film is composed of at least one selected from the group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film and a titanium nitride film.
  • FIG. 1 is a top view of the semiconductor device according to the embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
  • FIG. 3 is a cross-sectional view taken along the line III-III of FIG.
  • FIG. 4 is a cross-sectional view showing a detailed internal structure of the semiconductor device according to the embodiment.
  • FIG. 5 is a first cross-sectional view showing a state of external connection of the semiconductor device according to the embodiment.
  • FIG. 6 is a second cross-sectional view showing a state of external connection of the semiconductor device according to the embodiment.
  • FIG. 7 is a process diagram of a method for manufacturing a semiconductor device according to the embodiment.
  • FIG. 8 is a cross-sectional view of the semiconductor device according to the embodiment in the transistor forming step S1.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the embodiment in the interlayer insulating film forming step S2.
  • FIG. 10 is a cross-sectional view of the semiconductor device according to the embodiment in the aluminum electrode forming step S3.
  • FIG. 11 is a cross-sectional view of the semiconductor device according to the embodiment in the passivation film forming step S4.
  • FIG. 12 is a cross-sectional view of the semiconductor device according to the embodiment in the copper film forming step S5.
  • FIG. 13 is a cross-sectional view of the semiconductor device according to the comparative example.
  • An object of the present disclosure is to provide a semiconductor device capable of improving heat dissipation from an aluminum electrode while suppressing diffusion of copper from a copper film into a passivation film.
  • the semiconductor device includes a semiconductor substrate having a first main surface, a first surface facing the first main surface, and a second surface opposite to the first main surface.
  • a passivation film having an aluminum electrode arranged on the semiconductor substrate, an opening covering the peripheral edge of the second surface and exposing a part of the second surface, and a passivation film on the second surface exposed from the opening. It includes a copper film arranged apart from the passivation film and a metal film arranged on a second surface exposed from between the passivation film and the copper film.
  • the metal film is composed of at least one selected from the group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film and a titanium nitride film.
  • the semiconductor device of (1) above it is possible to improve the heat dissipation from the aluminum electrode while suppressing the diffusion of copper from the copper film into the passivation film.
  • the passivation film may be a polyimide film.
  • the metal film may be an electroless nickel plating film. In this case, the metal film can be formed without performing patterning.
  • the semiconductor substrate may be a silicon carbide semiconductor substrate.
  • the semiconductor device of the above (1) to (4) may further include a gate and a gate insulating film.
  • the semiconductor substrate has a second main surface opposite to the first main surface, a source region arranged on the first main surface, a drain region constituting the second main surface, and a first main of the drain region. It may have a drift region arranged on the surface side and a body region that separates the drift region and the source region.
  • the gate may face a portion of the body region between the drift region and the source region via a gate insulating film.
  • the aluminum electrode may be electrically connected to the source region.
  • a semiconductor substrate having a first main surface, a first surface facing the first main surface, and a second surface opposite to the first main surface are provided.
  • a passivation film having an aluminum electrode arranged on a semiconductor substrate, a passivation film having an opening covering the periphery of the second surface and exposing a part of the second surface, and a passivation on the second surface exposed from the opening. It includes a copper film arranged apart from the film, a metal film arranged on a second surface exposed from between the passivation film and the copper film, a gate, and a gate insulating film.
  • the metal film is composed of at least one selected from the group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film and a titanium nitride film.
  • the passivation film is a polyimide film.
  • the semiconductor substrate has a second main surface opposite to the first main surface, a source region arranged on the first main surface, a drain region constituting the second main surface, and a first main of the drain region. It has a drift region arranged on the surface side and a body region that separates the drift region and the source region.
  • the gate faces a portion of the body region between the drift region and the source region via a gate insulating film.
  • the aluminum electrode is electrically connected to the source region.
  • a semiconductor substrate having a first main surface, a first surface facing the first main surface, and a second surface opposite to the first main surface are provided.
  • a passivation film having an aluminum electrode arranged on a semiconductor substrate, a passivation film having an opening covering the periphery of the second surface and exposing a part of the second surface, and a passivation on the second surface exposed from the opening. It includes a copper film arranged apart from the film, a metal film arranged on a second surface exposed from between the passivation film and the copper film, a gate, and a gate insulating film.
  • the metal film is composed of at least one selected from the group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film and a titanium nitride film.
  • the passivation film is a polyimide film.
  • the metal film is an electroless nickel plating film.
  • the semiconductor substrate is a silicon carbide semiconductor substrate.
  • the semiconductor substrate has a second main surface opposite to the first main surface, a source region arranged on the first main surface, a drain region constituting the second main surface, and a first main of the drain region. It has a drift region arranged on the surface side and a body region that separates the drift region and the source region.
  • the gate faces a portion of the body region between the drift region and the source region via a gate insulating film.
  • the aluminum electrode is electrically connected to the source region.
  • FIG. 1 is a top view of the semiconductor device according to the embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
  • the semiconductor device according to the embodiment includes a semiconductor substrate 1, a first aluminum electrode 2, a passivation film 3, a copper film 4, a metal film 5, and a second aluminum electrode. It has 6 and a 3rd aluminum electrode 7.
  • the semiconductor substrate 1 is formed of, for example, single crystal silicon carbide.
  • the semiconductor substrate 1 has a first main surface 1a and a second main surface 1b.
  • the second main surface 1b is the opposite surface of the first main surface 1a.
  • the first aluminum electrode 2 is arranged on the semiconductor substrate 1. Specifically, the first aluminum electrode 2 is formed on the first main surface 1a of the semiconductor substrate 1.
  • the first aluminum electrode 2 is made of pure aluminum or an aluminum alloy.
  • the first aluminum electrode 2 has a first surface 2a and a second surface 2b.
  • the first surface 2a is a surface facing the first main surface 1a.
  • the second surface 2b is the opposite surface of the first surface 2a.
  • the passivation film 3 is arranged on the semiconductor substrate 1. Specifically, the passivation film 3 covers the peripheral edge of the second surface 2b of the first aluminum electrode 2. The passivation film 3 has an opening 3a that exposes a part of the second surface 2b of the first aluminum electrode 2.
  • the passivation film 3 is formed of, for example, polyimide. However, the passivation film 3 is not limited to this.
  • the passivation film 3 may be formed of an insulating resin material other than polyimide.
  • the passivation film 3 may be formed of a silicon oxide (SiO 2 ), a silicon nitride (Si 3 N 4 ), a silicon oxynitride (SiO N), or the like.
  • the copper film 4 is formed on the first aluminum electrode 2. More specifically, the copper film 4 is arranged on the second surface 2b of the first aluminum electrode 2 exposed from the opening 3a. The copper film 4 is arranged apart from the passivation film 3. That is, the second surface 2b of the first aluminum electrode 2 is exposed from between the passivation film 3 and the copper film 4.
  • the copper film 4 is formed of pure copper or a copper alloy.
  • the metal film 5 is arranged on the first aluminum electrode 2. More specifically, the metal film 5 is formed on the second surface 2b of the first aluminum electrode 2 exposed from between the passivation film 3 and the copper film 4. The metal film 5 is preferably in contact with the copper film 4 and the passivation film 3.
  • the metal film 5 is at least selected from the group consisting of a nickel (Ni) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, a tungsten (W) film, a titanium (Ti) film, and a titanium nitride (TiN) film. It is composed of a kind.
  • the metal film 5 is preferably an electroless nickel plating film.
  • the electroless nickel plating film is a nickel film formed by an electroless plating method.
  • the metal film 5 is not limited to the above.
  • the material constituting the metal film 5 can be appropriately selected so that the diffusion coefficient of copper in the metal film 5 is smaller than the diffusion coefficient of copper in the passivation film 3.
  • the material constituting the metal film 5 may be appropriately selected so that the diffusion coefficient of the material in the passivation film 3 is smaller than the diffusion coefficient of copper in the passivation film 3.
  • FIG. 3 is a cross-sectional view taken along the line III-III of FIG.
  • the second aluminum electrode 6 is arranged on the semiconductor substrate 1. Specifically, the second aluminum electrode 6 is arranged on the first main surface 1a of the semiconductor substrate 1.
  • the second aluminum electrode 6 has a third surface 6a and a fourth surface 6b.
  • the third surface 6a is a surface facing the first main surface 1a.
  • the fourth surface 6b is the opposite surface of the third surface 6a.
  • the second aluminum electrode 6 is made of pure aluminum or an aluminum alloy.
  • the passivation film 3 further covers the peripheral edge of the fourth surface 6b of the second aluminum electrode 6.
  • the passivation film 3 further has an opening 3b that exposes a part of the fourth surface 6b of the second aluminum electrode 6.
  • a copper film is not formed on the fourth surface 6b of the second aluminum electrode 6 exposed from the opening 3b.
  • the third aluminum electrode 7 is arranged on the second main surface 1b of the semiconductor substrate 1.
  • the third aluminum electrode 7 is made of pure aluminum or an aluminum alloy.
  • FIG. 4 is a cross-sectional view showing a detailed internal structure of the semiconductor device according to the embodiment.
  • the semiconductor substrate 1 has a source region 11, a body region 12, a drain region 13, a drift region 14, and a body contact region 15.
  • the semiconductor device according to the embodiment further has a gate insulating film 16, a gate 17, and an interlayer insulating film 18.
  • the source region 11 is arranged on the first main surface 1a of the semiconductor substrate 1.
  • the conductive type of the source region 11 is the first conductive type.
  • the first conductive type is, for example, n type.
  • the body region 12 is arranged on the first main surface 1a of the semiconductor substrate 1.
  • the body region 12 surrounds the source region 11.
  • the conductive type of the body region 12 is the second conductive type.
  • the second conductive type is the opposite conductive type of the first conductive type. That is, the second conductive type is, for example, the p type.
  • the end face of the drain region 13 is the second main surface 1b.
  • the conductive type of the drain region 13 is the first conductive type.
  • the drain region 13 is electrically connected to the third aluminum electrode 7. That is, the third aluminum electrode 7 is a drain electrode of the semiconductor device according to the embodiment.
  • the drift region 14 surrounds the body region 12 and is arranged on the first main surface 1a of the semiconductor substrate 1. From another point of view, the drift region 14 is arranged on the drain region 13 (that is, the first main surface 1a side of the drain region 13), and the drift region 14 and the source region 11 are formed by the body region 12. It is separated.
  • the conductive type of the drift region 14 is the first conductive type.
  • the impurity concentration in the drift region 14 is lower than the impurity concentration in the source region 11 and the drain region 13.
  • the portion of the body region 12 located on the first main surface 1a of the semiconductor substrate 1 and sandwiched between the source region 11 and the drift region 14 is hereinafter referred to as a channel region.
  • the body contact region 15 is arranged on the first main surface 1a of the semiconductor substrate 1 between two adjacent source regions 11.
  • the body contact region 15 has a depth that reaches the body region 12.
  • the conductive type of the body contact region 15 is a second conductive type.
  • the impurity concentration in the body contact region 15 is higher than the impurity concentration in the body region 12.
  • the gate insulating film 16 is arranged on the first main surface 1a of the semiconductor substrate 1. More specifically, the gate insulating film 16 is arranged on the channel region.
  • the gate insulating film 16 is formed of, for example, a silicon oxide.
  • the gate 17 is arranged on the gate insulating film 16. That is, the gate 17 is arranged so as to face the channel region while being insulated by the gate insulating film 16.
  • the gate 17 is formed of, for example, polycrystalline silicon (Si) doped with impurities.
  • the gate 17 is electrically connected to the second aluminum electrode 6. That is, the second aluminum electrode 6 is a gate electrode of the semiconductor device according to the embodiment.
  • the source region 11, the body region 12, the drain region 13, the drift region 14, the gate insulating film 16 and the gate 17 constitute the transistor 10.
  • the transistor 10 is a planar gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the interlayer insulating film 18 is formed on the first main surface 1a of the semiconductor substrate 1.
  • the interlayer insulating film 18 covers the gate 17.
  • the interlayer insulating film 18 is formed of, for example, a silicon oxide.
  • a contact hole 18a is formed in the interlayer insulating film 18. The contact hole 18a penetrates the interlayer insulating film 18 in the thickness direction. The source region 11 and the body contact region 15 are exposed from the contact hole 18a.
  • the first aluminum electrode 2 is arranged on the interlayer insulating film 18.
  • the first aluminum electrode 2 is also arranged in the contact hole 18a.
  • the first aluminum electrode 2 is electrically connected to the source region 11 and the body contact region 15. That is, the first aluminum electrode 2 is a source electrode.
  • the semiconductor device according to the embodiment has been described as having a planar gate type power MOSFET, but the semiconductor device according to the embodiment has another semiconductor element. May be good.
  • the semiconductor device according to the embodiment may have a trench gate type power MOSFET.
  • the semiconductor device according to the embodiment may have a Schottky barrier diode.
  • FIG. 5 is a first cross-sectional view showing a state of external connection of the semiconductor device according to the embodiment.
  • the first aluminum electrode 2 is externally connected by wire bonding the bonding wire 8a to the copper film 4.
  • the bonding wire 8a is preferably made of pure copper or a copper alloy.
  • the number of bonding wires 8a is preferably a plurality.
  • the third aluminum electrode 7 is electrically connected to the base plate 9 by, for example, soldering.
  • FIG. 6 is a second cross-sectional view showing a state of external connection of the semiconductor device according to the embodiment.
  • the second aluminum electrode 6 is externally connected by wire bonding using the bonding wire 8b.
  • the bonding wire 8b is formed of, for example, pure aluminum or an aluminum alloy.
  • the semiconductor device, the bonding wire 8a and the bonding wire 8b according to the embodiment may be resin-sealed.
  • FIG. 7 is a process diagram of a method for manufacturing a semiconductor device according to the embodiment.
  • the method for manufacturing the semiconductor device according to the embodiment includes a transistor forming step S1, an interlayer insulating film forming step S2, an aluminum electrode forming step S3, a passivation film forming step S4, and a copper film forming. It has a step S5 and a metal film forming step S6.
  • FIG. 8 is a cross-sectional view of the semiconductor device according to the embodiment in the transistor forming step S1. As shown in FIG. 8, in the transistor forming step S1, the transistor 10 is formed.
  • the base material is prepared.
  • This substrate is formed of single crystal silicon carbide doped with impurities.
  • an epitaxial layer is formed on the base material.
  • the source region 11, the body region 12, and the body contact region 15 are formed by performing ion implantation and activation annealing on the epitaxial layer.
  • the portion of the epitaxial layer where ion implantation was not performed becomes the drift region 14, and the base material becomes the drain region 13.
  • the semiconductor substrate 1 is prepared.
  • the gate insulating film 16 is formed by thermally oxidizing the first main surface 1a of the semiconductor substrate 1.
  • the gate 17 is formed by forming a film of the material constituting the gate 17 by CVD (Chemical Vapor Deposition) or the like and patterning the material constituting the filmed gate 17.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the embodiment in the interlayer insulating film forming step S2.
  • the interlayer insulating film 18 is formed in the interlayer insulating film forming step S2.
  • the interlayer insulating film 18 is formed by forming a film of the material constituting the interlayer insulating film 18 by CVD or the like, and flattening the material constituting the film-deposited interlayer insulating film 18 by CMP (Chemical Mechanical Polishing) or the like. Is done by.
  • CMP Chemical Mechanical Polishing
  • FIG. 10 is a cross-sectional view of the semiconductor device according to the embodiment in the aluminum electrode forming step S3.
  • the first aluminum electrode 2 and the third aluminum electrode 7 are formed as shown in FIG.
  • the second aluminum electrode 6 is also formed in the aluminum electrode forming step S3.
  • the contact hole 18a is formed in the interlayer insulating film 18 by anisotropic etching or the like.
  • the materials constituting the first aluminum electrode 2 and the second aluminum electrode 6 are formed on the interlayer insulating film 18 by sputtering or the like. At the same time, it is embedded in the contact hole 18a.
  • the materials constituting the formed first aluminum electrode 2 and the second aluminum electrode 6 are patterned.
  • the third aluminum electrode 7 is formed by forming a film of a material constituting the third aluminum electrode 7 on the second main surface 1b of the semiconductor substrate 1 by sputtering or the like.
  • FIG. 11 is a cross-sectional view of the semiconductor device according to the embodiment in the passivation film forming step S4.
  • the passivation film 3 is formed in the passivation film forming step S4.
  • the passivation film 3 is coated with a polyimide film so as to cover the first aluminum electrode 2 and the second aluminum electrode 6, and the applied polyimide film is exposed and developed. Is formed by.
  • the passivation film 3 When the passivation film 3 is a silicon oxide, a silicon nitride, or a silicon oxynitride, the passivation film 3 forms a film of the material constituting the passivation film 3 by CVD or the like, and the formed passivation film 3 is formed. It is formed by opening the material constituting the above by etching.
  • FIG. 12 is a cross-sectional view of the semiconductor device according to the embodiment in the copper film forming step S5. As shown in FIG. 12, in the copper film forming step S5, the copper film 4 is formed.
  • the copper film 4 is formed by forming a film of the material constituting the copper film 4 by sputtering or the like and patterning the material constituting the formed copper film 4.
  • the metal film 5 is formed.
  • the metal film 5 is an electroless nickel-plated film
  • the metal film 5 performs a pretreatment such as a zincate treatment on the second surface 2b between the passivation film 3 and the copper film 4, and also applies nickel ions. It is formed by immersing the semiconductor device according to the embodiment in the plating solution containing the mixture. In this case, since the metal film 5 (electroless nickel plating film) grows only on the second surface 2b between the passivation film 3 and the copper film 4, it is not necessary to pattern the metal film 5.
  • the metal film 5 When the metal film 5 is formed of another material, the metal film 5 forms a film of the material constituting the metal film 5 by sputtering or the like, and patterns the material constituting the filmed metal film 5. Is formed by As a result, the structure of the semiconductor device according to the embodiment shown in FIGS. 1 to 4 is formed.
  • FIG. 13 is a cross-sectional view of the semiconductor device according to the comparative example.
  • the semiconductor device according to the comparative example has a sealing material 5a instead of the metal film 5.
  • the sealing material 5a is formed of an insulating resin material.
  • the remaining configuration of the semiconductor device according to the comparative example is the same as that of the semiconductor device according to the embodiment.
  • the sealing material 5a is arranged on the second surface 2b exposed from between the passing film 3 and the copper film 4, the copper film 4 and the passing film 3 are separated from each other. There is no contact, and the diffusion of copper from the copper film 4 into the passivation film 3 is suppressed.
  • the second surface 2b exposed from between the passivation film 3 and the copper film 4 is covered with the sealing material 5a formed of the resin material, the first The heat dissipation from the aluminum electrode 2 is reduced.
  • the metal film 5 is arranged on the second surface 2b between the passing film 3 and the copper film 4, the copper film 4 and the passing film 3 are in contact with each other. However, the diffusion of copper from the copper film 4 into the passivation film 3 is suppressed. In addition, since the metal film 5 is formed on the second surface 2b between the passivation film 3 and the copper film 4, heat dissipation from the first aluminum electrode 2 is less likely to be hindered. Therefore, according to the semiconductor device according to the embodiment, it is possible to improve the heat dissipation from the first aluminum electrode 2 while suppressing the diffusion of copper from the copper film 4 into the passivation film 3.
  • the metal film 5 is arranged on the second surface 2b between the passivation film 3 and the copper film 4, the area through which the current flows can be expanded. As compared with the semiconductor device according to the comparative example, it is possible to suppress an increase in the electric resistance value around the first aluminum electrode 2.
  • the metal film 5 is an electroless nickel plating film in the semiconductor device according to the embodiment, the patterning of the metal film 5 becomes unnecessary, so that the manufacturing process can be simplified.
  • 1 Semiconductor substrate 1a 1st main surface, 1b 2nd main surface, 2 1st aluminum electrode, 2a 1st surface, 2b 2nd surface, 3 Passion film, 3a, 3b opening, 4 copper film, 5 metal film, 5a Encapsulant, 6th 2nd aluminum electrode, 6a 3rd surface, 6b 4th surface, 7th 3rd aluminum electrode, 8a, 8b bonding wire, 9 base plate, 11 source area, 12 body area, 13 drain area, 14 drift Region, 15 body contact region, 16 gate insulating film, 17 gate, 18 interlayer insulating film, 18a contact hole, S1 transistor forming step, S2 interlayer insulating film forming step, S3 aluminum electrode forming step, S4 passion film forming step, S5 copper Film forming process, S6 metal film forming process, 10 transistors.

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Abstract

半導体装置は、第１主面を有する半導体基板と、第１主面に対向している第１面と、第１面の反対面である第２面とを有し、半導体基板上に配置されたアルミニウム電極と、第２面の周縁を覆い、第２面の一部を露出させる開口を有するパッシベーション膜と、開口から露出している第２面上にパッシベーション膜から離間して配置された銅膜と、パッシベーション膜と銅膜との間から露出している第２面上に配置された金属膜とを備える。金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている。

Description

半導体装置
　本開示は、半導体装置に関する。本出願は、２０１９年４月８日に出願した日本特許出願である特願２０１９－０７３３９９号に基づく優先権を主張する。当該日本特許出願に記載された全ての記載内容は、参照によって本明細書に援用される。
　特許文献１（特許第６２３９２１４号公報）には、半導体装置が記載されている。特許文献１に記載の半導体装置は、単結晶の炭化珪素（ＳｉＣ）により形成された半導体基板と、半導体基板上に形成されているとともに上面を有するアルミニウム（Ａｌ）電極と、アルミニウム電極の上面の周縁を覆うとともに、アルミニウム電極の上面を露出させる開口を有するポリイミド膜と、ポリイミド膜の開口から露出するアルミニウム電極の上面上に形成された銅（Ｃｕ）膜とを有している。銅膜中の銅がポリイミド膜中へと拡散することにより、ポリイミド膜の信頼性が劣化する。そのため、特許文献１に記載の半導体装置においては、銅膜をポリイミド膜から離間して形成することにより、ポリイミド膜中への銅の拡散が防止されている。
特許第６２３９２１４号公報
　本開示の半導体装置は、第１主面を有する半導体基板と、第１主面に対向している第１面と第１面の反対面である第２面とを有しており、半導体基板上に配置されたアルミニウム電極と、第２面の周縁を覆い、第２面の一部を露出させる開口を有するパッシベーション膜と、開口から露出している第２面上にパッシベーション膜から離間して配置された銅膜と、パッシベーション膜と銅膜との間から露出している第２面上に配置された金属膜とを備える。金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている。
図１は、実施形態に係る半導体装置の上面図である。 図２は、図１のＩＩ－ＩＩに沿う断面図である。 図３は、図１のＩＩＩ－ＩＩＩに沿う断面図である。 図４は、実施形態に係る半導体装置の詳細な内部構造を示す断面図である。 図５は、実施形態に係る半導体装置の外部接続の状況を示す第１の断面図である。 図６は、実施形態に係る半導体装置の外部接続の状況を示す第２の断面図である。 図７は、実施形態に係る半導体装置の製造方法の工程図である。 図８は、トランジスタ形成工程Ｓ１における実施形態に係る半導体装置の断面図である。 図９は、層間絶縁膜形成工程Ｓ２における実施形態に係る半導体装置の断面図である。 図１０は、アルミニウム電極形成工程Ｓ３における実施形態に係る半導体装置の断面図である。 図１１は、パッシベーション膜形成工程Ｓ４における実施形態に係る半導体装置の断面図である。 図１２は、銅膜形成工程Ｓ５における実施形態に係る半導体装置の断面図である。 図１３は、比較例に係る半導体装置の断面図である。
　［本開示が解決しようとする課題］
　特許文献１に記載の半導体装置において、ポリイミド膜と銅膜との間には、封止部材が充填されている。封止部材は樹脂材料により形成されているため、特許文献１に記載の半導体装置は、アルミニウム電極からの放熱性に改善の余地がある。
　本開示の目的は、銅膜からパッシベーション膜中への銅の拡散を抑制しつつ、アルミニウム電極からの放熱性を改善することが可能な半導体装置を提供することである。
　［本開示の効果］
　本開示の半導体装置によると、銅膜からパッシベーション膜中への銅の拡散を抑制しつつ、アルミニウム電極からの放熱性を改善することができる。
　［本開示の実施形態の説明］
　まず、本開示の実施形態を列記して説明する。
　（１）一実施形態に係る半導体装置は、第１主面を有する半導体基板と、第１主面に対向している第１面と、第１面の反対面である第２面とを有し、半導体基板上に配置されたアルミニウム電極と、第２面の周縁を覆い、第２面の一部を露出させる開口を有するパッシベーション膜と、開口から露出している第２面上にパッシベーション膜から離間して配置された銅膜と、パッシベーション膜と銅膜との間から露出している第２面上に配置された金属膜とを備えている。金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている。
　上記（１）の半導体装置によると、銅膜からパッシベーション膜中への銅の拡散を抑制しつつ、アルミニウム電極からの放熱性を改善することができる。
　（２）上記（１）の半導体装置において、パッシベーション膜は、ポリイミド膜であってもよい。
　（３）上記（１）又は上記（２）の半導体装置において、金属膜は、無電解ニッケルめっき膜であってもよい。この場合、パターンニングを行うことなく金属膜を形成することができる。
　（４）上記（１）～上記（３）の半導体装置において、半導体基板は、炭化珪素半導体基板であってもよい。
　（５）上記（１）～上記（４）の半導体装置は、ゲートと、ゲート絶縁膜とをさらに備えていてもよい。半導体基板は、第１主面の反対面である第２主面と、第１主面に配置されたソース領域と、第２主面を構成しているドレイン領域と、ドレイン領域の第１主面側に配置されたドリフト領域と、ドリフト領域とソース領域とを分離するボディ領域とを有していてもよい。ゲートは、ドリフト領域とソース領域との間にあるボディ領域の部分とゲート絶縁膜を介して対向していてもよい。アルミニウム電極は、ソース領域に電気的に接続されていてもよい。
　（６）他の実施形態に係る半導体装置は、第１主面を有する半導体基板と、第１主面に対向している第１面と、第１面の反対面である第２面とを有し、半導体基板上に配置されたアルミニウム電極と、第２面の周縁を覆い、第２面の一部を露出させる開口を有するパッシベーション膜と、開口から露出している第２面上にパッシベーション膜から離間して配置された銅膜と、パッシベーション膜と銅膜との間から露出している第２面上に配置された金属膜と、ゲートと、ゲート絶縁膜とを備えている。金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている。パッシベーション膜は、ポリイミド膜である。半導体基板は、第１主面の反対面である第２主面と、第１主面に配置されたソース領域と、第２主面を構成しているドレイン領域と、ドレイン領域の第１主面側に配置されたドリフト領域と、ドリフト領域とソース領域とを分離するボディ領域とを有する。ゲートは、ドリフト領域とソース領域との間にあるボディ領域の部分とゲート絶縁膜を介して対向している。アルミニウム電極は、ソース領域に電気的に接続されている。
　（７）他の実施形態に係る半導体装置は、第１主面を有する半導体基板と、第１主面に対向している第１面と、第１面の反対面である第２面とを有し、半導体基板上に配置されたアルミニウム電極と、第２面の周縁を覆い、第２面の一部を露出させる開口を有するパッシベーション膜と、開口から露出している第２面上にパッシベーション膜から離間して配置された銅膜と、パッシベーション膜と銅膜との間から露出している第２面上に配置された金属膜と、ゲートと、ゲート絶縁膜とを備えている。金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている。パッシベーション膜は、ポリイミド膜である。金属膜は、無電解ニッケルめっき膜である。半導体基板は、炭化珪素半導体基板である。半導体基板は、第１主面の反対面である第２主面と、第１主面に配置されたソース領域と、第２主面を構成しているドレイン領域と、ドレイン領域の第１主面側に配置されたドリフト領域と、ドリフト領域とソース領域とを分離するボディ領域とを有する。ゲートは、ドリフト領域とソース領域との間にあるボディ領域の部分とゲート絶縁膜を介して対向している。アルミニウム電極は、ソース領域に電気的に接続されている。
　［本開示の実施形態の詳細］
　本開示の実施形態の詳細を、図面を参酌しながら説明する。以下の図面においては、同一又は相当する部分に同一の参照符号を付し、重複する説明は繰り返さない。
　（実施形態に係る半導体装置の構成）
　以下に、実施形態に係る半導体装置の構成を説明する。
　＜実施形態に係る半導体装置の概略構成＞
　図１は、実施形態に係る半導体装置の上面図である。図２は、図１のＩＩ－ＩＩに沿う断面図である。図１及び図２に示されるように、実施形態に係る半導体装置は、半導体基板１と、第１アルミニウム電極２と、パッシベーション膜３と、銅膜４と、金属膜５と、第２アルミニウム電極６と、第３アルミニウム電極７とを有している。
　半導体基板１は、例えば、単結晶の炭化珪素により形成されている。半導体基板１は、第１主面１ａと、第２主面１ｂとを有している。第２主面１ｂは、第１主面１ａの反対面である。
　第１アルミニウム電極２は、半導体基板１上に配置されている。具体的には、第１アルミニウム電極２は、半導体基板１の第１主面１ａ上に形成されている。第１アルミニウム電極２は、純アルミニウム又はアルミニウム合金により形成されている。第１アルミニウム電極２は、第１面２ａと、第２面２ｂとを有している。第１面２ａは、第１主面１ａに対向している面である。第２面２ｂは、第１面２ａの反対面である。
　パッシベーション膜３は、半導体基板１上に配置されている。具体的には、パッシベーション膜３は、第１アルミニウム電極２の第２面２ｂの周縁を覆っている。パッシベーション膜３は、第１アルミニウム電極２の第２面２ｂの一部を露出させる開口３ａを有している。
　パッシベーション膜３は、例えば、ポリイミドにより形成されている。但し、パッシベーション膜３は、これに限られない。パッシベーション膜３は、ポリイミド以外の絶縁性の樹脂材料により形成されてもよい。パッシベーション膜３は、シリコン酸化物（ＳｉＯ２）、シリコン窒化物（Ｓｉ３Ｎ４）、シリコン酸窒化物（ＳｉＯＮ）等により形成されていてもよい。
　銅膜４は、第１アルミニウム電極２上に形成されている。より具体的には、銅膜４は、開口３ａから露出している第１アルミニウム電極２の第２面２ｂ上に配置されている。銅膜４は、パッシベーション膜３から離間して配置されている。すなわち、パッシベーション膜３と銅膜４の間から、第１アルミニウム電極２の第２面２ｂが露出している。銅膜４は、純銅又は銅合金により形成されている。
　金属膜５は、第１アルミニウム電極２上に配置されている。より具体的には、金属膜５は、パッシベーション膜３と銅膜４との間から露出している第１アルミニウム電極２の第２面２ｂ上に形成されている。金属膜５は、好ましくは、銅膜４及びパッシベーション膜３に接している。
　金属膜５は、ニッケル（Ｎｉ）膜、タンタル（Ｔａ）膜、窒化タンタル（ＴａＮ）膜、タングステン（Ｗ）膜、チタン（Ｔｉ）膜及び窒化チタン（ＴｉＮ）膜からなる群から選択される少なくとも一種により構成されている。金属膜５は、好ましくは、無電解ニッケルめっき膜である。無電解ニッケルめっき膜は、無電解めっき法により形成されたニッケル膜である。
　金属膜５は、上記のものに限られない。金属膜５を構成する材料は、金属膜５中における銅の拡散係数がパッシベーション膜３中における銅の拡散係数よりも小さくなるように適宜選択することができる。金属膜５を構成する材料は、パッシベーション膜３中における当該材料の拡散係数がパッシベーション膜３中における銅の拡散係数よりも小さくなるように適宜選択されてもよい。
　図３は、図１のＩＩＩ－ＩＩＩに沿う断面図である。図３に示されるように、第２アルミニウム電極６は、半導体基板１上に配置されている。具体的には、第２アルミニウム電極６は、半導体基板１の第１主面１ａ上に配置されている。第２アルミニウム電極６は、第３面６ａと、第４面６ｂとを有している。第３面６ａは、第１主面１ａと対向している面である。第４面６ｂは、第３面６ａの反対面である。第２アルミニウム電極６は、純アルミニウム又はアルミニウム合金により形成されている。
　パッシベーション膜３は、さらに、第２アルミニウム電極６の第４面６ｂの周縁を覆っている。パッシベーション膜３は、第２アルミニウム電極６の第４面６ｂの一部を露出させる開口３ｂをさらに有している。なお、開口３ｂから露出する第２アルミニウム電極６の第４面６ｂ上には、銅膜は形成されていない。
　図２及び図３に示されるように、第３アルミニウム電極７は、半導体基板１の第２主面１ｂ上に配置されている。第３アルミニウム電極７は、純アルミニウム又はアルミニウム合金により形成されている。
　＜実施形態に係る半導体装置の詳細構造＞
　図４は、実施形態に係る半導体装置の詳細な内部構造を示す断面図である。図４に示されるように、半導体基板１は、ソース領域１１と、ボディ領域１２と、ドレイン領域１３と、ドリフト領域１４と、ボディコンタクト領域１５とを有している。実施形態に係る半導体装置は、さらに、ゲート絶縁膜１６と、ゲート１７と、層間絶縁膜１８とを有している。
　ソース領域１１は、半導体基板１の第１主面１ａに配置されている。ソース領域１１の導電型は、第１導電型である。第１導電型は、例えばｎ型である。ボディ領域１２は、半導体基板１の第１主面１ａに配置されている。ボディ領域１２は、ソース領域１１を取り囲んでいる。ボディ領域１２の導電型は、第２導電型である。第２導電型は、第１導電型の反対の導電型である。すなわち、第２導電型は、例えばｐ型である。
　ドレイン領域１３の端面は第２主面１ｂになっている。ドレイン領域１３の導電型は、第１導電型である。ドレイン領域１３は、第３アルミニウム電極７に電気的に接続されている。すなわち、第３アルミニウム電極７は、実施形態に係る半導体装置のドレイン電極になっている。
　ドリフト領域１４は、ボディ領域１２を取り囲んでおり、半導体基板１の第１主面１ａに配置されている。このことを別の観点から言えば、ドリフト領域１４はドレイン領域１３上（すなわち、ドレイン領域１３の第１主面１ａ側）に配置されており、ドリフト領域１４及びソース領域１１はボディ領域１２により分離されている。ドリフト領域１４の導電型は、第１導電型である。ドリフト領域１４中における不純物濃度は、ソース領域１１及びドレイン領域１３中における不純物濃度よりも低い。半導体基板１の第１主面１ａに位置するとともに、ソース領域１１とドリフト領域１４とに挟み込まれているボディ領域１２の部分を、以下においては、チャネル領域という。
　ボディコンタクト領域１５は、隣り合う２つのソース領域１１の間において、半導体基板１の第１主面１ａに配置されている。ボディコンタクト領域１５は、ボディ領域１２に達する深さを有している。ボディコンタクト領域１５の導電型は、第２導電型である。ボディコンタクト領域１５中における不純物濃度は、ボディ領域１２中における不純物濃度よりも高い。
　ゲート絶縁膜１６は、半導体基板１の第１主面１ａ上に配置されている。より具体的には、ゲート絶縁膜１６は、チャネル領域上に配置されている。ゲート絶縁膜１６は、例えばシリコン酸化物により形成されている。
　ゲート１７は、ゲート絶縁膜１６上に配置されている。すなわち、ゲート１７は、ゲート絶縁膜１６により絶縁されながら、チャネル領域と対向するように配置されている。ゲート１７は、例えば、不純物がドープされた多結晶のシリコン（Ｓｉ）により形成されている。図示されていないが、ゲート１７は、第２アルミニウム電極６に電気的に接続されている。すなわち、第２アルミニウム電極６は、実施形態に係る半導体装置のゲート電極になっている。
　ソース領域１１、ボディ領域１２、ドレイン領域１３、ドリフト領域１４、ゲート絶縁膜１６及びゲート１７は、トランジスタ１０を構成している。トランジスタ１０は、プレーナゲート型のパワーＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）になっている。
　層間絶縁膜１８は、半導体基板１の第１主面１ａ上に形成されている。層間絶縁膜１８は、ゲート１７を覆っている。層間絶縁膜１８は、例えばシリコン酸化物により形成されている。層間絶縁膜１８には、コンタクトホール１８ａが形成されている。コンタクトホール１８ａは、層間絶縁膜１８を厚さ方向に貫通している。コンタクトホール１８ａからは、ソース領域１１及びボディコンタクト領域１５が露出している。
　第１アルミニウム電極２は、層間絶縁膜１８上に配置されている。また、第１アルミニウム電極２は、コンタクトホール１８ａ中にも配置されている。これにより、第１アルミニウム電極２は、ソース領域１１及びボディコンタクト領域１５と電気的に接続されている。すなわち、第１アルミニウム電極２は、ソース電極になっている。
　上記の例においては、実施形態に係る半導体装置は、プレーナゲート型のパワーＭＯＳＦＥＴを有しているものとして説明を行ったが、実施形態に係る半導体装置は、他の半導体素子を有していてもよい。例えば、実施形態に係る半導体装置は、トレンチゲート型のパワーＭＯＳＦＥＴを有していてもよい。また、実施形態に係る半導体装置は、ショットキーバリアダイオードを有していてもよい。
　＜実施形態に係る半導体装置の外部接続＞
　図５は、実施形態に係る半導体装置の外部接続の状況を示す第１の断面図である。図５に示されるように、第１アルミニウム電極２は、ボンディングワイヤ８ａを銅膜４にワイヤボンディングすることにより、外部接続されている。ボンディングワイヤ８ａは、好ましくは、純銅又は銅合金により形成されている。ボンディングワイヤ８ａの数は、複数であることが好ましい。第３アルミニウム電極７は、例えばハンダ付けによりベース板９に電気的に接続されている。
　図６は、実施形態に係る半導体装置の外部接続の状況を示す第２の断面図である。図６に示されるように、第２アルミニウム電極６は、ボンディングワイヤ８ｂを用いたワイヤボンディングにより、外部接続されている。ボンディングワイヤ８ｂは、例えば純アルミニウム又はアルミニウム合金により形成されている。
　図示されていないが、実施形態に係る半導体装置、ボンディングワイヤ８ａ及びボンディングワイヤ８ｂは、樹脂封止されていてもよい。
　（実施形態に係る半導体装置の製造方法）
　以下に、実施形態に係る半導体装置の製造方法を説明する。
　図７は、実施形態に係る半導体装置の製造方法の工程図である。実施形態に係る半導体装置の製造方法は、図７に示されるように、トランジスタ形成工程Ｓ１と、層間絶縁膜形成工程Ｓ２と、アルミニウム電極形成工程Ｓ３と、パッシベーション膜形成工程Ｓ４と、銅膜形成工程Ｓ５と、金属膜形成工程Ｓ６とを有している。図８は、トランジスタ形成工程Ｓ１における実施形態に係る半導体装置の断面図である。図８に示されるように、トランジスタ形成工程Ｓ１においては、トランジスタ１０の形成が行われる。
　より具体的には、まず、基材が準備される。この基材は、不純物がドープされた単結晶の炭化珪素により形成されている。次に、基材上に、エピタキシャル層が形成される。さらに、エピタキシャル層に対してイオン注入及び活性化アニールが行われることにより、ソース領域１１、ボディ領域１２及びボディコンタクト領域１５が形成される。イオン注入が行われなかったエピタキシャル層の部分がドリフト領域１４になり、基材がドレイン領域１３となる。これにより、半導体基板１が準備される。ゲート絶縁膜１６は、半導体基板１の第１主面１ａを熱酸化することにより形成される。ゲート１７は、ゲート１７を構成する材料をＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）等で成膜するとともに、成膜されたゲート１７を構成する材料をパターンニングすることにより形成される。
　図９は、層間絶縁膜形成工程Ｓ２における実施形態に係る半導体装置の断面図である。図９に示されるように、層間絶縁膜形成工程Ｓ２においては、層間絶縁膜１８が形成される。層間絶縁膜１８の形成は、層間絶縁膜１８を構成する材料をＣＶＤ等で成膜するとともに、成膜された層間絶縁膜１８を構成する材料をＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）等で平坦化することにより行われる。
　図１０は、アルミニウム電極形成工程Ｓ３における実施形態に係る半導体装置の断面図である。アルミニウム電極形成工程Ｓ３においては、図１０に示されるように、第１アルミニウム電極２及び第３アルミニウム電極７が形成される。なお、図示されていないが、アルミニウム電極形成工程Ｓ３においては、第２アルミニウム電極６も形成される。
　第１アルミニウム電極２及び第２アルミニウム電極６の形成においては、第１に、異方性エッチング等により、層間絶縁膜１８中にコンタクトホール１８ａが形成される。第１アルミニウム電極２及び第２アルミニウム電極６の形成においては、第２に、スパッタリング等により、第１アルミニウム電極２及び第２アルミニウム電極６を構成する材料が、層間絶縁膜１８上に成膜されるとともに、コンタクトホール１８ａ中に埋め込まれる。第１アルミニウム電極２及び第２アルミニウム電極６の形成においては、第３に、成膜された第１アルミニウム電極２及び第２アルミニウム電極６を構成する材料がパターンニングされる。第３アルミニウム電極７は、半導体基板１の第２主面１ｂ上に第３アルミニウム電極７を構成する材料をスパッタリング等で成膜することにより形成される。
　図１１は、パッシベーション膜形成工程Ｓ４における実施形態に係る半導体装置の断面図である。図１１に示されるように、パッシベーション膜形成工程Ｓ４においては、パッシベーション膜３が形成される。パッシベーション膜３がポリイミド膜である場合には、パッシベーション膜３は、第１アルミニウム電極２及び第２アルミニウム電極６を覆うようにポリイミド膜を塗布するとともに、塗布されたポリイミド膜を露光・現像することにより形成される。
　パッシベーション膜３がシリコン酸化物、シリコン窒化物、シリコン酸窒化物である場合には、パッシベーション膜３は、パッシベーション膜３を構成する材料をＣＶＤ等で成膜するとともに、成膜されたパッシベーション膜３を構成する材料をエッチングで開口することにより形成される。
　図１２は、銅膜形成工程Ｓ５における実施形態に係る半導体装置の断面図である。図１２に示されるように、銅膜形成工程Ｓ５においては、銅膜４が形成される。銅膜４は、銅膜４を構成する材料をスパッタリング等で成膜するとともに、成膜された銅膜４を構成する材料をパターンニングすることにより形成される。
　金属膜形成工程Ｓ６においては、金属膜５が形成される。金属膜５が無電解ニッケルめっき膜である場合、金属膜５は、パッシベーション膜３と銅膜４との間にある第２面２ｂに対してジンケート処理等の前処理を行うとともに、ニッケルイオンを含むめっき液中に実施形態に係る半導体装置を浸漬することにより形成される。この場合、金属膜５（無電解ニッケルめっき膜）は、パッシベーション膜３と銅膜４との間にある第２面２ｂ上にのみ成長するため、金属膜５をパターンニングする必要がない。
　金属膜５がその他の材料で形成されている場合、金属膜５は、金属膜５を構成する材料をスパッタリング等で成膜するとともに、成膜された金属膜５を構成する材料をパターンニングすることにより形成される。以上により、図１～図４に示される実施形態に係る半導体装置の構造が形成される。
　（実施形態に係る半導体装置の効果）
　以下に、実施形態に係る半導体装置の効果を比較例と対比しながら説明する。
　図１３は、比較例に係る半導体装置の断面図である。比較例に係る半導体装置は、図１３に示されるように、金属膜５に代えて、封止材５ａを有している。封止材５ａは、絶縁性の樹脂材料により形成されている。比較例に係る半導体装置のその余の構成は、実施形態に係る半導体装置と同様である。
　比較例に係る半導体装置においては、パッシベーション膜３と銅膜４との間から露出している第２面２ｂ上に封止材５ａが配置されているため、銅膜４とパッシベーション膜３とが接触しておらず、銅膜４からパッシベーション膜３中への銅の拡散は抑制される。しかしながら、比較例に係る半導体装置においては、パッシベーション膜３と銅膜４との間から露出している第２面２ｂが樹脂材料で形成された封止材５ａで覆われているため、第１アルミニウム電極２からの放熱性が低下する。
　実施形態に係る半導体装置においては、パッシベーション膜３と銅膜４との間にある第２面２ｂ上に金属膜５が配置されているため、銅膜４とパッシベーション膜３とが接触しておらず、銅膜４からパッシベーション膜３中への銅の拡散は抑制される。加えて、パッシベーション膜３と銅膜４との間にある第２面２ｂ上に形成されているのは金属膜５であるため、第１アルミニウム電極２からの放熱が阻害されにくい。そのため、実施形態に係る半導体装置によると、銅膜４からパッシベーション膜３中への銅の拡散を抑制しつつ、第１アルミニウム電極２からの放熱性を改善することができる。
　なお、実施形態に係る半導体装置においては、パッシベーション膜３と銅膜４との間にある第２面２ｂ上に金属膜５が配置されているため、電流が流れる面積を拡大することができるため、比較例に係る半導体装置に比べ、第１アルミニウム電極２周りの電気抵抗値の増加を抑制することができる。
　実施形態に係る半導体装置において金属膜５が無電解ニッケルめっき膜である場合、金属膜５のパターンニングが不要となるため、製造工程を簡略化することが可能になる。
　今回開示された実施形態は全ての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態ではなく請求の範囲によって示され、請求の範囲と均等の意味及び範囲内での全ての変更が含まれることが意図される。
１　半導体基板、１ａ　第１主面、１ｂ　第２主面、２　第１アルミニウム電極、２ａ　第１面、２ｂ　第２面、３　パッシベーション膜、３ａ，３ｂ　開口、４　銅膜、５　金属膜、５ａ　封止材、６　第２アルミニウム電極、６ａ　第３面、６ｂ　第４面、７　第３アルミニウム電極、８ａ，８ｂ　ボンディングワイヤ、９　ベース板、１１　ソース領域、１２　ボディ領域、１３　ドレイン領域、１４　ドリフト領域、１５　ボディコンタクト領域、１６　ゲート絶縁膜、１７　ゲート、１８　層間絶縁膜、１８ａ　コンタクトホール、Ｓ１　トランジスタ形成工程、Ｓ２　層間絶縁膜形成工程、Ｓ３　アルミニウム電極形成工程、Ｓ４　パッシベーション膜形成工程、Ｓ５　銅膜形成工程、Ｓ６　金属膜形成工程、１０　トランジスタ。

Claims (7)

  1. 　第１主面を有する半導体基板と、
    　前記第１主面に対向している第１面と、前記第１面の反対面である第２面とを有し、前記半導体基板上に配置されたアルミニウム電極と、
    　前記第２面の周縁を覆い、前記第２面の一部を露出させる開口を有するパッシベーション膜と、
    　前記開口から露出している前記第２面上に前記パッシベーション膜から離間して配置された銅膜と、
    　前記パッシベーション膜と前記銅膜との間から露出している前記第２面上に配置された金属膜とを備え、
    　前記金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されている、半導体装置。
  2. 　前記パッシベーション膜は、ポリイミド膜である、請求項１に記載の半導体装置。
  3. 　前記金属膜は、無電解ニッケルめっき膜である、請求項１又は請求項２に記載の半導体装置。
  4. 　前記半導体基板は、炭化珪素半導体基板である、請求項１から請求項３のいずれか１項に記載の半導体装置。
  5. 　ゲートと、
    　ゲート絶縁膜とをさらに備え、
    　前記半導体基板は、前記第１主面の反対面である第２主面と、前記第１主面に配置されたソース領域と、前記第２主面を構成しているドレイン領域と、前記ドレイン領域の前記第１主面側に配置されたドリフト領域と、前記ドリフト領域と前記ソース領域とを分離するボディ領域とを有し、
    　前記ゲートは、前記ドリフト領域と前記ソース領域との間にある前記ボディ領域の部分と前記ゲート絶縁膜を介して対向しており、
    　前記アルミニウム電極は、前記ソース領域に電気的に接続されている、請求項１から請求項４のいずれか１項に記載の半導体装置。
  6. 　第１主面を有する半導体基板と、
    　前記第１主面に対向している第１面と、前記第１面の反対面である第２面とを有し、前記半導体基板上に配置されたアルミニウム電極と、
    　前記第２面の周縁を覆い、前記第２面の一部を露出させる開口を有するパッシベーション膜と、
    　前記開口から露出している前記第２面上に前記パッシベーション膜から離間して配置された銅膜と、
    　前記パッシベーション膜と前記銅膜との間から露出している前記第２面上に配置された金属膜と、
    　ゲートと、
    　ゲート絶縁膜とを備え、
    　前記金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されており、
    　前記パッシベーション膜は、ポリイミド膜であり、
    　前記半導体基板は、前記第１主面の反対面である第２主面と、前記第１主面に配置されたソース領域と、前記第２主面を構成しているドレイン領域と、前記ドレイン領域の前記第１主面側に配置されたドリフト領域と、前記ドリフト領域と前記ソース領域とを分離するボディ領域とを有し、
    　前記ゲートは、前記ドリフト領域と前記ソース領域との間にある前記ボディ領域の部分と前記ゲート絶縁膜を介して対向しており、
    　前記アルミニウム電極は、前記ソース領域に電気的に接続されている、半導体装置。
  7. 　第１主面を有する半導体基板と、
    　前記第１主面に対向している第１面と、前記第１面の反対面である第２面とを有し、前記半導体基板上に配置されたアルミニウム電極と、
    　前記第２面の周縁を覆い、前記第２面の一部を露出させる開口を有するパッシベーション膜と、
    　前記開口から露出している前記第２面上に前記パッシベーション膜から離間して配置された銅膜と、
    　前記パッシベーション膜と前記銅膜との間から露出している前記第２面上に配置された金属膜と、
    　ゲートと、
    　ゲート絶縁膜とを備え、
    　前記金属膜は、ニッケル膜、タンタル膜、窒化タンタル膜、タングステン膜、チタン膜及び窒化チタン膜からなる群から選択される少なくとも一種により構成されており、
    　前記パッシベーション膜は、ポリイミド膜であり、
    　前記金属膜は、無電解ニッケルめっき膜であり、
    　前記半導体基板は、炭化珪素半導体基板であり、
    　前記半導体基板は、前記第１主面の反対面である第２主面と、前記第１主面に配置されたソース領域と、前記第２主面を構成しているドレイン領域と、前記ドレイン領域の前記第１主面側に配置されたドリフト領域と、前記ドリフト領域と前記ソース領域とを分離するボディ領域とを有し、
    　前記ゲートは、前記ドリフト領域と前記ソース領域との間にある前記ボディ領域の部分と前記ゲート絶縁膜を介して対向しており、
    　前記アルミニウム電極は、前記ソース領域に電気的に接続されている、半導体装置。
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JP2009177104A (ja) * 2007-02-20 2009-08-06 Nec Electronics Corp 半導体装置
JP2014187073A (ja) * 2013-03-21 2014-10-02 Renesas Electronics Corp 半導体装置およびその製造方法
WO2017199706A1 (ja) * 2016-05-18 2017-11-23 三菱電機株式会社 電力用半導体装置およびその製造方法

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