CN102412273A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102412273A
CN102412273A CN2011100668673A CN201110066867A CN102412273A CN 102412273 A CN102412273 A CN 102412273A CN 2011100668673 A CN2011100668673 A CN 2011100668673A CN 201110066867 A CN201110066867 A CN 201110066867A CN 102412273 A CN102412273 A CN 102412273A
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electrode
semiconductor device
semiconductor
electrically connected
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小野升太郎
斋藤涉
谷内俊治
渡边美穗
山下浩明
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Toshiba Corp
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Abstract

本发明提供半导体装置，具有：第一主电极，与第一导电型的第一半导体区域及在上述第一半导体区域的表面选择性地设置的第二导电型的第二半导体区域电连接；控制电极，与上述第一半导体区域之间隔着第一绝缘膜地设置；以及引出电极，与上述控制电极电连接。还具有：第二绝缘膜，设在上述第一主电极及上述引出电极的上方；以及多个接触电极，设置在形成于上述第二绝缘膜的多个第一接触孔的内部，与上述引出电极电连接。通过上述第二绝缘膜与上述第一主电极电绝缘的控制端子，覆盖上述引出电极、以及上述第一主电极中的设置在上述第一半导体区域上方、上述第二半导体区域上方、上述控制电极上方的部分，与上述多个接触电极电连接。

Description

半导体装置及其制造方法
相关申请的交叉引用
本申请基于2010年9月17日提交的在先日本专利申请2010-210134号并享受其优先权，并通过援引包括其全部内容。
技术领域
本发明的实施方式涉及半导体装置及其装置方法。
背景技术
MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)及IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)等功率半导体装置具有高速开关特性、几十～几百V的反向阻止电压(耐压)，被广泛应用于家用电器、通信设备、车载马达等的电力转换、控制等。在这些领域中，也强烈追求半导体装置的小型化、高效率化及低功耗化。
例如，作为半导体装置的不依赖于芯片面积的性能指标而能够考虑到导通电阻Ron与芯片面积S的积Ron×S。即使单纯地缩小芯片面积S而使半导体装置小型化，由于与芯片面积S成反比的Ron会增大，所以Ron×S的值不会减小。因此，为了鉴于高效率化及低功耗化而实现半导体装置的小型化，缩小Ron×S是很重要的。
为了缩小Ron×S，可以举出如下方式：通过优化或改良元件结构而减小每单位面积的Ron的方式、以及增大导通电流流过的有效区域占芯片面的比例的方式。例如，通过在栅电极焊盘下方形成流动导通电流的沟道，能够不改变芯片面积S地扩大相对有效区域而降低Ron，从而缩小Ron×S。
但是，在形成于栅电极焊盘下方的沟道中，不直接接触源电极，会产生由雪崩击穿引起的元件破坏的问题。因此，很少有在栅电极焊盘下方形成作为导通电流的流路的沟道的做法。所以，追求一种半导体装置，其能够抑制栅电极焊盘下方的雪崩击穿、将栅电极焊盘下方有效地利用为电流沟道。
发明内容
本发明的实施方式提供一种低导通电阻的半导体装置及其制造方法，抑制栅电极焊盘下部的雪崩击穿，能够将栅电极焊盘下方有效地利用为电流沟道。
本发明的实施方式的半导体装置具备：第一主电极，与第一导电型的第一半导体区域及在上述第一半导体区域的表面选择性地设置的第二导电型的第二半导体区域电连接；控制电极，与上述第一半导体区域之间隔着第一绝缘膜地设置；引出电极，与上述控制电极电连接。还具备：第二绝缘膜，设置在上述第一主电极及上述引出电极的上方；多个接触电极，设置在形成于上述第二绝缘膜的多个第一接触孔的内部，与上述引出电极电连接；通过上述第二绝缘膜与上述第一主电极电绝缘的控制端子，覆盖上述引出电极、以及上述第一主电极中的设置在上述第一半导体区域的上方、上述第二半导体区域的上方和上述控制电极的上方的部分，与上述多个接触电极电连接。
根据本发明的实施方式，能够提供低导通电阻的半导体装置及其制造方法，能够抑制栅电极焊盘下部的雪崩击穿，能够将栅电极焊盘的下方有效地利用为电流沟道。
附图说明
图1是表示一实施方式的半导体装置的截面的示意图。
图2是示意性地表示一实施方式的半导体装置的俯视图。
图3～图9是示意性地表示一实施方式的半导体装置的制造过程的剖视图。
图10是表示一实施方式的变形例的半导体装置的截面的示意图。
具体实施方式
以下，参照附图说明本发明的实施方式。另外，在下面的实施方式中，对附图中的同一部分附加同一附图标记并适当省略其详细说明，适当说明不同部分。将第一导电型设为p型、第二导电型设为n型来进行说明，但也可以将第一导电型设为n型、第二导电型设为p型。
图1是表示本实施方式的半导体装置100的截面的示意图。
半导体装置100例如为纵型的平面MOSFET。如图1所示，在第一主电极即源电极12与漏电极17(第二主电极)之间流通导通电流的元件部10中，具有：设在n+漏层16(第二半导体层)上的n型漂移层2(第一半导体层)；设于n型漂移层2表面的p型基底区域3；以及设于p型基底区域3表面的n型源区域4。在p型基底区域3之上，隔着作为第一绝缘膜的栅绝缘膜6而设有作为控制电极的栅电极7。
作为第一半导体区域的p型基底区域3和作为第二半导体区域的n型源区域4电连接于源电极12。即，源电极12被设置为，与露出在经由层间绝缘膜33而被绝缘的栅电极7之间的n型源区域4接触。在栅电极7之间，源电极12既与p+接触区域5接触，又经由p+接触区域5而与p型基底区域3电连接。
并且，与源电极12隔开间隔的栅引出电极13设置在栅电极7及n型源区域4、p+接触区域5的上方。栅引出电极13经由设于层间绝缘膜33的开口而与栅电极7电连接。另一方面，栅引出电极13与n型源区域4、p+接触区域5之间通过层间绝缘膜33而被绝缘。
并且，还设有作为第二绝缘膜的绝缘性保护膜15，该绝缘性保护膜15覆盖源电极12与栅引出电极13。
并且，在绝缘性保护膜15设有与栅引出电极13连通的多个接触孔15a(第一接触孔)。在接触孔15a的内部，设有与栅引出电极13连接的接触电极21。并且，在接触电极21的上方，设有由含有金属的粘接材料构成的导电性的粘接层23，将栅端子25的连接部25a与接触电极21之间连接。
栅端子25的连接部25a覆盖源电极12中的、设置在p型基底区域3上方、n型源区域4上方、栅电极7上方的部分、及栅引出电极13，并与设置在多个接触孔15a内部的接触电极21电连接。另一方面，栅端子25与源电极12之间通过绝缘性保护膜15而电绝缘。
在设于元件部10周围的末端部20，在n型漂移层2的表面设有场氧化膜24，并且，还设有从元件部10与末端部20的边界延伸到场氧化膜24的表面上的场板12a。
场板12a与在元件部10与末端部20的边界设置的保护环18组合而发挥作用，用于提高末端部的耐压。
图2是示意性地表示半导体装置100的俯视图。
如图2(a)所示，半导体装置100具有如下结构：在与漏端子26结合(ボンデイング)的半导体芯片90表面，结合有栅端子25和源端子27(第一端子)。栅端子25的连接部25a与源端子27的连接部27a分别具有平板状的形状，设置所谓的直接导联(ダイレクトリ一ド接続)。漏端子26(第二端子)与半导体芯片90的背面经由漏电极17而电连接。
图2(a)所示的I-I截面具有图1所示的截面结构，栅端子25的连接部25a与半导体芯片90之间通过粘接层23而连接。粘接层23例如能够采用焊料。
另一方面，源端子27的连接部27a也能够同样地经由粘接层23与半导体芯片90的表面连接。并且，源端子27与源电极12之间电连接。
图2(b)是示意性地表示与栅端子25的连接部25a接触的半导体芯片90的一部分的俯视图。该图所示的虚线所包围的区域25b是与连接部25a接触的部分。
本实施方式的半导体装置100，不在与栅端子25接触的部分设有一体的栅电极焊盘，而是如图1及图2(b)所示地，相互隔开间隔地设置多个栅引出电极13。并且构成为，经由在栅引出电极13上方设置的接触电极21及粘接层23，栅端子25的连接部25a与栅引出电极13电连接。
在图2(b)所示的例子中，区域25b的内部设有8个栅引出电极13，但栅引出电极13例如至少为2个及2个以上即可，能够对应栅电流来选择个数及尺寸。并且，在图2(b)中，示出了正方形的粘接层23及栅引出电极13，但它们不限于正方形，能够做成长方形、圆形等各种形状。
并且，例如，图2(b)所示的8个粘接层23不必都与栅引出电极13电连接，为了确保栅端子25的粘接强度，其一部分可以设在绝缘性保护膜15的表面。
栅引出电极13的尺寸及个数可以考虑到栅电流的最大值而决定为必要最小限度。栅电流是对半导体装置100进行开关控制情况下的瞬态电流，其值较小。因此，例如能够使多个栅引出电极13的总面积比包含在区域25b中的源电极12的面积小。
本实施方式的半导体装置100中，如图1所示，在栅端子25的连接部25a所结合的区域25b(参照图2(b))，也设有p型基底区域3及n型源区域4、栅电极7并形成沟道。并且，源电极12也设置成与p型基底区域3及n型源区域4连接，所以能够与区域25b以外的元件部10同样地流通导通电流。
因此，能够扩大半导体装置100中的流通导通电流的有效区域的面积，所以能够降低导通电阻Ron，从而能够减小Ron与芯片面积S的积Ron×S。
并且，栅引出电极13能够形成多个，因此能够将各个栅引出电极13的面积相比于栅端子25的连接部25a的面积而大幅度地缩小。由此，例如，能够对在位于栅引出电极13下方的n型漂移层2中产生的空穴，降低经由不与源电极12直接接触的p型基底区域3以及p+接触区域5的排出电阻。并且，能够抑制栅端子25的连接部25a的雪崩击穿而提高雪崩耐量，或者能够防止电流集中引起的破坏。
另外，如上所述，在缩小了栅引出电极13的大小的情况下，还能够构成为在栅引出电极13的下方不含有n型源区域4的结构，即栅电极7下方没有沟道的结构。
下面，参照图3～图9说明半导体装置100的制造过程。
图3(a)是示意性地表示在n型漂移层2的表面形成了作为栅绝缘膜6的绝缘膜6a、并形成了作为栅电极的导电层7a的状态的剖视图。
n型漂移层2例如能够形成在高浓度掺杂有n型杂质的硅基板上。绝缘膜6a能够采用热氧化膜(SiO2膜)，导电层7a能够采用多晶硅。
下面，图3(b)表示对导电层7a进行图案形成而形成了栅电极7的状态。
接着，如图3(c)所示，在栅电极7的表面形成绝缘膜31。例如，能够对多晶硅的表面进行热氧化而形成SiO2膜。
图4(a)是示意性地表示在n型漂移层2的表面形成了p型基底区域3的状态的剖视图。
例如，能够以栅电极7作为掩模，向n型漂移层2的表面离子注入p型杂质，之后，实施热处理而使p型杂质扩散。作为p型杂质，能够采用硼(B)。
接着，如图4(b)所示，在P型基底区域3的表面形成n型源区域4和p+e接触区域5。
例如，通过分别选择性地离子注入作为n型杂质的砷(As)及作为p型杂质的B，能够形成n型源区域4及p+接触区域5。
如5表示图4之后的制造过程，是示意性地表示在层间绝缘膜33形成用于与n型源区域4及p+接触区域5、栅电极7接触的开口的工序的剖视图。
如图5(a)所示，在层间绝缘膜33上方，形成具有开口41a的抗蚀剂掩模41。接着，例如采用干式刻蚀法来对层间绝缘膜33进行蚀刻。
图5(b)表示在层间绝缘膜33形成开口33a及开口33b、并去除了抗蚀剂掩模41的状态。形成开口33a以用于使源电极12与n型源区域4及p+接触区域5接触。另一方面，在形成有栅引出电极13的区域(参照图6(b))，仅形成用于与栅电极7接触的开口33b，而不形成与n型源区域4及p+接触区域5连通的开口。
图6表示图5之后的制造过程，是示意性地表示形成源电极12与栅引出电极13的工序的剖视图。
如图6(a)所示，在形成有开口33a及33b的层间绝缘膜33上方形成电极金属36。例如能够采用溅射法来形成铝(Al)膜。
接着，如图6(b)所示，对电极金属36进行图案形成，使其分离为源电极12与栅引出电极13。源电极12经由开口33a与n型源区域4和p+接触区域5接触。另一方面，栅引出电极13经由开口33b与栅电极7接触。
这样，本实施方式的半导体装置100的制造方法中，能够将源电极12与栅引出电极13同时形成在p型基底区域3、n型源区域4及栅电极7上。
图7是表示图6所示的制造过程之后的、在源电极12及栅引出电极13上方形成了绝缘性保护膜15的状态。
绝缘性保护膜15保护半导体芯片90的表面，并且存在于栅端子25与源电极12之间而使两者绝缘。作为绝缘性保护膜15，例如能够采用聚酰亚胺。
在绝缘性保护膜15形成多个接触孔15a(参照图2(b))。并且，也可以形成用于对源端子27与源电极12之间进行电连接的接触孔15b(第二接触孔)(参照图9)。
接着，如图8所示，在接触孔15a及15b的内部，形成接触电极21与粘接层23。
接触电极21例如是镍(Ni)电极，能够通过电镀法形成。
粘接层23能够采用例如用于将栅端子25及源端子27粘接的焊料。
接触孔15a能够形成尺寸比栅引出电极13小的开口，以使得接触电极21与栅引出电极13的内侧接触。
例如，粘接层23为焊料的情况下，使用了Ni的接触电极21发挥防止焊料迁移(マイグレ一シヨン)的阻挡层的功能。并且，如图8所示，通过将接触电极21形成得与栅引出电极13的内侧接触，能够将沿接触电极21与绝缘性保护膜15的界面进入的焊料阻止在栅引出电极13的表面。
接着，如图2所示，将半导体芯片90从基板切出并结合在漏端子26上。并且，栅端子25及源端子27分别结合于半导体芯片90的表面。
然后，如图9所示，栅端子25的连接部25a及源端子27的连接部27a经由粘接层23及接触电极21分别与栅引出电极13及源电极12连接。
本实施方式的半导体装置100中，连接部25a的下方也设置与n型源区域4及p+接触区域5连接的源电极12，并通过绝缘性保护膜15与连接部25a绝缘。
图10是表示本实施方式的变形例的半导体装置200的截面的示意图。
半导体装置200与半导体装置100的区别在于，栅端子25的连接部25a及源端子27的连接部27a利用金属凸点42与接触电极21连接。金属凸点42例如能够采用焊球。
在绝缘性保护膜15的接触孔15a及15b的内部所设置的接触电极21之上，设有凸点电极43。凸点电极43例如能够采用Ni膜而形成。
在凸点电极43的中央，存在与接触孔15a及15b的开口对应的凹陷，能够将例如球状的金属凸点42引导到接触孔15a及15b的开口上面。
并且，从位于接触孔15a及15b的开口上面的金属凸点42上方，对栅端子25的连接部25a与源端子27的连接部27a进行热压接，从而能够与半导体芯片90的表面连接。
以上参照本发明的一实施方式说明了本发明，但本发明不限于这些实施方式。例如，本领域技术人员根据申请时的技术水平能够做出的设计变更、材料变更等与本发明技术思想一致的实施方式也包含在本发明的技术范围内。
例如，本实施方式的半导体装置100及200中，例示了所谓的纵型平面栅型功率MOSFET，但也可以是具有沟槽栅结构的MOSFET，也可以是IGBT等其他开关器件。并且，也能够适用于横型的器件结构。此外，也能够适用于采用GaN或SiC等硅以外的材料的器件。
本实施方式以将栅端子25电连接于栅电极7的结构为例进行了说明，但不限于与栅电极7连接，即使与其他部分连接，也能够适用于将不流通导通电流的区域有效地利用为有效区域。
以上对本发明的几个实施方式进行了说明，但这些实施方式只是例示，并不意欲限定发明范围。这些新的实施方式能够通过其他各种方式来实施，在不脱离发明主旨的范围内，能够进行各种省略、替换及变更。这些实施方式及其变形包含在发明范围及主旨中，并且包含在权利要求书所记载的发明及其等同的范围内。

Claims (20)

1.一种半导体装置，其特征在于，
该半导体装置具备：
第一主电极，与第一导电型的第一半导体区域及在上述第一半导体区域的表面选择性地设置的第二导电型的第二半导体区域电连接；
控制电极，与上述第一半导体区域之间隔着第一绝缘膜地设置；
引出电极，与上述控制电极电连接；
第二绝缘膜，设置在上述第一主电极及上述引出电极的上方；
多个接触电极，设置在形成于上述第二绝缘膜的多个第一接触孔的内部，与上述引出电极电连接；以及
控制端子，覆盖上述引出电极、以及上述第一主电极中的设置在上述第一半导体区域的上方、上述第二半导体区域的上方和上述控制电极的上方的部分，与上述多个接触电极电连接，通过上述第二绝缘膜与上述第一主电极电绝缘。
2.如权利要求1所述的半导体装置，其特征在于，
该半导体装置还具备第三绝缘膜，该第三绝缘膜覆盖上述第一半导体区域和上述第二半导体区域，
上述引出电极通过上述第三绝缘膜与上述第一半导体区域及上述第二半导体区域绝缘。
3.如权利要求1所述的半导体装置，其特征在于，
该半导体装置还具备粘接部件，该粘接部件设置在上述接触电极与上述控制端子之间，含有金属。
4.如权利要求3所述的半导体装置，其特征在于，
在上述第二绝缘膜与上述控制端子之间具备上述粘接部件。
5.如权利要求3所述的半导体装置，其特征在于，
上述粘接部件为焊料或金属凸点。
6.如权利要求5所述的半导体装置，其特征在于，
在上述接触电极的上部设有用于引导上述金属凸点的凹陷。
7.如权利要求1所述的半导体装置，其特征在于，
多个上述引出电极隔开间隔地设置，在与该多个上述引出电极分别对应的多个上述第一接触孔的内部设有多个上述接触电极。
8.如权利要求1所述的半导体装置，其特征在于，
上述引出电极的总面积小于上述主电极的被上述控制端子覆盖的一部分的面积。
9.如权利要求1所述的半导体装置，其特征在于，
在上述引出电极的正下方设置的上述第一半导体区域不含有上述第二半导体区域。
10.如权利要求1所述的半导体装置，其特征在于，
上述第一主电极及上述引出电极含有铝。
11.如权利要求1所述的半导体装置，其特征在于，
上述第二绝缘膜是聚酰亚胺膜。
12.如权利要求1所述的半导体装置，其特征在于，
上述接触电极含有镍。
13.如权利要求1所述的半导体装置，其特征在于，
上述第一接触孔的开口设置成比上述引出电极的外边缘靠近内侧。
14.如权利要求1所述的半导体装置，其特征在于，还具备：
第二主电极，经由第二导电型的第二半导体层，与设有上述第一半导体区域的第二导电型的第一半导体层的背面电连接；
第一端子，与上述第一主电极电连接；以及
第二端子，与上述第二主电极电连接。
15.如权利要求14所述的半导体装置，其特征在于，
上述控制端子及第一端子的连接部被设置为平板状。
16.如权利要求14所述的半导体装置，其特征在于，
上述第一端子经由设置在形成于上述第二绝缘膜的第二接触孔的内部的上述接触电极，与上述第一主电极电连接。
17.如权利要求14所述的半导体装置，其特征在于，
该半导体装置还具备粘接部件，该粘接部件设置在上述接触电极与上述第一端子之间，含有金属。
18.如权利要求14所述的半导体装置，其特征在于，
含有上述第一半导体层及上述第二半导体层的半导体芯片的背面，经由上述第二主电极与上述第二端子结合。
19.一种半导体装置的制造方法，
该半导体装置具备：
主电极，与第一导电型的第一半导体区域及在上述第一半导体区域的表面选择性地设置的第二导电型的第二半导体区域电连接；
控制电极，与上述第一半导体区域之间隔着第一绝缘膜地设置；
引出电极，与上述控制电极电连接；
第二绝缘膜，设置在上述主电极及上述引出电极的上方；以及
多个接触电极，在覆盖上述主电极的一部分及上述引出电极且结合有控制端子的区域内，设置在形成于上述第二绝缘膜的多个接触孔的内部，与上述控制端子和上述引出电极电连接，
该半导体装置的制造方法的特征在于，
在上述第一半导体区域、上述第二半导体区域及上述控制电极的上方，同时形成作为上述主电极及上述引出电极的金属膜。
20.如权利要求19所述的半导体装置的制造方法，其特征在于，
上述金属膜含有铝。
CN2011100668673A 2010-09-17 2011-03-18 半导体装置及其制造方法 Pending CN102412273A (zh)

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