CN110419111A - 自对准且稳健的绝缘栅双极晶体管器件 - Google Patents

自对准且稳健的绝缘栅双极晶体管器件 Download PDF

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CN110419111A
CN110419111A CN201980001643.9A CN201980001643A CN110419111A CN 110419111 A CN110419111 A CN 110419111A CN 201980001643 A CN201980001643 A CN 201980001643A CN 110419111 A CN110419111 A CN 110419111A
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bipolar transistor
rod structure
type
region
back side
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CN110419111B (zh
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H.耶尔马兹
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Ai Bao Erbandaoti
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Ai Bao Erbandaoti
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Abstract

公开了一种垂直IGBT器件。垂直IGBT结构包含形成在第一导电性类型的半导体衬底的正侧的有源区域中的有源MOSFET单元阵列。一个或多个第二导电性类型的柱结构同心地围绕有源MOSFET单元阵列。每个柱结构包含柱沟槽和深柱区域。通过将第二导电性类型的注入物通过柱沟槽的底面注入到半导体衬底中来形成深柱区域。在除了沟槽的底壁之外的沟槽侧壁上形成电介质侧壁间隔体，并且使用第二导电性类型的多晶硅填充柱沟槽。一个或多个柱结构比有源MOSFET单元阵列实质上更深。

Description

自对准且稳健的绝缘栅双极晶体管器件
相关申请的交叉引用
本申请涉及并要求2018年1月16日提交的题为“Self-Aligned and Robust IGBT”的美国临时专利申请No.62/617,994的优先权，该美国临时专利申请的全部内容通过引用明确并入本文。
技术领域
本发明涉及绝缘栅半导体器件，更具体地，涉及形成绝缘栅双极晶体管(IGBT)半导体器件的器件结构和方法。
背景技术
IGBT(绝缘栅双极晶体管)是由MOSFET驱动的宽基极PNP双极结晶体管(BJT)器件，其成为处理高电流和高压电机控制和感应加热型应用的关键电源器件。为了改善IGBT效率和稳健性，存在持续的研究和开发以降低正向电压降——Vce-Sat(集电极-发射极饱和电压)，最小化开关损耗以及改善IGBT的安全操作区(SOA)。
可以通过低MOSFET电阻，通过在位于IGBT上部的MOSFET单元之间扩展电阻，以及通过PNP BJT的宽n基区域的高水平载流子调制来降低来降低正向电压降Vce-Sat，低MOSFET电阻为垂直PNP BJT提供基电流，PNP BJT的宽n基极区域受到少数载流子寿命和注入效率载流子调制的影响。
遗憾的是，高水平载流子调制或存储还通过减慢关断速度和降低IGBT的SOA而增加了开关损耗。在漏极和源极端子(Rd)上每单位面积的低MOSFET导通电阻之间的另一个折衷是通常在电机驱动应用的负载短路模式期间产生更高的饱和度和更短的耐受时间。作为MOSFET的一部分的寄生NPN BJT的基极到源极短路，对于防止闩锁和增强IGBT稳健性非常关键。
本发明通过扩展电阻减小、控制载流子注入和由多晶硅沟槽形成更深的结来优化Vce-Sat、关断速度和安全操作区(SOA)，从而实现稳健且有效的IGBT器件制造。
发明内容
本发明的一个方面包含一种垂直绝缘栅双极晶体管(IGBT)器件，包括有源金属氧化物半导体场效应晶体管(MOSFET)单元阵列，其形成在第一导电性类型的半导体衬底的正侧；以及至少一个第二导电性类型的柱结构，其形成在半导体衬底中，至少一个柱结构同心地围绕有源MOSFET单元阵列，至少一个柱结构包含填充有第二导电性类型的多晶硅的沟槽，在除了沟槽的底壁之外的沟槽侧壁上形成的电介质侧壁间隔体，以及从沟槽的底壁延伸的第二导电性的深区域，其中至少一个柱结构比有源MOSFET单元阵列实质上更深，并且第一导电性类型是n型和第二导电性类型是p型。
本发明的另一方面提供了一种垂直绝缘栅双极晶体管(IGBT)器件，包括有源金属氧化物半导体场效应晶体管(MOSFET)单元阵列，其形成在n型导电性的半导体衬底的正侧；以及至少一个p型导电性的柱结构，其形成在半导体衬底中，至少一个柱结构同心地围绕有源MOSFET单元阵列，至少一个柱结构包含填充有p多晶硅的沟槽，在除了沟槽的底壁之外的沟槽侧壁上形成的p掺杂侧壁区域，以及从沟槽的底壁延伸的p型深区域，其中至少一个柱结构比有源MOSFET单元阵列实质上更深，并且其中p掺杂侧壁区域防止p掺杂多晶硅中的p掺杂剂耗尽。
本发明的另一方面提供了一种形成垂直绝缘栅双极晶体管(IGBT)器件的方法，包括提供具有正侧和背侧的第一导电性类型的半导体衬底；形成第二导电性类型的柱结构，其同心地围绕半导体衬底的正侧的区域，形成柱结构包含在半导体衬底的正侧形成柱沟槽，沟槽包含沟槽侧壁和沟槽底面，在沟槽侧壁上形成电介质间隔体，通过将第二导电性类型的掺杂剂通过沟槽底面施加到半导体衬底中，形成从沟槽底面向下延伸的柱深区域，使用第二导电性的多晶硅填充沟槽，第二导电性的多晶硅与柱深区域接触；和在包含填充有多晶硅的柱沟槽的半导体衬底的正侧上沉积包含氧化硅的氧化物层；平坦化氧化物层；在氧化物层上沉积包含硅氮化物的蚀刻停止层；在蚀刻停止层上施加光掩模；以及在由柱结构同心地围绕的区域中形成至少一个金属氧化物半导体场效应晶体管(MOSFET)单元，其中第一导电性类型是n型和第二导电性类型是p型。
附图说明
图1A图示了根据实施例的示出了具有p柱的沟槽MOSFET单元的IGBT结构；
图1B图示了具有栅极金属和n+多晶硅接触区域的IGBT结构；
图1C图示了具有高压(HV)终止区域的IGBT结构；
图1D图示了在HV终止区域的最后一个p柱环之后具有沟道区域的IGBT结构；
图2A图示了具有n缓冲层和p/p+层的IGBT结构；
图2B图示了具有p+和n+区域的背侧以控制注入的IGBT结构；
图2C图示了具有背侧p+多晶硅以控制注入的IGBT结构；
图3A图示了替代的IGBT结构，其包含在没有氧化物间隔体的情况下由p柱保护的沟槽MOSFET单元；
图3B图示了具有p柱的p隔离沟槽MOS结构的替代IGBT结构；
图3C以俯视图图示了使用阶梯和弧形结构的在IGBT器件角部处的HV终止；
图4A以俯视图图示了环绕IGBT有源器件单元的p柱；
图4B以俯视图图示了多个IGBT有源器件单元；
图4C以俯视图图示了IGBT器件，p柱隐藏在发射极金属下方；
图5A图示了形成用于IGBT的包含沟槽和p区域的p柱的工艺；
图5B图示了形成包含具有氧化物间隔体的沟槽和p区域的p柱的工艺；
图5C图示了形成p柱的工艺，该p柱包含沟槽、形成p区域的高能B注入物，以及用于在没有氧化物间隔体的情况下进行处理的侧壁角注入物；
图5D图示了形成p柱的工艺，该p柱包含具有p+多晶硅的沟槽；
图5E图示了在截面中形成IGBT的多个有源MOSFET沟槽栅极和自对准基极接触沟槽的工艺；
图5F图示了在截面中形成IGBT的有源MOSFET沟槽栅极中的n+多晶硅和多晶硅的CMP的工艺；
图5G图示了在截面中形成IGBT的p体和n+发射极的工艺；
图5H图示了形成接触沟槽的工艺；
图5I图示了填充接触沟槽以及金属和钝化层的施加的工艺；
图5J图示了背侧处理的工艺；
图6A图示了在图5H中所示的步骤之后的替代工艺；
图6B图示了在图6A中所示的步骤之后的替代工艺，包含在背侧处理期间保护接触；
图6C图示了在图6B中所示的步骤之后的替代工艺，包含晶圆背侧减薄以形成厚外围环(Taiko环)；
图6D图示了在图6C中所示的步骤之后的替代工艺，包含背侧金属化；和
图6E图示了在图6D中所示的步骤之后的替代工艺，包含正侧金属化。
具体实施方式
在下面描述的示例性实施例中，本发明提供了IGTB器件，其具有完全围绕有源MOSFET单元阵列的壁状深阻挡结构，该壁状深阻挡结构可以形成在相反导电性类型的半导体层中并且成形为柱或柱结构，在截面中具有沟槽部分和从沟槽底面延伸深入到半导体层中的注入区域。围绕有源MOSFET单元的这种连续阻挡结构在下文中将称为柱或柱环。
当柱的沟槽部分和注入部分具有p型导电性时，柱是p柱或深p柱，即柱具有p型导电性。在这方面，p柱的沟槽部分可以包含p+多晶硅(p+多晶Si)填充物材料，并且注入区域包含p型注入物或掺杂剂注入区域。这种深p柱可以在IGTB器件的接通状态期间(即，当IGBT器件导通时)电浮置，并且可以减小IGBT器件的发射极和集电极端子两端的电压降。此外，与没有深p柱的现有技术沟槽IGBT器件相比，这种深p柱可以改善击穿电压。
如下面将更全面地描述的，可以使用几种方法形成本发明的柱。在一个实施例中，IGBT器件的p柱可以在沟槽侧壁上具有氧化物间隔体或电介质间隔体，以将p+多晶硅限制在沟槽内，从而防止任何侧向p型注入物(硼离子)扩散到邻近器件区域中。在另一个实施例中，可以将p型注入物注入p柱沟槽侧壁，以在沟槽侧壁上形成注入区域或屏蔽，而不在沟槽的侧壁上采用氧化物间隔体。
在IGBT器件形成工艺的实施例中，可以同时形成MOSFET p体和有源MOSFET沟槽栅极的接触窗口，因此栅极沟槽和p体接触沟槽是自对准的。因此，由于消除了掩模未对准，p体的p+接触注入物可以均匀地影响MOSFET阈值电压，这增强了IGBT器件的闩锁能力。在非自对准沟槽和p体型结构中，未对准的p+注入可以提高IGBT有源单元一侧的阈值电压，而IGBT单元的另一侧可以具有较少的p体电荷，因此寄生NPN双极结晶体管(BJT)的高基极到发射极短路电阻可能是高的。如果NPN BJT的基极到发射极的短路电阻是高的，则NPN BJT可以在较低的电流水平下导通，这可能会降低IGBT的闩锁电流能力。这是因为当NPN BJT和宽基极PNP BJT总电流增益达到1时，IGBT可能会闩锁。
在IGBT器件制造工艺期间，传统上，可以初始完成包含正侧金属化的正侧晶圆工艺，然后进行背侧工艺。对于背侧，前缘IGBT器件可能需要激光背侧退火工具，这是一种高成本工具。背侧退火工具可能不适用于许多晶圆代工厂(foundry)。在本发明的一个实施例中，可以在正侧金属化工艺步骤之前有利地完成晶圆背侧工艺，以例如使用快速热退火(RTA)工具来激活背侧注入物。在正侧金属化之前进行背侧工艺步骤可以具有其优点，因为首先沉积正侧金属可以将晶圆在背侧工艺期间可能暴露的最高温度限制到通常低于450℃。在450℃或更低的温度下，在背侧工艺期间发生的注入物激活速率可能非常低，例如，约1％。传统上，高压(HV)终止结构可能在IGBT器件的外周中需要n+区域，以防止耗尽区域(称为“沟道停止”)延伸到器件的锯切边缘，并防止在电压阻断模式(IGBT的断开状态)期间的泄露电流。包含沟槽MOS沟道停止和浮置深p柱的新型HV终止结构可以实现稳健且可靠的边缘终止，这是本发明的另一个优点。
现在转向附图，图1A和1B可以分别示出沿图4A中的线A1-A1和B1-B1截取的示例性截面(具有减少数目的示例性MOSFET单元)。图4A以俯视图示出了示例性IGBT单位单元100或IGBT单元100。
图1A图示了在n型半导体衬底101或基极区域101中以及在半导体衬底的正侧101A处形成的垂直IGBT单元100的实施例。基极区域101可以是n型导电性(第一类型导电性)的单晶半导体，例如n型硅半导体。IGBT单元100的中心部分可以包含并联连接的MOSFET单元102的阵列。出于清楚的目的，在图1A-1B的截面中使用减少数目的MOSFET单元102。
IGBT单元100的边缘区域可以包含完全围绕MOSFET单元102的柱104或柱结构104。柱104可以具有p型导电性或第二类型导电性。可以存在多于一个柱104，其同心地围绕MOSFET单元102的阵列，用于MOSFET单元的高压保护。在图1A和1B中，柱104用于MOSFET单元102的高压(HV)保护。在该实施例中，MOSFET单元102可以是沟槽MOSFET单元。柱104可以包含经由沟槽界面110连接到掩埋区域108(注入区域)或深区域108的柱基极106。柱基极106可以包含柱沟槽112，沟槽112具有限定该柱沟槽112的沟槽侧壁114和沟槽底面115。柱沟槽112可以包含形成在沟槽侧壁114上的沟槽间隔体116或间隔体116，以及填充柱沟槽112的沟槽填充物118，该沟槽填充物118经由柱界面122与电介质层120(诸如BPSG层)接触。基极区域101内的漂移区域124可以从沟槽MOSFET单元102并沿着基极区域101延伸。
沟槽MOSFET单元102可以包含p体接触区域128，p体接触区域128包含p体接触127。p体接触区域128可以由用于栅极接触131的栅极接触沟槽130或栅极沟槽130彼此分开(如图1B所示)。栅极沟槽130可以填充有n+多晶硅(n+多晶硅接触区域)。p体接触区域128可以具有内部p体接触区域128A和外部p体接触区域128B，两者都是重度p掺杂的。内部p体接触区域128A可以包含n+发射极接触区域132。发射极金属134可以通过延伸穿过电介质层120的Ti/TiN/W缓冲金属136连接到n+发射极接触区域132和p体接触区域128，从而形成延伸到p体接触区域128中的p体接触127。钝化层135可以涂覆正侧101A。
在一个实施例中，柱104的沟槽填充物118可以是p+多晶硅材料，并且深区域108可以是p区域，被注入p型注入物的深区域或深p区域。IGBT结构的深区域108可以是电浮置的，即它们与任何电极没有直接的欧姆接触。在本文中，p+表示高p型掺杂剂材料(诸如硼(B))浓度，并且p表示较低的p型掺杂剂材料浓度。因为柱基极106和深区域108都包含p型掺杂剂，因此柱104可以称为p柱。在一个实施例中，可以通过将高能硼注入物通过柱沟槽112的底面115注入来形成深区域108，柱沟槽112的底面115可以形成在n型硅的基极材料101中。间隔体116可以是通过氧化沟槽侧壁114而形成在沟槽侧壁114上的氧化物间隔体，并且柱沟槽112填充有沟槽填充物118，即p+多晶硅(p+多晶Si)。柱104的高能量p离子注入的深区域108d可以与p+多晶硅沟槽填充物118直接接触。
间隔体116可以限制硼在柱沟槽112中的横向扩散，并且可以将与沟槽界面110相邻的柱的深区域108保持在其灯泡形状中，灯泡形状可以是顶部窄并且底面宽。取决于基极区域101的n掺杂浓度，柱104可以彼此分开5至20微米(μm)形成，因此柱104的间隔可以取决于IGBT器件的额定电压。
柱104形成在IGBT单位单元100的有源区域中，该有源区域是HV边缘终止区域的器件内部区域，环绕MOSFET单元102(平面MOSFET或沟槽MOSFET)。当IGBT单元100处于截止状态(电压阻断模式)时，柱104在MOSFET单元102的击穿以下夹断(pinch)，MOSFET单元102被例如图4A中所示的柱104环绕。因此，这可以证明具有浅p体扩散和浅沟槽的IGBT器件如何可以支持非常高的电压阻断(等于或大于1000V)。
柱104可以电浮置以改善恰在有源IGBT单元下方的载流子调制，以减小集电极-发射极上的导通状态电压(Vce-Sat)，从而降低IGBT器件的功率耗散。P+多晶硅沟槽填充物118与深P区域108直接接触，并与IGBT单元100的漂移区域124间接接触，并且因此沟槽填充物118可以表现得像缺陷聚集中心，其可以改善载流子寿命并减少IGBT器件泄漏。可以通过沟槽底面115建立深p区域108与沟槽填充物118之间的直接接触以及漂移区域124与沟槽填充物118之间的间接接触。
在一个实施例中，p体区域128和n+发射极区域132中的接触可以与栅极沟槽130自对准，并在形成接触开口之后填充缓冲金属Ti/TiN/W。P+注入物不会影响IGBT器件的阈值电压(VT)。
本发明的IGTB结构可以提供以下益处。例如，一个益处可以是，本发明的IGBT结构可以防止IGBT闩锁，并因此使得器件更加稳健。另一个益处可以是，IGBT结构可以仅在沟槽内部而不在表面上具有多晶硅，因此可以容易使用CMP(化学机械抛光)来平坦化沟槽。还可以增加有源器件单元密度，以驱动用于较快的IGBT器件的较低增益的PNP BJT。此外，较高密度的沟槽MOS可以降低顶表面区域或正侧101A处的有源器件区域中的扩展电阻。较高的沟槽MOS密度，即使n+源(或IGBT的n+发射极)外围电压降低以对于电机控制应用限制IGBT饱和电流，从而在“短路负载测试”或“短路测试”期间增加器件的稳健性，也可以减小沟槽侧壁和底部区域的附近的扩展电阻。
图1B图示了IGBT单位单元100的示例性栅极金属部分。栅极金属138经由延伸通过电介质层120的Ti/TiN/W缓冲金属140连接到栅极沟槽130。栅极沟槽130包含n+多晶硅。栅极接触131至n+多晶硅可以是平面型，而不是沟槽型，因为栅极接触形成步骤可以仅包含BPSG电介质层120的蚀刻。栅极接触形成步骤可以不包含硅蚀刻工艺。
图1C-1D图示了用于环绕有源MOSFET单元阵列的示例性高压(HV)终止区域200的实施例。可以使用在其之间具有变化的分开距离的p柱204(用于n型半导体衬底)来形成HV终止区域200。
如图1C所示，在一个实施例中，HV终止区域200中的p柱204可以通过形成同心p柱环(图4C)而完全环绕有源器件区域。第一p柱环204A可以短接到发射极金属234，以漏出HV终止区域200中存储的电荷。在形成第一p柱环204A之后，可以形成其它p柱环204，同时增大它们之间的空间，以使表面电场最小化，从而实现用于高压终止的最小面积。此外，柱沟槽212内的p+多晶硅填充物218被氧化物间隔体216限制，以防止p+掺杂剂侧向扩散以节省面积并由深p区域208建立分压。深p区域208连接到填充柱沟槽212的p+多晶硅，以最小化由于来自封装和组装环境的外部电荷引起的表面电场敏感性。
如图1D所示，在邻近锯切道244的HV终止区域200的远侧边缘处，放置与场板236接触的MOS单元230，以阻止HV耗尽到达裸芯边缘或衬底边缘，(锯切区域)，从而防止和泄漏电流。场板236是在电介质上使用的导体，以帮助减小表面电场。
图2A-2C图示了用于图1A-1D中所示的IGBT单元的半导体衬底101的背侧101B处的各种背侧结构150。图2A图示了IGBT单元100的背侧结构150A，其包含n缓冲层或场停止层103和集电极金属154以及p和p+空穴注入区域152A，以控制IGBT单元100中的空穴注入。尽管图2A示出了图1A中所示的正侧结构，但是图1A-1D中所示的所有正侧结构可以具有图2A中所示的背侧结构150A。
图2B图示了背侧结构150B的实施例，其包含n缓冲层或场停止层103和集电极金属154以及p和p+/n+空穴注入区域152B，以控制IGBT单元100中的空穴注入。尽管图2B示出了图1A中所示的正侧结构，但是图1A-1D中所示的所有正侧结构可以具有图2B中所示的背侧结构150B。
图2C图示了背侧结构150C，其包含n缓冲层或场停止层103和集电极金属154以及p和p+掺杂多晶硅空穴注入区域152C，以控制IGBT单元100中的空穴注入。尽管图2C示出了图1A中所示的正侧结构，但是图1A-1D中所示的所有正侧结构可以具有图2C中所示的背侧结构150C。
图3A图示了根据本发明的替代IGBT单元300，其包含在沟槽侧壁处没有氧化物间隔体的情况下由柱结构304或柱304或pp柱304完全围绕和保护的沟槽MOSFET单元302。在IGBT单元300的该实施例中，沟槽侧壁314可以不包含氧化物间隔体，并且先前实施例(图1A)的重度掺杂p+多晶硅(p+多晶Si)填充物可以用轻度p掺杂多晶硅(p多晶Si)填充物318替换。p+多晶硅具有比p多晶硅更高的掺杂剂比率。具有电浮置p多晶硅填充物318的柱304和深p区域308可以在“导通状态”期间改善靠近MOSFET单元302的区域中的载流子调制，以降低Vce(集电极到发射极电压)并在IGBT单元300的“断开状态”期间保护MOSFET单元。
与先前实施例(图1A)的p+多晶硅相反，柱304的沟槽填充材料p多晶硅318可以具有p型掺杂剂的最小横向扩散。此外，通过向柱沟槽312的侧壁注入p型掺杂剂，在沟槽侧壁314上形成屏蔽316，可以在柱沟槽312内屏蔽p型多晶硅。屏蔽316可以防止在IGBT器件的HV阻断状态期间的耗尽，以避免由于在多晶硅边界处产生多晶硅的大EHP(电子-空穴对)而导致的高泄漏。
图3B图示了根据本发明的替代IGBT单元结构，其可以包含隔离结构。隔离结构(例如，p隔离沟槽MOS结构305)可以放置在柱304和MOSFET单元302的外部p体接触区域之间。
隔离结构可以减小所需的反向偏压以停止柱304的电浮置。在较低的反向偏压下，柱304之间的区域的耗尽使得能够实现较薄且浅的p体型IGBT器件制造。
在大多数应用中，施加负栅极-发射极电压(Vge)以关断IGBT器件。返回参考图2B，负Vge可以经由p隔离沟槽MOS 305的p体区域307创建p沟道，并且有源沟槽MOSFET单元302可以导通，这可以在浮置柱304和沟槽MOSFET单元302的p体之间建立电连接。p沟道可以是p隔离沟槽MOS 305下方的反n区域部分。因为沟槽MOSFET单元302的p体连接到发射极电极334，所以柱304可以间接连接到发射极电极334，这可以进而在IGBT单元的关断阶段期间更快地漏出存储的空穴。
当IGBT单元300关断(断开状态)时，浮置柱304附近存储的空穴可以更快地楼出，因此IGBT单元300可以具有更短的关断时间。利用在IGBT单元300的导通状态期间施加的正Vge，p柱和IGBT单元300的p体之间的n区域的一部分可以是电子累积的，其可以使柱304浮置以用于低Vce。
图3C示出了在使用弧形和阶梯状结构的IGBT器件角部处的高压(HV)终止区域的俯视图。对于图3A-3B中所示和所述的实施例，可以使用阶梯状而不是弧形角部来适应p侧壁注入以形成屏蔽316。为了避免侧壁不连续，HV终止区域的角部区域中的沟槽可以设计成具有阶梯状沟槽结构350A而不是传统设计的弧形沟槽结构350B。阶梯状沟槽结构350A可以避免在深沟槽中形成氧化物间隔体。
图4A图示了根据本发明的由p柱404环绕的有源MOSFET单元阵列402的俯视图。
图4B图示了根据本发明形成的一组IGBT有源器件单元400A-400H的俯视图。
图4C以俯视图图示了根据本发明形成在衬底上的IGBT器件90，包含金属化和焊盘。HV终止区域包含围绕有源IGBT单元的第一柱环。第一柱环位于金属和钝化区域下方。HV终止区域沿着与锯切道相邻的衬底/晶圆的边缘延伸。
图5A-5J图示了根据本发明的IGBT单元的实施例的制造方法。因此，图5A图示了使用掩模-1在半导体衬底500中形成p柱的工艺。可以通过沟槽蚀刻在衬底500中形成柱沟槽512。在随后的步骤中，可以将高能p型注入物(硼)通过柱沟槽512注入，以在衬底中形成注入区域IR。柱沟槽512可以包含沟槽侧壁514和沟槽底面515。注入区域IR在柱沟槽512下方用圆圈描绘。在该实施例中，可以在形成氧化物侧壁间隔体516A(图5B)之前进行高能掺杂剂注入。
图5B可以是通过采用掩模-1形成p柱的替代工艺。工艺可以包含在形成氧化物侧壁间隔体516A之后，将高能p掺杂剂通过沟槽底面515注入，以形成注入物区域IR。
图5C图示了通过采用掩模-1形成具有柱沟槽和高能注入的p柱的另一替代工艺。工艺可以包含将高能硼通过沟槽底面515注入，以形成注入区域IR，然后注入侧壁角p型注入，以形成侧壁屏蔽516B。
图5D图示了通过采用掩模-1形成p柱504的工艺的实施例。工艺可以包含以下步骤：沟槽蚀刻，以及高能p型掺杂剂注入；然后是以下步骤：在驱动在先前工艺步骤期间注入的p型掺杂剂(硼)以形成深p区508时在柱沟槽512中进行氧化物(SiO2)沉积或氧化物生长，氧化物的RIE蚀刻以限定柱沟槽512内的侧壁间隔体516A，将多晶硅沉积到柱沟槽512中，然后进行硼注入以在柱沟槽512中形成p+多晶硅，以及回蚀刻p+多晶硅以形成p+多晶硅沟槽填充物518。
图5E图示了通过在衬底500上采用掩模-2(未示出)来形成有源MOSFET单元和自对准p体接触的工艺的实施例。工艺可以包含以下步骤：在p+多晶硅填充物518之上沉积氧化物(SiO2)层550并平坦化氧化物层550；在平坦化的氧化物层上沉积氮化物(Si3N4)层552作为蚀刻停止层；以及，应用光掩模(掩模-2)以形成有源栅极沟槽530和自对准p体接触沟槽531。图5E示出了在移除掩模-2之后具有有源MOSFET栅极沟槽和自对准接触的IGBT单元的截面。移除掩模-2之后的工艺步骤可以包含：在硅衬底中初始蚀刻例如约0.5μm的深沟槽，以用于有源栅极沟槽530，并且蚀刻p体接触沟槽531；沉积氧化物以填充窄的p体接触沟槽531；各项同性地回蚀刻氧化物以移除未完全填充的有源栅极沟槽530内的氧化物，然而，p体接触沟槽531可以保持完全填充氧化物。在完成氧化物蚀刻步骤之后，可以将硅蚀刻例如另外约2.5μm，以实现例如MOSFET单元的约3μm有源栅极沟槽深度。
图5F示出了IGBT结构在完成栅极氧化以氧化栅极沟槽530的壁从而形成电介质层551，n+多晶硅沉积以填充氧化物衬垫栅极沟槽和CMP工艺步骤以在衬底500上平坦化n+多晶硅之后的截面。
图5G图示了用于形成p体528的掩模-3和用于形成n+发射极532的掩模-4之后的IGBT结构的截面。工艺步骤可以包含在p体光掩模(掩模-3)之后回蚀刻填充p体接触沟槽531的氧化物；离子注入p体528；以及，应用掩模-4以用于注入磷和砷，从而形成n+发射极532。
图5H图示了作为接触掩模的掩模-5之后的IGBT结构的截面。工艺步骤可以包含：沉积BPSG电介质层520；应用接触掩模(掩模-5)；蚀刻BPSG层520；p+低能硼注入(1-5E15原子cm-2或(1-5E15 cm-2))。
图5I图示了掩模-6(金属掩模)和掩模-7(钝化掩模)之后的IGBT结构的截面。工艺步骤可以包含：沉积Ti/TiN/W缓冲金属536，并沉积约4μm的Al：Si：Cu发射极金属534；施加金属掩模；使用湿/干/湿金属蚀刻进行蚀刻；沉积包含SiO2/Si3N4和聚酰胺的钝化层535。
图5J图示了背侧工艺之后的IGTB的截面。工艺步骤可以包含通过Taiko研磨方法减薄晶圆背侧501B或通过蚀刻以使晶圆变薄；通过蚀刻移除研磨损伤；在完成晶圆减薄工艺之后，使用注入工艺形成n缓冲场停止层503和p/p+空穴注入层562；通过低温RTA或管或激光退火来将注入退火；沉积背侧金属564，包含Al：Ti：Ni：Ag或Ti：Ni：Ag；金属烧结，温度范围为250℃至450℃。
图6A图示了通过接触蚀刻的IGBT工艺的实施例。在BPSG 520的接触蚀刻和注入低能p+注入物(1-5E15 cm-2)之后，在开始背侧减薄(图6B)和注入工艺之前，可以沉积SiO2/Si3N4的薄层552A(200A SiO2和1000A Si3N4)，以在背侧处理期间保护衬底表面和正侧501A处的接触。
图6B-6D图示了示例性背侧注入物激活和金属化工艺。可以首先通过Taiko或掩模湿法蚀刻来研磨晶圆背侧501B，以在衬底或晶圆的外周留下厚的硅环566，以最小化翘曲(图6B)。接下来，n缓冲层503或场停止层503和p/p+空穴注入层562可以被形成，并且然后通过常规RTA被激活，因为没有正侧金属化。可以通过沉积包含Al：Ti：Ni：Ag或Ti：Ni：Ag的背侧金属564来完成背侧工艺。
在完成背侧注入物激活和金属化之后，如图6E所示，晶圆正侧工艺继续进行以下：通过沉积包含Ti/TiN/W/Al：Cu：Al的正金属层的正侧金属化工艺；使用金属掩模蚀刻前金属层；沉积包含SiO2/Si3N4和聚酰亚胺的钝化层；并且，可以通过焊盘打开和退火的步骤完成该工艺。
通过混合正侧处理和背侧处理在半导体衬底上形成垂直IGBT结构的示例性方法可以包含：(a)已经处理至正侧金属沉积步骤的IGBT；(b)在接触蚀刻工艺步骤之后，沉积厚度范围约为100-300埃的薄氧化物，然后沉积厚度范围为500-2000埃的氮化物(Si3N4)层以接触保护，如图6A所示；(c)继续进行晶圆研磨和背侧损伤移除蚀刻，如图6B所示；(d)施加用于n缓冲和p+注入物的背侧注入物，如图6C所示；(e)激活掺杂和在适当的薄晶圆处理的情况下使用RTA退火注入物损伤；(f)沉积背侧金属Al/Ti/Ni/Ag或Ti/Ni/Ag，如图6D所示；(g)通过选择性地移除氮化物接触保护层，以及接下来在不蚀刻BPSG电介质层的情况下蚀刻约100-300埃的SiO2层以从接触区域移除氧化物，返回到正侧工艺；(h)沉积正金属，Ti/TiN/W缓冲层和Al：Si：Cu或Al；Cu，厚度范围为1-8μm；(i)施加金属掩模并蚀刻金属；(j)沉积等离子体增强PSG(磷掺杂硅氧化物)的钝化层和氮化物层，并且还沉积范围为5-20μm的聚酰亚胺层；(k)施加钝化掩模并蚀刻钝化层，如图6E所示；以及(1)退火晶圆以恢复MOSFET/IGBT的阈值电压。
尽管本文关于某些实施例描述了本发明的方面和优点，但实施例的修改对于本领域技术人员而言是显而易见的。尽管本发明使用N沟道型IGBT作为示例，但是本发明也适用于通过使用p区域替换所有n区域和使用n区域替换所有p区域来构造P沟道型IGBT。因此，本发明的范围不应限于前述讨论，而应由所附权利要求限定。

Claims (30)

1.一种垂直绝缘栅双极晶体管(IGBT)器件，包括：
有源金属氧化物半导体场效应晶体管单元(MOSFE)阵列，形成在第一导电性类型的半导体衬底的正侧；以及
第二导电性类型的至少一个柱结构，形成在所述半导体衬底中，所述至少一个柱结构同心地围绕所述有源金属氧化物半导体场效应晶体管单元阵列，至少一个柱结构包含填充有所述第二导电性类型的多晶硅的沟槽、在除了所述沟槽的底壁之外的沟槽侧壁上形成的电介质侧壁间隔体，以及从所述沟槽的底壁延伸的所述第二导电性的深区域，
其中，所述至少一个柱结构比所述有源金属氧化物半导体场效应晶体管单元阵列实质上更深。
2.根据权利要求1所述的垂直绝缘栅双极晶体管器件，其中所述第一导电性类型是n型，并且所述第二导电性类型是p型。
3.根据权利要求2所述的垂直绝缘栅双极晶体管器件，其中填充所述沟槽的多晶硅是p掺杂的。
4.根据权利要求2所述的垂直绝缘栅双极晶体管器件，其中所述有源金属氧化物半导体场效应晶体管单元阵列包含沟槽金属氧化物半导体场效应晶体管器件。
5.根据权利要求2所述的垂直绝缘栅双极晶体管器件，其中所述有源金属氧化物半导体场效应晶体管单元阵列包含平面金属氧化物半导体场效应晶体管器件。
6.根据权利要求3所述的垂直绝缘栅双极晶体管器件，其中所述至少一个柱结构与所述有源金属氧化物半导体场效应晶体管单元阵列分开定位，以在所述垂直绝缘栅双极晶体管器件的导通状态期间电浮置。
7.根据权利要求3所述的垂直绝缘栅双极晶体管器件，其中所述至少一个柱结构包含多个柱结构，所述多个柱结构同心地围绕所述有源金属氧化物场效应晶体管单元阵列。
8.根据权利要求7所述的垂直绝缘栅双极晶体管器件，其中所述柱结构中的一些是浮置的，并且所述柱结构中的另一些电连接到所述垂直绝缘栅双极晶体管器件的发射电极，其中在浮置的所述柱结构和连接到所述发射电极的所述柱结构之间存在间隙。
9.根据权利要求7所述的垂直绝缘栅双极晶体管器件，其中所述多个柱结构电连接到除了高压终止区域中的发射电极之外的发射电极。
10.根据权利要求3所述的垂直绝缘栅双极晶体管器件，其中所述沟槽金属氧化物半导体场效应晶体管器件的p体接触体是沟槽类型并且与栅极沟槽自对准。
11.根据权利要求2所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以从所述背侧移除硅损伤，并且被注入以形成n缓冲区域、与形成在所述背侧处的集电极电极接触的p和p+空穴注入区域。
12.根据权利要求2所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以从所述背侧移除硅损伤，并且被注入以形成n缓冲区域、与形成在所述背侧处的集电极电极接触的p和交替p+空穴注入区域和n+区域。
13.根据权利要求2所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以从所述背侧移除硅损伤，并且被注入以形成n缓冲区域和p区域，p+多晶硅注入区域在所述p区域上与形成在所述背侧处的集电极电极接触。
14.根据权利要求2所述的垂直绝缘栅双极晶体管器件，还包含高压终止区域，所述高压终止区域包含：
多个p型柱结构，每个柱结构包含沟槽，所述沟槽填充有p型多晶硅，在所述沟槽侧壁上具有或不具有电介质侧壁间隔体，以及从所述沟槽的底壁延伸的p型深区域，其中所述p型深区域用作浮置场环；
场板和金属氧化物半导体沟道停止。
15.一种垂直绝缘栅双极晶体管器件，包括：
有源金属氧化物半导体场效应晶体管单元阵列，形成在n型导电性的半导体衬底的正侧；以及
至少一个p型导电性的柱结构，形成在所述半导体衬底中，所述至少一个柱结构同心地围绕所述有源金属氧化物半导体场效应晶体管单元阵列，至少一个柱结构包含填充有p多晶硅的沟槽、在除了所述沟槽的底壁之外的沟槽侧壁上形成的p掺杂侧壁区域，以及从所述沟槽的底壁延伸的p型深区域，
其中，所述至少一个柱结构比所述有源金属氧化物半导体场效应晶体管单元阵列实质上更深。
16.根据权利要求15所述的垂直绝缘栅双极晶体管器件，其中所述p掺杂侧壁区域防止p掺杂多晶硅中的p掺杂剂耗尽。
17.根据权利要求15所述的垂直绝缘栅双极晶体管器件，其中所述至少一个柱结构包含多个柱结构，所述多个柱结构同心地围绕所述有源金属氧化物半导体场效应晶体管单元阵列。
18.根据权利要求17所述的垂直绝缘栅双极晶体管器件，其中所述柱结构中的一些是浮置的，并且所述柱结构中的另一些电连接到所述垂直绝缘栅双极晶体管器件的发射电极，其中在浮置的所述柱结构和连接到所述发射电极的所述柱结构之间存在间隙。
19.根据权利要求15所述的垂直绝缘栅双极晶体管器件，还包括在所述至少一个柱结构和所述有源金属氧化物半导体场效应晶体管单元阵列之间的隔离结构、平面金属氧化物半导体或沟槽金属氧化物半导体之一。
20.根据权利要求15所述的垂直绝缘栅双极晶体管器件，还包括在所述垂直绝缘栅双极晶体管器件的高压终止区域处的阶梯状角部结构。
21.根据权利要求15所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以移除硅损伤，并且被注入以形成n缓冲区域、与形成在所述背侧处的集电极电极接触的p和p+空穴注入区域。
22.根据权利要求15所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以移除硅损伤，并且被注入以形成n缓冲区域、与形成在所述背侧处的集电极电极接触的p和交替p+空穴注入区域和n+区域。
23.根据权利要求15所述的垂直绝缘栅双极晶体管器件，所述半导体衬底的背侧被进行机械和化学处理以移除硅损伤，并且被注入以形成n缓冲区域和p区域，p+多晶硅注入区域在所述p区域上与形成在所述背侧处的集电极电极接触。
24.一种形成垂直绝缘栅双极晶体管器件的方法，包括：
提供具有正侧和背侧的第一导电性类型的半导体衬底；
形成第二导电性类型的柱结构，其同心地围绕所述半导体衬底的正侧的区域，形成所述柱结构包含：
在所述半导体衬底的正侧中形成柱沟槽，所述沟槽包含沟槽侧壁和沟槽底面，
在所述沟槽侧壁上形成电介质间隔体，
通过将所述第二导电性类型的掺杂剂通过所述沟槽底面施加到所述半导体衬底中，形成从所述沟槽底面向下延伸的柱深区域，
使用第二导电性的多晶硅填充所述沟槽，所述第二导电性的多晶硅与所述柱深区域接触；和
将包含硅氧化硅的氧化物层沉积到包含填充有所述多晶硅的柱沟槽的所述半导体衬底的正侧上；
平坦化所述氧化物层；
在所述氧化物层上沉积包含硅氮化物的蚀刻停止层；
在所述蚀刻停止层上施加光掩模；以及
在由所述柱结构同心地围绕的区域中形成至少一个金属氧化物半导体场效应晶体管单元。
25.根据权利要求24所述的方法，其中所述第一导电性类型是n型，并且所述第二导电性类型是p型。
26.根据权利要求25所述的方法，其中形成所述至少一个金属氧化物半导体场效应晶体管单元包含经由所述光掩模形成p体接触沟槽和金属氧化物半导体场效应晶体管栅极沟槽，其中使用所述光掩模形成所述接触沟槽和所述栅极沟槽两者以使所述接触沟槽与所述栅极沟槽自对准。
27.根据权利要求26所述的方法，其中形成所述p体接触沟槽和所述金属氧化物场效应晶体管栅极沟槽包含使用相同掩模同时蚀刻所述p体接触沟槽和所述金属氧化物半导体场效应晶体管栅极沟槽约0.5μm深度，并且在所述金属氧化物半导体场效应晶体管栅极沟槽正被向下蚀刻到3-6μm深度时使用氧化物填充所述p体接触沟槽以停止进一步蚀刻。
28.根据权利要求27所述的方法，还包含：
施加包含接触掩模的光致抗蚀剂掩模，所述接触掩模使得能够从所述p体接触沟槽移除氧化物，以及
注入p+掺杂剂，所述p+掺杂剂在每个p体的中心处对准，所述每个p体被形成为使得所述至少一个金属氧化物半导体场效应晶体管单元的阈值不受影响。
29.根据权利要求28所述的方法，还包含在将焊盘掩模施加到所述半导体衬底的正侧之后处理所述半导体衬底的背侧，所述处理背侧包含：
在2至5密耳厚度范围内研磨所述背侧，以用于600伏特和1200伏特绝缘栅双极晶体管器件制造，
在所述研磨后湿法蚀刻以移除硅损伤，和
通过将n型和p型注入物注入所述背侧中，在所述背侧上形成n缓冲区域和p/p+空穴注入区域，
激活背侧注入物，以及
施加背侧金属。
30.根据权利要求29所述的方法，其中所述背侧注入物激活由低温管、快速热退火(RTA)和激光退火之一来进行。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116110961A (zh) * 2023-02-22 2023-05-12 强华时代(成都)科技有限公司 一种沟槽栅双极型晶体管及其制作工艺

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110419111B (zh) 2018-01-16 2023-08-15 艾鲍尔半导体 自对准且稳健的绝缘栅双极晶体管器件
US11069770B2 (en) * 2018-10-01 2021-07-20 Ipower Semiconductor Carrier injection control fast recovery diode structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789396A (zh) * 2008-12-20 2010-07-28 电力集成公司 制造深沟槽绝缘栅极双极晶体管的方法
CN102136490A (zh) * 2009-12-03 2011-07-27 株式会社日立制作所 半导体装置以及使用它的电力变换装置
US20120056201A1 (en) * 2009-05-11 2012-03-08 Sumitomo Electric Industries, Ltd. Insulated gate bipolar transistor
CN104347689A (zh) * 2013-07-31 2015-02-11 万国半导体股份有限公司 双沟槽-栅极绝缘栅双极晶体管结构
US20170243745A1 (en) * 2015-10-20 2017-08-24 Maxpower Semiconductor, Inc. Vertical power transistor with deep floating termination regions

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2689047B2 (ja) 1991-07-24 1997-12-10 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタとその製造方法
JPH0897375A (ja) 1994-07-26 1996-04-12 Toshiba Corp マイクロ波集積回路装置及びその製造方法
US6124179A (en) 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
JP4198251B2 (ja) 1999-01-07 2008-12-17 三菱電機株式会社 電力用半導体装置およびその製造方法
DE10127950B4 (de) 2001-06-08 2007-04-12 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement
JP4566470B2 (ja) 2001-07-17 2010-10-20 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタ
US7132321B2 (en) 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch
WO2004066391A1 (ja) 2003-01-20 2004-08-05 Mitsubishi Denki Kabushiki Kaisha 半導体装置
US6861317B1 (en) * 2003-09-17 2005-03-01 Chartered Semiconductor Manufacturing Ltd. Method of making direct contact on gate by using dielectric stop layer
US7112499B2 (en) * 2004-01-16 2006-09-26 Chartered Semiconductor Manufacturing Ltd. Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal
JP4930894B2 (ja) 2005-05-13 2012-05-16 サンケン電気株式会社 半導体装置
US8110868B2 (en) 2005-07-27 2012-02-07 Infineon Technologies Austria Ag Power semiconductor component with a low on-state resistance
US8461648B2 (en) 2005-07-27 2013-06-11 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
US7442584B2 (en) 2005-11-21 2008-10-28 Stmicroelectronics, Inc. Isolated vertical power device structure with both N-doped and P-doped trenches
JP2008117881A (ja) 2006-11-02 2008-05-22 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
US7541247B2 (en) * 2007-07-16 2009-06-02 International Business Machines Corporation Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication
JP2009064825A (ja) 2007-09-04 2009-03-26 Toyota Motor Corp 半導体装置とその製造方法
US7713794B2 (en) 2007-11-01 2010-05-11 Fuji Electric Device Technology Co., Ltd. Manufacturing method of a semiconductor device
US7666711B2 (en) 2008-05-27 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming double-sided through vias in saw streets
JP2010098189A (ja) 2008-10-17 2010-04-30 Toshiba Corp 半導体装置
JP5333342B2 (ja) 2009-06-29 2013-11-06 株式会社デンソー 半導体装置
US10566462B2 (en) 2009-07-30 2020-02-18 Infineon Technologies Austria Ag Bipolar semiconductor device and manufacturing method
JP5526811B2 (ja) 2010-01-29 2014-06-18 富士電機株式会社 逆導通形絶縁ゲート型バイポーラトランジスタ
JP5757103B2 (ja) 2011-02-21 2015-07-29 富士電機株式会社 ワイドバンドギャップ逆阻止ｍｏｓ型半導体装置
US9478646B2 (en) 2011-07-27 2016-10-25 Alpha And Omega Semiconductor Incorporated Methods for fabricating anode shorted field stop insulated gate bipolar transistor
JP5995435B2 (ja) 2011-08-02 2016-09-21 ローム株式会社 半導体装置およびその製造方法
US8785279B2 (en) * 2012-07-30 2014-07-22 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (FBM)
JP5817686B2 (ja) 2011-11-30 2015-11-18 株式会社デンソー 半導体装置
US20130181253A1 (en) * 2012-01-18 2013-07-18 Richtek Technology Corporation, R.O.C. Semiconductor structure and manufacturing method thereof
JP2015046502A (ja) * 2013-08-28 2015-03-12 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
US9337262B2 (en) 2014-01-16 2016-05-10 Ideal Power Inc. Structures and methods with reduced sensitivity to surface charge
JP2016058428A (ja) 2014-09-05 2016-04-21 株式会社東芝 半導体装置
DE102014113557B4 (de) 2014-09-19 2020-06-10 Infineon Technologies Ag Halbleitervorrichtung mit variablem resistivem element
EP3155664B1 (en) 2014-10-13 2019-04-03 Ideal Power Inc. Field plates on two opposed surfaces of a double-base bidirectional bipolar transistor; devices and methods for switching
CN110419111B (zh) 2018-01-16 2023-08-15 艾鲍尔半导体 自对准且稳健的绝缘栅双极晶体管器件
WO2019157222A1 (en) 2018-02-07 2019-08-15 Ipower Semiconductor Igbt devices with 3d backside structures for field stop and reverse conduction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789396A (zh) * 2008-12-20 2010-07-28 电力集成公司 制造深沟槽绝缘栅极双极晶体管的方法
US20120056201A1 (en) * 2009-05-11 2012-03-08 Sumitomo Electric Industries, Ltd. Insulated gate bipolar transistor
CN102136490A (zh) * 2009-12-03 2011-07-27 株式会社日立制作所 半导体装置以及使用它的电力变换装置
CN104347689A (zh) * 2013-07-31 2015-02-11 万国半导体股份有限公司 双沟槽-栅极绝缘栅双极晶体管结构
US20170243745A1 (en) * 2015-10-20 2017-08-24 Maxpower Semiconductor, Inc. Vertical power transistor with deep floating termination regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116110961A (zh) * 2023-02-22 2023-05-12 强华时代(成都)科技有限公司 一种沟槽栅双极型晶体管及其制作工艺

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