CN101369532A - 沟槽形栅极的金属-绝缘体-硅器件的结构和制造方法 - Google Patents
沟槽形栅极的金属-绝缘体-硅器件的结构和制造方法 Download PDFInfo
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
在一种沟槽栅极型MIS器件中,在沟槽中形成与栅极的接触,从而消除了使栅极材料,通常为多晶硅,延伸至沟槽外的需要。这避免了沟槽上角的应力问题。栅极金属与多晶硅之间的接触通常在位于器件的有源区之外的栅极金属区中形成。描述了各种用于形成栅极金属与多晶硅之间的接触配置,包括其中沟槽在接触区中展宽的实施例。由于多晶硅回刻蚀至比整个器件的硅的表面低,通常不再需要多晶硅掩模,从而节省了制造成本。
Description
本申请是于2003年3月24日递交的题为“沟槽形栅极的MIS器件的结构和制造方法”的发明专利申请03107661.0的分案申请。
技术领域
本发明涉及一种金属-绝缘体-硅(MIS)半导体器件,并特别涉及其栅极形成在沟槽形中的此类器件。
背景技术
有一类MIS器件,其栅极形成为由硅或其它半导体材料的表面向下延伸的沟槽中。此器件中流动的电流主要是垂直的,并因此该单元可以被以更高的密度封装。在其它条件相同的情况下,这增加了电流输运能力(currentcarrying capability)并降低了器件的导通电阻(on-resistance)。属于通常的MIS器件范畴的器件包括金属-氧化物-硅场效应晶体管(MOSFET)、绝缘栅极双极型晶体管(IGBT)和MOS栅极型栅流管(thyristor)。MOSFET、IGBT和MOS栅极型栅流管中的单个栅极沟槽分别在图1、2和3中示出。
此器件中的栅极,通常为多晶硅,必须连接至器件封装的引线并通过通常为金属的导电焊垫连接至外部线路。为了实现这一点,向沟槽内填充栅极材料直至溢出,并通过光刻和腐蚀对栅极材料构图。形成图案后,通常将栅极材料限定在器件的有源区中的沟槽内,如图1、2和3所示。然而,在与栅极材料形成接触的区域,栅极材料延伸至沟槽的外部并位于硅的表面上。这在图4中的传统MIS器件40的三维剖面图中示出,其中,在非有源栅极金属区41中,多晶硅层42延伸至沟槽44的外部,并位于外延硅层46之上。沟槽44以栅极氧化层47为衬里,其中栅极氧化层47将多晶硅层42与外延层46绝缘。沟槽的端部表示为43。多晶硅层42的一部分位于厚的场氧化区48上。位于后来的栅极金属层与多晶硅层42之间的接触区表示为45。
图5A为同一器件的栅极金属区41的俯视图。图5B为同一器件沿5B-5B线截取的截面图(与图5A的坐标不同)。在此实施例中,有源区56中的MIS单元(cell)54为方形。多晶硅层42和栅极金属49与多晶硅层42之间的接触区45被示出。图6为一取自器件的栅极焊垫边缘与接线端区域的近似的俯视图。
已知沟槽的角是应力的来源,其导致了器件中与缺陷相关的问题。这在图7中示出,该图为取自沟槽44中的一个的端部附近的细节截面图。上沟槽角,表示为52,通常以导致氧化物的局部薄化和更低的氧化物击穿电压的方式来氧化。角越尖,问题变得越严重。另外,当在栅极与邻近的半导体材料(图7中的P-基体,其在MOSFET中通常与源极短接)之间施加电压差时,由于电场的拥挤现象(crowding),电场在沟槽角处达到最大。这导致了来自通过栅极氧化物的Fowler-Nordheim隧穿的漏电流,并限制了器件的最大可用栅极电压。即使在栅极氧化物层相当均匀时,电场拥挤现象的问题也会出现,其在沟槽角变得更尖时变得更严重。
因此,许多制造商使用各种技术来圆化沟槽角。然而,充分圆化上沟槽角以避免过大的栅极漏电流的问题是很困难的,并且随着单元密度的增加会变得更加困难。
另外,用于制造沟槽栅极型MOSFET的方法通常包括多个掩模步骤,并且产生了妨碍非常小的部件的精确度的不均匀形貌。图8A至8I说明了实施在N+硅衬底802上的传统工艺的步骤。该工艺由在氧化层804上形成并利用常规光刻工艺图案化的,用以限定P型盆将要形成的区域的,第一光致抗蚀剂掩模A1开始。该P型盆被用来降低沟槽的角处的电场强度。P型杂质通过掩模A1中的开口注入,以形成P型盆806,然后去除掩模A1。在通过加热驱入(drive in)P型盆806后,其使得氧化层804(图8B)变厚,沉积并构图第二掩模A2以限定器件的有源区808,变为场氧化层的氧化层804保留在器件的接线端区域810中(图8C)。
去除掩模A2,形成并构图第三,即沟槽掩模A3,以限定沟槽将要形成的位置。然后蚀刻沟槽812,通常是采用反应离子刻蚀(RIE)工艺(图8D)。沟槽812A和812B被相互连接(在纸的平面以外的第三维度上),而沟槽812C为光学“通道终止”沟槽,其位于接线端区域的外部边缘上。在腐蚀了该沟槽且去除了掩模A3以后,形成并去除牺牲氧化层以修复任何在RIE工艺中发生的晶体缺陷。在沟槽812的壁上形成栅极氧化层813。
沉积并掺杂填充沟槽812并溢出至硅表面之上的多晶硅层814。在多晶硅层814上沉积并构图第四,即多晶硅掩模A4(图8E)。除去允许由沟槽812B延伸至栅极总线区中的场氧化层804上的部分以外的多晶硅层814被回刻蚀至沟槽812内。通过多晶硅层814的此突出部形成了与沟槽812中的多晶硅层814的部分的电接触。
然后去除掩模A4,注入P型杂质,以形成P-基体区816(图8F)。然而,此杂质也影响到了多晶硅层814,其浓度在该处太低而不足以产生任何问题。
沉积并构图第五掩模A5以限定将要注入N型掺杂以形成N+源极区818的区域(图8G)。在形成N+源极区818并去除掩模A5以后,沉积并回流硼磷硅酸盐玻璃(BPSG:borophosphosilicate)层820。形成并构图第六掩模A6以限定将要形成与衬底(P-基体区域816和N+源极区818)和与栅极(多晶硅层814)的接触的位置(图8H)。注入P型掺杂以形成P+基体接触区域821,且然后沉积金属层822。在金属层822上形成并构图第七掩模(未示出)。金属层822通过第七掩模刻蚀以形成源极金属822A和栅极总线822B(图8I)。可选地,沉积一钝化层,且若在此时,形成并构图限定源极和栅极垫片,将要形成与MOSFET的外部接触的第八掩模层(未示出)。
此工艺有多个缺点。首先,需要八个掩模层,这导致了相当大的复杂度和费用。第二,场氧化层804的出现和多晶硅层814向沟槽外侧的突出产生了栅极总线822B的区域中形貌的升高。此升高区域在光刻中产生问题,特别是当器件的尺寸进一步延伸至亚微量范围时。第三,可能会产生透过多晶814和衬底802的沟槽812B的上角处的栅极氧化物的击穿。
从而,需要一种简单的工艺,形成平坦的形貌并避免沟槽的上角处的击穿问题。
发明内容
本发明提供了一种结构和技术,用于避免沟槽栅极型MIS器件中沟槽上角处的电压击穿的问题。在一半导体芯片中形成一沟槽栅极型MIS器件,其包括一包含晶体管单元的有源区、一不包含晶体管单元的栅极金属区、以及一栅极金属层。在该半导体芯片的表面上的图案中形成沟槽,该沟槽从该有源区延伸至该栅极金属区中,该沟槽具有以一种绝缘材料为衬里的壁。在该沟槽中设置一种通常为多晶硅的导电栅极材料,该栅极材料的顶面处于比该半导体芯片的顶面低的水平。一非导体层位于该有源和栅极金属区上,且在位于该栅极金属区中的沟槽的一部分上的该非导体层中形成孔。该孔被填充以一种导电材料,通常指“栅极金属”,使得该栅极金属在沟槽中的接触区中与该导电栅极材料接触。
由于该栅极材料未从该沟槽溢出至该半导体芯片的顶面,该栅极金属不会延伸至该沟槽的上角周围。这避免了当在该栅极金属与该半导体材料之间建立电压差时产生的应力。
有多种根据本发明的可能的实施例。例如,为建立该栅极材料与该栅极金属之间良好的电接触,该栅极接触材料与该栅极材料之间的接触区处的沟槽的宽度可比有源区中的沟槽的宽度大。该栅极金属可在一第一栅极指(gate finger)中与该导电栅极材料接触,该第一栅极指与一第二栅极指垂直,该第二栅极指由该有源区延伸至该栅极金属区中并与该第一栅极指交叉。
本发明的另一方面涉及一种制造MIS器件的工艺。该工艺需要比传统工艺更少的掩模步骤,且产出具有相对平整的形貌的器件,其更适于十分精细的光刻工艺。该工艺包括:在一半导体衬底表面上形成一沟槽掩模,该沟槽掩模具有用于限定沟槽位置的孔;通过该沟槽掩模中的孔刻蚀,以在该衬底中形成沟槽;去除该沟槽掩模;在该沟槽的壁上形成一第一非导电层;沉积一导电栅极材料层,使得该栅极材料溢出该沟槽至该衬底的表面上;无须掩模刻蚀该栅极材料,使得该栅极材料的顶面降低至比该衬底表面低的水平;在该衬底的表面上沉积一第二非导电层,在该第二非导电层上形成一接触掩模,该接触掩模具有孔;通过该接触掩模中的孔刻蚀,以在该第二非导电层中形成栅极接触孔;去除该接触掩模;以及,在该第二非导电层上沉积一第二导电层,该第二导电层通过该栅极接触孔延伸,以形成与栅极金属的接触。可选地,通过该接触掩模的刻蚀可在该第二非导电层中形成衬底接触孔,且该第二导电层可通过该衬底接触孔延伸,以形成与该衬底的接触,并且该工艺可包括:在该第二导电层上形成一金属掩模,该金属掩模具有孔;以及,通过该金属掩模中的孔刻蚀该第二导电层。该工艺没有包括用于刻蚀该栅极接触材料的一部分的掩模,并且可不包括用于刻蚀氧化层的一部分以形成一电场氧化区的掩模。
该工艺的多种变化都是可能的,并且该工艺可用于制造各种MIS器件,包括MOSFET、IGBT和MOS栅极型栅流管。该工艺还可用于制造具有集成肖特基或多晶硅二极管的MOSFET。
本发明还包括一种MIS器件,其具有相对平整的表面形貌。具体地,该栅极总线没有位于一厚电场氧化区上。而是,一非导电层(例如,BPSG)位于该半导体衬底的顶面上。一导电层,通常为金属,位于该非导电层上。该非导电层包括孔,金属层通过该孔与该MIS器件的有源区中的衬底(例如,MOSFET中的源极和基体)形成电接触。栅极总线也位于同一非导电层上。该栅极总线下的该非导电层的厚度基本与该器件的有源区中的非导电层的厚度相同。在一些实施例中,以导电栅极材料填充的栅极接触沟槽形成在栅极总线下的衬底中,并且该栅极总线通过该非导电层中的孔电连接至该栅极材料。
根据本发明的另一方面,两个或更多的保护沟槽形成在该栅极接触沟槽的对侧。这有助于该栅极接触沟槽比该器件的有源区中的沟槽形成得更宽、更深,而不会对该栅极接触沟槽底部的击穿电压产生负面的影响。
附图说明
图1为MOSFET中的单个栅极沟槽的截面图;
图2为IGBT中的单个栅极沟槽的截面图;
图3为MOS栅极型栅流管中的单个栅极沟槽的截面图;
图4为示出传统MIS器件中如何与栅极接触的三维剖视图;
图5A和图5B分别为图4所示的MIS器件中的栅极金属区的俯视图和截面图;
图6为取自MIS器件的栅极垫片边缘和接线端区域的俯视图;
图7为栅极沟槽的细节图,示出位于沟槽上角处的应力区域;
图8A至图8I示出了形成沟槽栅极型MOSFET的传统工艺的步骤;
图9为根据本发明的一种MIS器件的三维剖面图;
图10为根据本发明的一种MIS器件的三维剖面图,其包括平台中的P型盆;
图11为根据本发明的一种MIS器件的三维剖面图,其包括在沟槽下延伸的P型盆;
图12为由扫描电子显微镜(SEM)获取的根据本发明制造的MOS电容器的截面图;
图13为示出由各种类型的MOS电容器的栅极与硅之间的电压导致的Fowler-Nordheim隧穿的图;
图14为MIS芯片的整体俯视图,示出了如何设置有源区、栅极焊垫区、接线端区和栅极金属区;
图15A为根据本发明的第一实施例的MIS器件的栅极金属区和有源区的俯视图;
图15B为第一实施例的边缘接线端区和栅极焊垫区的俯视图;
图15C为第一实施例的栅极接触区的截面图;
图16A为根据本发明的第二实施例的MIS器件的栅极金属区和有源区的俯视图;
图16B为第二实施例的边缘接线端区和栅极焊垫区的俯视图;
图16C为第二实施例的栅极接触区的截面图;
图16D为第二实施例中,栅极指与其中形成有栅极金属与多晶硅之间的接触的栅极指之间的交叉点的细节俯视图;
图16E为第二实施例中的沟槽的截面图;
图16F为第二实施例中,栅极指与其中形成有栅极金属与多晶硅之间的接触的栅极指之间的交叉点的截面图;
图17A为根据本发明的第三实施例的MIS器件的栅极金属区和有源区的俯视图;
图17B为第三实施例的边缘接线端区和栅极焊垫区的俯视图;
图18为根据本发明的第四实施例的MIS器件的栅极金属区和有源区的俯视图;
图19为根据本发明的第五实施例的MIS器件的栅极金属区和有源区的俯视图;
图20A至20F示出了根据本发明,在MIS器件中,制造栅极多晶硅与栅极金属之间的接触的工艺的步骤;
图21A至21I示出了根据本发明的用于制造沟槽MOSFET的工艺的步骤;
图22A至22I示出了用于形成具有集成肖特基二极管的沟槽MOSFET的工艺的步骤;
图23A至23J示出了用于形成具有集成多晶硅二极管的沟槽MOSFET的传统工艺的步骤;
图24A至24I示出了根据本发明的用于形成具有集成多晶硅二极管的沟槽MOSFET的工艺的步骤;
图25A至25F示出了根据本发明通过外延地生长基体区域来制造MOSFET的工艺的步骤;
图26A示出了传统栅极接触沟槽的截面图;
图26B示出了根据本发明的栅极接触沟槽和一对保护沟槽的截面图;
图27A示出可利用图24A至24I中示出的工艺制造的多晶硅MOSFET;以及
图27B和27C分别示出对于多晶硅MOSFET的一个特殊实施例的俯视图和截面图。
具体实施方式
根据本发明,用于在MIS器件中填充沟槽的多晶硅或其它材料被回蚀或者说抑制在沟槽内,使得栅极填充材料与栅极金属之间的接触形成在沟槽内。栅极填充材料未覆盖沟槽的上角,从而,消除了由沟槽的上角处的应力产生的问题。(注意:此处所用的“多晶硅”代表任何作为栅极材料沉积在沟槽内的导电材料,可以理解,在某些实施例中可以使用金属或其它导电材料代替多晶硅作为栅极材料;类似地,“栅极金属”代表用于在沟槽内与栅极材料形成接触的导电材料,可以理解,在某些实施例中可以使用多晶硅或其它导电材料代替金属作为“栅极金属”。)
图9示出形成于生长在N+衬底81上的N型外延(epi)层82中的沟槽栅极型MIS器件80的局部视图。P型基体区83在N型外延层82中示出。栅极沟槽84以栅极氧化层85为衬里,栅极氧化层85与N型外延层82顶面上的氧化层89连接。沟槽84部分地由具有位于沟槽84之中的(例如,低于N型外延层82的顶表面)具有顶表面87的多晶硅栅极86填充。在此实施例中,沟槽84包括稍微更宽一些的横向(transverse)部分84A。顶面87的位于横向部分84A中的部分88代表将要形成多晶硅栅极86与一栅极金属层(未示出)之间的接触的位置。
与图4中示出的类似的MIS器件40相比,沟槽84中的多晶硅未按多晶硅层42的方式延伸至沟槽的上角周围。这避免了上述的应力问题。
图10示出了除在沟槽段之间的平台中的N型外延层中形成有用以保护栅极沟槽84的P型盆91以外,与MIS器件80相似的MIS器件90。在图11示出的MIS器件100中,P型盆101延伸至直接位于沟槽84下方的区域中。MIS器件90和100设计为具有高的击穿电压。
图12为由扫描电子显微镜(SEM)获取的根据本发明制造的MOS电容器的截面图。多晶硅栅极示为110而栅极金属示为112。BPSG介电层116位于沟槽114各个段之间的平台上,并在栅极金属112与沟槽114上角之间提供绝缘。
图13为示出由各种类型的MOS电容器的栅极与硅之间的电压导致的Fowler-Nordheim隧穿的图。曲线A至E对应如下器件:
表一
曲线 | 器件类型 |
A | 传统平板器件 |
B | 根据本发明的具有方形单元的器件 |
C | 根据本发明的具有带状单元的器件 |
D | 传统的具有方形单元的器件 |
E | 传统的具有带状单元的器件 |
根据图13,在从约25V至50V的范围,FN隧穿电流在根据本发明的器件中比在传统沟槽栅极型器件中低得多,且事实上其与传统平板器件中的电流很相似。
本发明的原理可施用于各种配置。几个示例,并非全部,示于图15A至15C、16A至16F、17A、17B、18和19。所有这些示例示出了一系列从MIS器件的有源区出发并进入接线端或栅极焊垫区的栅极金属区的平行“栅极指(gate finger)”。此处,术语“栅极指”代表栅极沟槽向MIS器件的有源区外的区域中的延伸,例如,有时代表“栅极金属”或“栅极总线”区或“接线端”或“边缘接线端”区。图14为MIS芯片的整体俯视图,示出了如何设置有源区、栅极焊垫区和边缘接线端区。对本领域技术人员可以接受可能有多种替代设置。
图15A示出了本发明第一实施例。方形单元型MOSFET 140包括有源区141和栅极金属区142。一系列平行的栅极指143由有源区141延伸至栅极金属区142中。源极金属的边缘表示为144;栅极金属的边缘表示为145。区域146代表栅极指143中的多晶硅与栅极金属145之间的接触区。注意,栅极指143延伸至宽部147以容纳接触区146。这有助于在沟槽中形成与沟槽的上角隔离的、良好的电接触,即使是当有源单元的尺寸变得很小的时候。图15C示出接触区146中的一个在截面15C-15C处的截面图,其示出了栅极金属148和BPSG层149。图15B示出了MOSFET 140与接线端区150和栅极焊垫151相邻的一部分的俯视图。
图16A示出了本发明的第二实施例。MOSFET 160包括有源区161和栅极金属区162。源极金属的边缘示为164,而栅极金属168的边缘示为165。一系列平行的栅极指163由有源区161延伸至栅极金属区162中。栅极多晶硅与栅极金属168之间的接触区166形成在垂直于栅极指163延伸的栅极指167中。在此实施例中,栅极指167比栅极指163宽,但这不是必需的。图16C示出沿图16A中的16C-16C截取的细节截面图。图16B为MOSFET 160的接线端区170和栅极焊垫171附近的俯视图。
因为栅极指167比栅极指163宽,在栅极指163与栅极指167之间的交点处填充沟槽可能存在问题。这种可能的问题示出于图16C至16F中。图16C为栅极指163中的一个与栅极指167之间的交点的细节俯视图。如图16E所示的沿16E-16E的截面视图示出了以多晶硅173填充的沟槽部分,而在如图16F所示的沿16F-16F的截面图中表示的栅极指163与栅极指167之间的交点处,多晶硅173并未完全填充沟槽。
这一问题可在第三实施例中克服,如图17A和17B所示。MOSFET 180与图16A和16B所示的MOSFET 160类似,除了栅极指183的间隔比栅极指163更宽,而栅极指187在与栅极指183的交点处变得更窄。栅极多晶硅与栅极金属之间的接触区186未延伸至栅极指183与187相交的区域。从而,由栅极指187的在与栅极指183交点处的宽度引起的可能的问题被避免了。当然,栅极指183之间的间隔是可变的,且无需比MOSFET 160的栅极指163之间的间隔大。图17B为MOSFET 180的接线端区190和栅极焊垫191附近的俯视图。
第四实施例,如图18所示,展示了克服上述沟槽填充问题的另一种方法。在平行的栅极指203由有源区201延伸至栅极金属区202并且与栅极指207交为直角的方面,MOSFET 200基本上与图16A所示的MOSFET 160相似,但是在MOSFET 200中,栅极指207与由栅极指207相对的两侧出发的栅极指203是交错的,其产生“T”型交点。结果,与图16A所示的设置相比,交点处的沟槽填充得到改善。多晶硅栅极与栅极金属之间的接触形成在接触区206中,接触区206沿栅极指207纵向延伸。
第五实施例,如图19所示,在包括形成有栅极多晶硅与栅极金属之间的接触的宽部227的栅极指223的方面,与图15A所示的MOSFET 140相似。然而,在MOSFET 220中,宽部227在栅极指223的纵向上彼此交错,从而有助于减少栅极指223之间的距离至超过其它情况中可能的水平。
在沟槽中形成栅极接触的工艺示出于图20A至20F。该工艺开始于包括利用传统工艺在N+衬底300中生长的N型外延层301的半导体芯片。在N型外延层301的表面中形成光致抗蚀剂沟槽掩模302,如图20A所示。如图20B所示,沟槽303通过沟槽掩模302中的开口利用反应离子刻蚀(RIE)形成。在沟槽的一定部分被扩宽以有利于栅极接触的实施例中(如图15A、16A和17),这伴随着调节沟槽掩模中的开口的宽度。然后,去除沟槽掩模302。
通常,牺牲氧化层(未示出)形成在沟槽的壁上,以修复在RIE刻蚀中产生的晶体损伤,且随后去除牺牲氧化层。栅极氧化层304热生长于沟槽的壁上。多晶硅层305沉积在N型外延层301的顶面上,填充沟槽303,形成如图20B所示的结构。
然后回蚀多晶硅层305,如图20C所示,直至多晶硅层305的顶面306低于N型外延层301的顶面307。多晶硅层305被回蚀至足以使其不再覆盖沟槽303的上角的十分重要的。多晶硅层305的表面306可正好低于N型外延层301的顶面307。注意,由于多晶硅在整个芯片上被均匀地回蚀,此工艺步骤通常可不借助掩模进行,从而降低生产的成本。
接着,硼磷硅酸盐玻璃(BPSG)层308沉积在该结构的顶面上,且以光致抗蚀剂层309为掩模。光致抗蚀剂掩模中的开口310形成在沟槽303的中央部分上,使得开口310的边缘与沟槽303的壁横向向内隔开。得到的结构如图20D所示。
BPSG层308通过在光致刻蚀剂层309中的开口310刻蚀,产生通常与开口310相一致并延伸至多晶硅305的表面306的栅极接触开口311。然后去除光致抗蚀剂层309,产生如图20E所示的结构。
如图20F,沉积金属层312。由于金属层312与多晶硅305之间的接触整个产生于沟槽303的中央区内,且由于栅极接触开口311的宽度比多晶硅层305的顶面306的宽度小,多晶硅层305与在沟槽303上角的N外延层301之间的接近被避免。正是此接近造成了上述应力问题。
如上所述,用于形成沟槽栅极型MOSFET的传统工艺需要多个掩模步骤(图8A至8I中示出的例子中的八个)且在栅极总线区中留有脊(ridge),其对小尺寸的光刻造成困难。本发明的另一方面是能避免此类问题的改善的工艺。
图21A至21F示出根据本发明的工艺步骤。该工艺以N-层402开始,该N-层402可以是覆盖N+衬底的外延层。可选地,薄氧化层404可形成在层402的表面,用于为光致抗蚀剂掩模提供附着力,或为抑制刻蚀选择性原因或为避免后面的氧化提供硬掩模。接下来,形成并构图第一光致抗蚀剂掩模B1,以限定沟槽的位置。由于层402非常平坦,掩模B1可以比现有技术中需要的掩模(例如图8D所示的掩模A3)更薄,且更小的部件(沟槽)可由此限定。沟槽406通过掩模B1利用RIE刻蚀。沟槽406包括有源区407中的沟槽406A,接线端区409中的栅极总线接触沟槽406B,以及通道终止区411中的可选通道终止沟槽406C(图21A)。沟槽406A和406B在第三维度上连接在一起。
刻蚀沟槽406后,剥去掩模B1,并且在沟槽406的壁上生长并刻蚀牺牲氧化层(未示出),以除去由RIE工艺导致的晶体缺陷。栅极氧化层408生长在沟槽406的壁上。沉积、掺杂多晶硅层410,并回刻蚀直至多晶硅层410仅保留在沟槽406内部(图21B)。注意,与图8A至8I所述的工艺不同,此工艺不需要多晶硅掩模来构图多晶硅层410。如果需要平台和接线端区上的较厚氧化层,可进行再氧化。
沉积并构图第二掩模B2,以限定将要向层402中引入基体注入物(implant)的区域。P型杂质通过掩模B2中的开口注入,并被驱入以形成P型基体区412(图21C)。与图8A至8I所述的工艺不同,此工艺不需要掩模(例如图8C中的掩模A2)来限定有源区。如果设计者希望在平台区内构图基体以实现“分立阱”结构,如J.Zeng et al.ISPSD 2000,145至148页中描述的,层402的表面非常平坦的事实使得小部件的光刻更加容易。P型杂质的注入能量选择为使杂质穿透氧化层408而非掩模B2。如果氧化层408太厚,可对其回刻蚀,以有助于通过注入来穿透。
然后,剥落第二掩模B2,清洗结构并对P型杂质退火和扩散,以实现N型层中期望的结深度。
沉积并构图第三掩模B3,以限定源极区的位置。N型杂质通过掩模B3的开口注入以形成N+源极区414(图21D)。注意,N型杂质保持在接线端区和有源区的周边以外,但允许进入靠近“通道终止”沟槽406C的区域,形成N+区415,其防止表面倒置层的形成。该结构的表面仍然很平坦,使得光刻相对容易。根据将要通过氧化层408注入的离子种类,可能需要适当利用掩模B3向下刻蚀氧化层408。
去除掩模B3并清洗该结构。
沉积并根据需要硬化诸如BPSG的介电层416。在BPSG层416上沉积第四掩模B4,并对其构图以限定接触开口(图21E)。由于结构仍然非常平坦,此光刻步骤可以使用比例如图8H中的掩模A6薄的掩模层进行。在BPSG层416通过掩模B4中的开口刻蚀后,去除掩模B4,并注入P型杂质以形成P型接触区418(图21F)。此注入降低了将要沉积的金属层与基体之间的电阻,其还可用于将雪崩击穿由沟槽附近的区域转换到沟槽之间的平台的中央区,如授予Bulucea等的美国专利No.5,072,266中所述。如果由于基体结过深而妨碍此技术,可通过构图基体杂质阻塞(blocked)的区域建立一系列分布的雪崩钳,建立杂质横向扩散的弯曲结(curved junction)。弯曲结之间的间隔可控制为设定击穿电压比有源沟槽的击穿电压低。源极接触必须在这些区域中断。另外,击穿电压可通过设计接线端区409中的击穿电压而被设定为低于有源区407的击穿电压。
注意,与栅极的接触形成在沟槽406B中,从而消除对多晶硅掩模的需要。层402的平整度使得在BPSG层416中限定小的接触开口十分容易。
另外,可使用两个分开的掩模分别形成通过BPSG层416到达栅极总线接触沟槽406B中的多晶硅层410和N型层402的接触开口,而取代利用单一掩模B4。
现在,对该结构进行范围为750℃至950℃的高温退火。如此激活P+接触注入物、激活N+源极注入物(如果其尚未被激活)并硬化BPSG层416且使其变得光滑。
沉积金属层419,在金属层419上沉积并构图第五掩模B5(图21G)。金属层419通过掩模层B5中的开口刻蚀为源极金属部分419S、栅极金属部分419G、电场电极(field plate)419F、以及边缘接线端419E。钝化层420沉积在金属层419上,且沉积并构图第六掩模B6(图21H)。钝化层420通过掩模层B6中的开口刻蚀,以暴露源极金属部分419S(图21I)。接着,通过从背面研磨减薄晶片,且可按平常形成漏极接触的方式施用背侧金属层。
示于图21A至21I的工艺与图8A至8I所示的现有技术相比提供了多个优点。本发明的工艺具有更少的步骤且成本更低。例如,需要六个而非八个掩模步骤。在整个工艺中直至金属沉积都保持了高度的硅的平整度,这有助于光刻描画小型部件及小单元间距的制造。与栅极的所有的接触都形成在沟槽内,从而避免作为当多晶硅栅极材料延伸至沟槽外并达到平台的顶面上时,通过沟槽上角的栅极氧化物的Fowler-Nordheim隧穿的结果的漏电流问题。
另外,“通道终止”沟槽406C周围的区域没有P型扩散,并且可以设有通过沟槽404C与漏极耦合的电场电极,如图21I。周边的N+区415延续了漏极的电势,这是因为,芯片的被锯的边缘成为了与漏极之间的电阻的短路。此结构通过消除了由接线端上的电荷或被辅助脱离的热载流子形成的任何倒置层,来改善较高的电压接线端的可靠性。
图21A至21I中示出的工艺可简单地适用于提供具有集成肖特基(Schottky)二极管的沟槽MOSFET,如沟槽MOS型势垒肖特基(TMBS)器件。图22A至22I示出了另一种形成具有沟槽MOS型势垒肖特基器件的沟槽型MOSFET的工艺。该工艺与图21A至21I中示出的工艺相比包括一个附加的掩模。
此工艺开始于同样可以是位于重掺杂衬底上的N-硅层502。可选地,薄氧化层504可形成在层502上,用于为光致抗蚀剂掩模提供附着力,或为抑制刻蚀选择性原因或为避免后面的氧化提供硬掩模。接着,第一光致抗蚀剂掩模形成并被构图以限定沟槽的位置。由于层502的表面非常平坦,掩模C1可比现有技术需要的掩模更薄(例如,掩模A3示于图8D中),且从而可限定更小的部件(沟槽)。沟槽506通过掩模C1利用RIE刻蚀。沟槽506包括有源区507中的沟槽506A,接线端区509中的栅极总线接触沟槽506B,通道终止区511中的可选的通道停止沟槽506C,以及肖特基二极管区513中的沟槽506D(图22A)。沟槽506A和506B(以及可选地沟槽506D)在第三维度上连接在一起。
刻蚀沟槽506后,剥去掩模C1,在沟槽506的壁上生长一牺牲氧化层并对其刻蚀以去除由RIE工艺导致的晶体缺陷。栅极氧化层508生长在沟槽506的壁上。沉积、掺杂多晶硅层510,并回刻蚀直至多晶硅层510仅保留在沟槽506内部(图22B)。与图21A至21I所述的工艺相似,此工艺不需要多晶硅掩模来构图多晶硅层510。如果需要平台和接线端区上的厚氧化层,可进行再氧化。
沉积并构图第二掩模C2,以限定将要向层502中引入基体注入物的区域。P型杂质通过掩模C2中的开口注入,并被驱入以形成P型基体区512(图22C)。与图21A至21I所述的工艺相似,此工艺不需要掩模(例如图8C中的掩模A2)来限定有源区。P型杂质的注入能量选择为使杂质穿透氧化层508而非掩模C2。如果氧化层508太厚,可对其回刻蚀,以有助于通过注入来穿透。
然后,剥落第二掩模C2,清洗结构,并对P型杂质退火和扩散,以实现N型层502中期望的结深度。
沉积并构图第三掩模C3,以限定源极区的位置。N型杂质通过掩模C3中的开口注入以形成N+源极区514(图22D)。注意,N型杂质保持在接线端区和有源区的周边以外,但允许其进入靠近“通道终止”沟槽506C的区域,从而形成N+区515。该结构的表面仍然很平坦,使得光刻相对容易。根据将要通过氧化层508注入的离子种类,可能需要利用掩模C3适当向下刻蚀氧化层508。
去除掩模C3并再次清洗该结构。
沉积并根据需要硬化诸如BPSG的介电层516。在BPSG层516上沉积第四掩模C4,并对其构图以限定接触开口(图22E)。由于结构仍然非常平坦,此光刻步骤可以使用比例如图8H中的掩模A6薄的光致抗蚀剂层进行。对BPSG层516通过掩模C4中的开口刻蚀后,去除掩模C4。沉积额外的第五掩模(接触阻断(contact block))C5,并对其构图,以覆盖肖特基二极管区513和通道终止区511的一部分。利用防止杂质进入肖特基二极管区513的掩模C5,注入P型杂质以形成P型接触区518(图22F)。此注入降低了将要沉积的金属层与基体之间的电阻,其还可用于将雪崩击穿由沟槽附近的区域转换到沟槽之间的平台的中央区,如授予Bulucea等的美国专利No.5,072,266中所述。如果由于基体结过深而妨碍此技术,可通过构图基体注入物被阻塞(blocked)的区域建立一系列分布的雪崩钳,建立杂质横向扩散的弯曲结(curved junction)。弯曲结之间的间隔可控制以设定击穿电压比有源沟槽的击穿电压低。源极接触必须在这些区域中断。另外,击穿电压可通过设计接线端区509中的击穿电压而被设定为低于有源区507的击穿电压。
注意,在沟槽506B中形成与栅极的接触,从而消除对多晶硅掩模的需要。该层的平整度使得在BPSG层516中限定小的接触开口更容易。
现在,对该结构施以范围为750℃至950℃的高温退火。如此活化P+接触注入物、活化N+源极注入物(如果其尚未被激活)并将其驱至较低的结深度,再硬化BPSG层516且使其变得光滑。
沉积金属层519,具体地,是形成与有源区507中的N+源极区514和P型基体区518的接触,以及与肖特基二极管区513中的层502的表面的接触。在金属层519上沉积并构图第六掩模C6(图22G)。金属层519通过掩模层C6中的开口刻蚀,并分为肖特基二极管区513和有源区505中的源极金属部分519S、栅极金属部分519G、电场电极(field plate)519F、以及边缘接线端519E。钝化层520沉积在金属层519上,且沉积并构图第七掩模C7(图22H)。钝化层520通过掩模层C7中的开口刻蚀,以暴露源极金属部分519S(图22I)。接着,通过从背面研磨减薄晶片,且可按平常形成漏极接触的方式施用背侧金属层。
同样要注意的是第五掩模层C5的可用性有助于防止建立暴露N+区515的BPSG层516中的开口的第四掩模层C4进入沟槽506C,并有助于金属层形成与N+区515和沟槽506A中的多晶硅之间的接触。这提供了电场电极边缘接线端与漏极之间更好的接触。
另外,沟槽MOS型势垒肖特基(TMBS)、MPS整流器或结势垒肖特基(JBS)可在相同的普通工艺流程中形成。肖特基二极管可散布在有源区中的MOSFET单元当中,或聚集在芯片的一分离部分中,如图22A至22I所示。图22A至22I的工艺提供了,目前可使用在两芯片形式中的,取代传统MOSFET-肖特基组合的有成本效益的方法。与图21A至21I示出的基本工艺相比,仅需增加一个接触阻断掩模(图22F中的掩模C5)。在如图8A至8I所示的包括肖特基二极管的八掩模现有技术工艺中,将要增加两个掩模(基体阻断掩模和接触阻断掩模),结果总共为十个掩模。
另一种可选的基本工艺有助于将多晶硅二极管集成入器件中。图24A至24I示出包含附加一个掩模的此种工艺的步骤。
需要九个掩模的传统工艺示出于图23A至23J。氧化层604和第一光致抗蚀剂掩模D1沉积在N+硅层602上,并且构图使其具有P型盆将要形成的区域中的开口(图23A)。
P型杂质通过掩模D1中的开口注入,并被驱入,形成P型盆606(图23B)。去除第一掩模D1后,形成具有用于限定有源区608的位置的开口的第二光致抗蚀剂掩模D2。通过掩模D2中的开口刻蚀氧化层604(图23D),并去除掩模D2。形成第三光致抗蚀剂掩模D3,以限定沟槽的位置。层602被刻蚀以形成有源区608中的沟槽610和通道终止区中的沟槽612(图23C)。
形成并从沟槽610的612壁上去除牺牲氧化层,再在沟槽壁上形成栅极氧化层。沉积多晶硅层614,并将N型背景杂质注入多晶硅层614。沉积低温氧化(LTO)层611。在多晶硅层614的将要形成二极管的区域上沉积第四光致抗蚀剂掩模D4。利用光致抗蚀剂掩模D4刻蚀LTO 611层以形成一掩模(图23E),并去除光致抗蚀剂掩模D4。然后,利用LTO层611为掩模,以POCl3掺杂多晶硅层614。
沉积第五掩模D5,并将多晶硅层614回刻蚀至除去区域616中的以外的沟槽610中,其中多晶硅的一部分允许覆盖在沟槽的边缘并延伸至氧化层604上(图23F)。去除掩模D5。
在沟槽610的附近注入P型杂质,并驱入以形成P型基体区618(图23G)。
沉积并构图第六N+阻断掩模D6。注入N型杂质以形成沟槽610附近的N+源极区。同样,将N型杂质注入至多晶硅层614的部分,其在多晶硅层614的N型背景掺杂区之间的结处形成二极管622和624(图23H)。去除掩模D6。
沉积BPSG层626,且在BPSG层626上沉积并构图第七接触掩模D7。掩模D7中的开口限定将要与器件的各个区域形成接触的位置。通过掩模D7中的开口刻蚀BPSG层626,并通过BPSG层626的开口注入P型杂质以形成P+接触区625(图23I)。去除掩模D7。
沉积金属层628,金属层628通过BPSG层626中的开口形成与器件的接触。在金属层628上形成第八掩模层(未示出)。通过该第八掩模层中的开口刻蚀金属层628,以形成与二极管622的阳极接触的部分628A,与二极管622的阴极和有源区中的MOSFET的源极基体区接触的部分628B,以及与二极管624的阴极接触的部分628C(图23J)。金属层628的另一部分(未示出)与多晶硅栅极(其同样是二极管624的阳极)在第三维度上接触。
金属层628的部分628A与多晶硅栅极连接,金属层628的部分628C与器件的漏极连接(都是在第三维度上)。从而,二极管622与源极基体和栅极连接,而二极管624与漏极和栅极连接。然而,如果附加了最后的钝化和焊垫掩模的话,为制造该器件需要九个掩模步骤。
前述的现有技术工艺可与图24A至24I所示的工艺相比,其中掩模步骤减少为七个。
该工艺开始于N-层702,其可为N+衬底上的外延层。可选地,可在层702的表面上形成薄氧化层704,用于为光致抗蚀剂掩模提供附着力,或为抑制刻蚀选择性原因或为避免后面的氧化提供硬掩模。接着,第一光致抗蚀剂掩模E1形成并被构图以限定沟槽的位置。由于层702的表面非常平坦,掩模E1可比现有技术需要的掩模更薄(例如,图8D中示出的掩模A3),且从而可限定更小的部件(沟槽)。沟槽706利用RIE通过掩模E1刻蚀。沟槽706包括有源区707中的沟槽706A,接线端区709中的栅极总线接触沟槽706B,以及通道终止区711中的可选的通道终止沟槽706C(图24A)。沟槽706A和706B在第三维度上连接在一起。
刻蚀沟槽706后,剥去掩模E1,在沟槽706的壁上生长并刻蚀一牺牲氧化层,以去除由RIE工艺导致的晶体缺陷。栅极氧化层708生长在沟槽706的壁上。沉积、掺杂多晶硅层710,并回刻蚀直至多晶硅层710仅保留在沟槽706内部(图24B)。如果需要平台和接线端区上的更厚的氧化层,可对其进行再氧化。
沉积并构图第二掩模E2,以限定将要向层702中引入基体注入物(bodyimplant)的区域。P型杂质通过掩模E2中的开口注入,并被驱入,以形成P型基体区712(图24C)。去除掩模E2。
在层702的表面上沉积低温氧化(LTO)层714至厚度为,例如2000并在层714上沉积第二多晶硅层716。进行利用P型杂质的多晶硅层716的覆盖性注入。在层702上沉积第三掩模E3,并构图以限定多晶硅二极管的位置(图24D)。
多晶硅层716和LTO层714被通过掩模E3中的开口刻蚀,限定多晶硅二极管,并去除掩模E3。沉积第四掩模E4,并将N型杂质通过掩模E4中的开口注入,同时形成N+源极718和二极管720的阴极(图24E)。去除掩模E4。
接着沉积BPSG层722,且在BPSG层722上沉积并构图第五掩模E5(图24F)。通过掩模E5中的开口刻蚀BPSG层722,以建立BPSG层722中的接触开口,然后去除掩模E5。通过BPSG层722中的开口注入P型杂质,以形成接触区724(图24G)。BPSG层通过加热回流。
在BPSG成722上沉积金属层726,通过BPSG层722中的开口建立与器件的电接触。在金属层726上沉积第六掩模E6,并构图(图24H)。通过掩模E6中的开口刻蚀金属层726,以将金属层726分离为与MOSFET的源极基体接线端和二极管720的阳极接触的部分726A,与二极管720的阳极和器件的栅极总线区的沟槽706B中的多晶硅接触的部分726B,形成器件的接线端区中的电场电极的部分726C,以及与器件的通道终止区中的沟槽706C中的多晶硅接触的部分726D。
图24A至24I描述的工艺还可以用于制造多晶硅MOSFET 730,如图27A至27C所示。通过掩模E1刻蚀沟槽706D。生长栅极氧化层708,并如上所述地(见图24B)沉积多晶硅层710。沉积掩模E2,并通过掩模E2中的开口注入P型杂质以在N-外延层702中形成P型区740。然后,在去除掩模E2后,在层702的表面上沉积LTO层714,并在LTO层714上沉积第二多晶硅层716(见图24D)。进行多晶硅层716的覆盖性P型注入。
多晶硅MOSFET 730可形成为多种形貌。例如,源极/漏极区可为图27B的俯视图中的交叉指型。图27C为图27B中所示结构沿27C-27C截取的截面图。
掩模E3用于对多晶硅层716和LTO层714构图,如图27A所示。同时,掩模E3还用于形成通过多晶硅层716和LTO层714到达多晶硅层710上的栅极接触区748的开口。去除掩模E3后,沉积并构图掩模E4,使得后续的通过掩模E4中的开口的N型杂质的注入形成多晶硅层716中的N+源极区742和N+漏极区744。N+区742和744与二极管720阴极同时形成(见图24E)。源极区742和漏极区744被直接位于沟槽706D上的P型基体区746分离。
沉积BPSG层722,并利用掩模E5中的开口通过BPSG层刻蚀至源极接触750、漏极接触752和基体接触754。BPSG层722中的开口被填充以金属层726,并利用掩模E6将金属层726分离为源极、漏极、基体和栅极部分(未示出)。在许多是实施例中,金属层726的源极和基体段被短接在一起,或为金属层726的单个源极-基体段的一部分。
该工艺的另一种变化可被用于通过外延器件基体区的生长制造MOSFET。此工艺在图25A至25F中示出。
首先,在N-层902上生长P型外延(epi)层904。然后在外延层904的表面上沉积并构图第一掩模F1。通过掩模F1中的开口刻蚀沟槽906,使得沟槽906A在有源区907中、沟槽906B在接线端区909中、沟槽906C在通道终止区911中、以及宽沟槽906D在接线端区909中(图25A)。在沟槽906的壁上生长牺牲氧化层(未示出),以修复由刻蚀导致的晶体缺陷。去除牺牲氧化层,并在沟槽906的壁上生长栅极氧化层908。在器件的表面上沉积、掺杂多晶硅层910,并对其进行回刻蚀使得其保留在沟槽906A、906B和906C中(图25B)。由于沟槽906D很宽,多晶硅层910被从沟槽906D中去除。
沉积并构图第二掩模F2,并通过掩模F2中的开口注入N型杂质,以形成N+源极区914和沟槽906C周围的N+区915(图25C)。去除掩模F2。
沉积BPSG层922,并在BPSG层922上沉积并构图第三掩模F3(图25D)。通过掩模F3刻蚀BPSG层922,并去除掩模F3。注入P型杂质以形成P+接触区918(图25E)。P型杂质的掺杂浓度不足以明显地影响沟槽906B中的多晶硅层910的掺杂。
沉积金属层926,并在金属层926上沉积并构图第四掩模F4。通过掩模F4中的开口刻蚀金属层926,以将金属层926分为与MOSFET的源极-基体区接触的部分926A和与沟槽906A中的多晶硅接触的部分926B。然后去除掩模F4。
此工艺具有多个优点。需要的掩模数量减少至仅仅四个。它是低热积存工艺(low thermal budget process),因为通过外延生长而非注入获得P型基体杂质无需活化和驱入。这为浅沟槽、低阈值电压和P通道器件的制造提供了便利。(当然,对于P通道器件,基体杂质为N型。)由于填充沟槽后,温度不需要超过900℃,诸如钨和钛的硅化物的材料可替代多晶硅填充沟槽。该工艺可被如图24A至24I所示的采用,以在同一器件中制造多晶硅二极管和MOSFET。
形成比器件的有源区中的沟槽宽的栅极接触沟槽是合乎需求的,如图15至19。当如此进行时,除非在刻蚀工艺中采取特殊的预防,栅极接触沟槽将同样比有源区中的沟槽深。这在图26A中示出,其示出了位于两个MOSFET沟槽952之间的栅极接触沟槽950。如果沟槽底部被与基体具有相同极性的深扩散所覆盖或屏蔽,沟槽950的增大的深度将不会产生后果。然而,在没有这样的一个深扩散时,栅极接触沟槽950下的击穿电压将比有源MOSFET沟槽952的低。等势线,在图25A中以点线示出,在沟槽950下弯曲,这代表该处的击穿电压比沟槽952下的小。
这一问题可通过在沟槽950的对侧设置屏蔽沟槽来减轻或克服,如图25B中示出的屏蔽沟槽954。屏蔽沟槽954可具有与有源MOSFET沟槽952相同的尺寸,但在此情况中不是必需的。屏蔽沟槽954应接近栅极接触沟槽950。优选地,屏蔽沟槽954与栅极接触沟槽950之间的间隔比N型外延层的厚度小,例如,与器件的有源区中的沟槽间的平台的宽度相同。屏蔽沟槽954与栅极接触沟槽950之间的平台可以是浮置的。在一些情况下,希望在栅极接触沟槽的每一侧形成两个或更多的屏蔽沟槽。该屏蔽沟槽改善了栅极接触沟槽的击穿电压,因为屏蔽沟槽与栅极接触沟槽之间有限的电荷平滑了等势线,如图25B中的点线所示。
可以理解,本领域技术人员可利用本发明宽泛的原理形成多种不同于本说明书在此描述的实施例。因此,此处描述的实施例应视为解释说明性的而非限制性的。
Claims (28)
1.一种制造MIS器件的方法,该方法包括:
在一半导体芯片的表面中形成沟槽;
在该沟槽的壁上形成一非导电层;
沉积一导电栅极材料层,使得该栅极材料溢出该沟槽之外的半导体芯片的表面上;
刻蚀该栅极材料,使得该栅极材料的顶面降低至比该衬底半导体芯片表面的所有区域都低的水平。
2.如权利要求1的方法,其中该刻蚀在没有掩模的情况下进行。
3.一种制造MIS器件的方法,该器件包括一有源区和一接线端区,该方法包括:
在一半导体衬底的表面上形成一沟槽掩模,该衬底被以具有第一导电类型的材料掺杂,该沟槽掩模具有用于限定接线端沟槽将要形成的位置的孔;
通过该沟槽掩模中的孔刻蚀,以形成该衬底中的接线端沟槽;
去除该沟槽掩模;
在该接线端沟槽的壁上形成一第一非导电层;
向该接线端沟槽中沉积一导电栅极材料层,该导电的栅极材料溢出该沟槽至该衬底的表面上;
在没有掩模的情况下刻蚀该栅极材料,使得该接线端沟槽中的栅极材料的顶面降低至比该衬底的表面低的水平;
在该衬底的表面上沉积一第二非导电层;
在该第二非导电层上形成一接触掩模,该接触掩模具有栅极接触孔;
通过该接触掩模的栅极接触孔刻蚀该第二非导电层,以在该第二非导电层中形成栅极接触孔;
去除该接触掩模;以及
在该第二非导电层上沉积一第二导电层,该第二导电层通过该栅极接触孔延伸,以形成与接线端沟槽中的导电栅极材料的接触。
4.如权利要求3的方法,其中该接触掩模具有衬底接触孔,该方法包括通过该接触掩模中的衬底接触孔的刻蚀该第二非导电层,以在该第二非导电层中形成衬底接触孔,且其中在该第二非导电层上沉积一第二导电层使得该第二导电层通过该衬底接触孔延伸以形成与该衬底的接触。
5.如权利要求4的方法,包括在该第二导电层上形成一金属掩模,该金属掩模具有孔,以及,通过该金属掩模中的孔刻蚀该第二导电层,以形成该第二导电层的与该栅极材料电接触的第一部分和第二导电层的与该衬底电接触的第二部分,该第二导电层的第一和第二部分彼此电绝缘。
6.如权利要求3的方法,其中该方法不包括用于刻蚀该氧化物层的一部分以形成该接线端区中的电场氧化区的掩模。
7.如权利要求3的方法,包括在该衬底的表面上形成一具有孔的基体掩模,并通过该基体掩模中的孔向该衬底中注入具有第二导电类型的杂质以形成一基体区。
8.如权利要求3的方法,其中该沟槽掩模包括该有源区中的第二孔和一通道终止区中的第三孔,以及,其中该方法包括通过该第二和第三孔刻蚀该衬底已形成该有源区中一有源沟槽和该通道终止区中的一通道终止沟槽。
9.如权利要求8的方法,包括在该衬底上形成一源极掩模,该源极掩模在该衬底的与该有源沟槽相邻的区域具有孔,并且通过该源极掩模中的孔注入第一导电类型的杂质以形成该MIS器件的源极区。
10.如权利要求9的方法,其中该源极掩模包括该通道终止区中的一第二孔,且该方法包括向与该通道终止沟槽相邻的区域注入第一导电类型的杂质。
11.如权利要求4的方法,包括通过该第二非导电层中的该衬底接触孔注入第二导电类型的杂质,以形成该衬底中的重掺杂接触区。
12.如权利要求8的方法,其中
沉积一导电栅极材料层包括向该通道终止沟槽沉积该导电栅极材料;
在没有掩模的情况下刻蚀该栅极材料包括降低该通道终止沟槽中的栅极材料的表面至低于该衬底表面的水平;
该接触掩模在该通道终止沟槽上具有一第二孔;
该方法包括通过该接触掩模中的第二孔刻蚀该第二非导电层以暴露该通道终止沟槽中的该导电栅极材料的表面;以及
沉积该第二导电层包括导致该第二导电层流入该接触掩模中的第二孔并与该通道终止沟槽中的导电栅极材料电接触。
13.如权利要求3的方法,其中
该第二导电层包括金属;
该沟槽掩模包括第二孔;
该方法包括通过该沟槽掩模中的第二孔刻蚀该衬底以在该衬底中形成一肖特基二极管沟槽;
沉积一导电栅极材料层包括向该肖特基沟槽中沉积导电栅极材料;
该基体掩模覆盖该肖特基沟槽和该衬底的邻近区域;
该接触掩模具有位于该衬底的与该肖特基沟槽相邻的区域上的第二孔;
该方法包括通过该接触掩模的第二孔刻蚀该第二非导电层以暴露该衬底的与该肖特基沟槽相邻的区域;以及
沉积该第二导电层包括导致该第二导电材料填充该接触掩模中的第二孔,并与该衬底的临近该肖特基沟槽的区域形成电接触,以形成一肖特基二极管。
14.如权利要求3的方法,其中该沟槽掩模包括在该有源区中的第二孔,以及,其中该方法包括通过该第二孔刻蚀该衬底以形成在该有源区中的有源沟槽。
15.如权利要求14的方法,包括:
在该衬底上沉积一多晶硅层;
向该多晶硅层中引入一种第二导电类型的杂质;
在该多晶硅层上形成一多晶硅掩模,该多晶硅掩模限定将要形成的多晶硅二极管的位置;
刻蚀该多晶硅层的未被该多晶硅掩模覆盖的区域;
去除该多晶硅掩模;
形成一源极掩模,该源极掩模具有在该衬底的与该沟槽邻近的区域上的第一孔和该多晶硅层区域上的第二孔;以及
通过该源极掩模中的第一和第二孔注入第一导电类型的杂质,以形成该MIS器件的源极区和一多晶硅二极管的接线端。
16.如权利要求15的方法,其中:
沉积一第二非导电层在通过该源极掩模中的第一和第二孔注入第一导电类型的杂质以后进行;
该接触掩模具有位于该多晶硅二极管阳极上的阳极孔和位于该多晶硅二极管阴极上的阴极孔;
该方法包括通过该接触掩模中的阳极和阴极孔刻蚀该第二非导电层,以分别形成该第二非导电层中的阳极和阴极接触孔;以及
沉积第二导电层包括导致该第二导电层流入该阳极和阴极接触孔,以分别与该多晶硅二极管的阳极和阴极形成电接触。
17.如权利要求15的方法,其中
该多晶硅掩模限定一将要形成的多晶硅MOSFET的位置;
该沟槽掩模包括在该有源区中的一第三孔,该方法包括通过该第三孔刻蚀该衬底以形成一多晶硅MOSFET沟槽;以及
其中该源极掩模具有至少一个限定该多晶硅MOSFET中的区域的开口。
18.如权利要求3的方法,其中
在该第二非导电层上形成一第二接触掩模,该第二接触掩模具有一衬底接触孔;
通过该第二接触掩模中的该衬底接触孔刻蚀该第二非导电层,以在该第二非导电层中形成一衬底接触孔;以及
其中在该第二非导电层上沉积一第二导电层使得该第二导电层通过该衬底接触孔延伸,以与该衬底形成接触。
19.一种制造MIS器件的方法,包括:
提供一个以第一导电类型的杂质掺杂的半导体衬底;
在一半导体衬底上生长一第二导电类型的外延层;
在该外延层的表面上形成一沟槽掩模,该沟槽掩模具有在该器件的有源区中的第一孔和在该器件的接线端区中的第二孔,该接线端区位于该有源区与一通道终止区之间;
通过该沟槽掩模中的第一和第二孔刻蚀该外延层,以形成第一和第二沟槽,该第二沟槽基本比该第一沟槽宽;
去除该沟槽掩模;
在该第一和第二沟槽的壁上形成一第一非导电层;
向该第一和第二沟槽中沉积一导电栅极材料层,该导电栅极材料层溢出该沟槽至该衬底的表面上;
刻蚀该导电栅极材料,使得该第一沟槽中的该导电栅极材料的表面降低至比该衬底的表面低的水平,而该第二沟槽中的导电栅极材料基本被去除;
向该外延层的表面上、该第一沟槽中的栅极材料上和该第二沟槽中沉积一第二非导电层;
在该第二非导电层上形成一接触掩模,该接触掩模具有衬底接触孔和栅极接触孔;
通过该接触掩模的孔刻蚀该第二非导电层,以在该第二非导电层中形成衬底接触孔和栅极接触孔;
去除该接触掩模;以及
在该第二非导电层上沉积一第二导电层,该第二导电层通过该衬底接触孔延伸以形成与衬底的接触,该第二导电层通过该栅极接触孔延伸以形成与该导电栅极材料的接触。
20.如权利要求19的方法,包括:
在该第二导电层上形成一金属掩模,该金属掩模具有孔;以及
通过该金属掩模中的孔刻蚀该第二导电层。
21.一种沟槽栅极型MIS器件,包括一有源器件区和一通道终止区,该器件包括:
一半导体衬底,通常掺杂为第一导电类型;
一外延层,位于该衬底上;
一第一沟槽,形成在该器件的有源区中的外延层中,一绝缘层沿该沟槽的壁设置,该沟槽含有一种导电栅极材料,该导电栅极材料的表面处于比该外延层的表面低的水平;
一第二沟槽,形成在该外延层的位于该有源区与该通道终止区之间的位置,在该第二沟槽的至少一个位置中,该第二沟槽基本比该第一沟槽宽;
一非导电层,位于该有源区中的外延层上,该非导电层具有在有源区中的孔;以及
一导电层位于该非导电层上,该导电层包括一载流部分和一栅极总线部分,该载流部分位于该有源区中,该栅极总线部分位于该有源区与该通道终止区之间,该载流部分通过该非导电层中的孔延伸,以形成与该外延层之间的电接触,
其中位于该导电层的栅极总线部分下面的非导电层的厚度基本与位于该导电层的载流部分下面的非导电层的厚度相同。
22.如权利要求21的沟槽栅极型MIS器件,还包括一第三沟槽,其位于该栅极总线的下面的外延层中,该第三沟槽包含导电栅极材料,该非导电层具有第二孔,通过该第二孔,该导电层的栅极总线部分与该第三沟槽中的栅极材料电接触。
23.一种沟槽栅极型MIS器件,具有一有源区和一栅极总线区,该器件包括:
一半导体衬底,一第一沟槽形成在该有源区中的衬底中,一第二沟槽形成在该栅极总线区中的衬底中,一绝缘层沿该第一和第二沟槽中的每一个的壁设置,该第一和第二沟槽中的每一个包含一种导电栅极材料,在该第二沟槽的位置的至少一个中,该第二沟槽比该第一沟槽宽且深,该第二沟槽中的导电栅极材料与一栅极总线电接触;
至少一对保护性沟槽形成在该第二沟槽的相对的两侧,该第二沟槽比该保护性沟槽深,该保护性沟槽中的每一个包含导电栅极材料,该保护性沟槽中的导电栅极材料与该第二沟槽中的导电栅极材料电接触。
24.如权利要求23的沟槽栅极型MIS,其中在该保护性沟槽中的至少一个与该第二沟槽之间的平台有助于电浮置(electrically float)。
25.如权利要求23的沟槽栅极型MIS,其中该保护性沟槽具有基本与该第一沟槽相同的宽度和深度。
26.一种沟槽栅极型MIS器件,形成在一半导体芯片中,其包括:
一有源区,包含晶体管单元;
一栅极金属区,不包含晶体管单元;
一第一和一第二栅极指由该有源区延伸至该栅极金属区;以及
一栅极金属层,
其中,在该半导体芯片的表面的图案中形成沟槽,该沟槽从该有源区延伸至该栅极金属区中,该沟槽具有以一种绝缘材料层为衬里的壁,在该沟槽中设置一种导电栅极材料,该栅极材料的顶面处于比该半导体芯片的顶面低的水平,一非导体层位于该有源区和栅极金属区上,在位于该栅极金属区中的沟槽的一部分上的该非导体层中形成孔,该孔被填充以一种栅极金属,使得该栅极金属在沟槽中与接触区中的该导电栅极材料接触。
27.如权利要求26的沟槽栅极型MIS器件,其包括一位于该栅极金属区中的该非导电层上的栅极金属层,该栅极金属层与该栅极材料电接触。
28.如权利要求27的沟槽栅极型MIS器件,其中该栅极金属层沿着与该栅极金属区中的沟槽的方向垂直的方向纵向地延伸。
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-
2002
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-
2003
- 2003-03-21 EP EP12176149.8A patent/EP2511955B1/en not_active Expired - Lifetime
- 2003-03-21 EP EP03006486.9A patent/EP1351313B1/en not_active Expired - Lifetime
- 2003-03-24 CN CN2008101492031A patent/CN101369532B/zh not_active Expired - Lifetime
- 2003-03-24 CN CNB031076610A patent/CN100433366C/zh not_active Expired - Lifetime
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2004
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2007
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2010
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102859699A (zh) * | 2010-03-02 | 2013-01-02 | 维西埃-硅化物公司 | 制造双栅极装置的结构和方法 |
CN102859699B (zh) * | 2010-03-02 | 2016-01-06 | 维西埃-硅化物公司 | 制造双栅极装置的结构和方法 |
CN103633135A (zh) * | 2012-08-15 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | 一种沟槽型双层栅功率mos器件的接触孔版图 |
CN103633135B (zh) * | 2012-08-15 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | 一种沟槽型双层栅功率mos器件的接触孔版图 |
CN103854964A (zh) * | 2012-11-30 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | 改善沟槽栅分立功率器件晶圆内应力的方法 |
CN103854964B (zh) * | 2012-11-30 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | 改善沟槽栅分立功率器件晶圆内应力的方法 |
Also Published As
Publication number | Publication date |
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EP2511955A3 (en) | 2013-07-03 |
EP2511955A2 (en) | 2012-10-17 |
US7335946B1 (en) | 2008-02-26 |
CN100433366C (zh) | 2008-11-12 |
EP1351313A2 (en) | 2003-10-08 |
US9324858B2 (en) | 2016-04-26 |
CN1455459A (zh) | 2003-11-12 |
US20030178673A1 (en) | 2003-09-25 |
EP1351313B1 (en) | 2016-01-20 |
JP5651097B2 (ja) | 2015-01-07 |
US7868381B1 (en) | 2011-01-11 |
EP1351313A3 (en) | 2007-12-26 |
US20040113201A1 (en) | 2004-06-17 |
US20110042742A1 (en) | 2011-02-24 |
CN101980356A (zh) | 2011-02-23 |
JP2012060147A (ja) | 2012-03-22 |
JP2003309263A (ja) | 2003-10-31 |
US7005347B1 (en) | 2006-02-28 |
CN101369532B (zh) | 2010-10-27 |
EP2511955B1 (en) | 2017-07-05 |
JP5379339B2 (ja) | 2013-12-25 |
CN101980356B (zh) | 2013-04-03 |
US6838722B2 (en) | 2005-01-04 |
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