CN102237279A - 用三个或四个掩膜制备的氧化物终止沟槽mosfet - Google Patents

用三个或四个掩膜制备的氧化物终止沟槽mosfet Download PDF

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CN102237279A
CN102237279A CN2011100802704A CN201110080270A CN102237279A CN 102237279 A CN102237279 A CN 102237279A CN 2011100802704 A CN2011100802704 A CN 2011100802704A CN 201110080270 A CN201110080270 A CN 201110080270A CN 102237279 A CN102237279 A CN 102237279A
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groove
insulation
gate
mask
oxide
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CN102237279B (zh
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雷燮光
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种氧化物终止半导体器件可以由多个栅极沟槽、一个栅极滑道以及一个绝缘终止沟槽构成。这些栅极沟槽位于有源区中。每个栅极沟槽都含有一个导电栅极电极。绝缘终止沟槽位于包围着有源区的终止区中。用绝缘材料填充绝缘终止沟槽，以制备半导体器件的绝缘终止。该器件可以利用三掩膜或四掩膜工艺制备。

Description

用三个或四个掩膜制备的氧化物终止沟槽MOSFET
技术领域
本发明主要是关于沟槽金属氧化物半导体场效应管(MOSFET)，更确切地说，是关于氧化物终止沟槽MSOFET以及仅用三个或四个掩膜制成的此类器件及其制备方法。
背景技术
DMOS(双扩散MOS)晶体管是一类利用两个顺序扩散阶梯，校准到一个公共边上，以构成晶体管的通道区的金属氧化物半导体场效应管(MOSFET)。DMOS晶体管通常是高电压、高电流器件，既可以作为分立式晶体管，也可以作为功率集成电路的元件。DMOS晶体管仅用很低的正向电压降，就可以在单位面积上产生高电流。
典型的DMOS晶体管是一种叫做沟槽DMOS晶体管的器件，其中通道位于沟槽的侧壁上，栅极形成在沟槽中，沟槽从源极延伸到漏极。其沟槽栅极，布满了薄氧化层并且用多晶硅填充，这种沟槽栅极比平面垂直DMOS晶体管结构对电流的限制还低，因此它的导通电阻率较小。
然而，制备这种沟槽DMOS场效应管的传统方法，需要五至六个掩膜工艺，不仅价格昂贵而且耗费时间。
制备沟槽MOSFET的传统方法需要五至六个掩膜。第一个掩膜是一个深势阱掩膜，它也可用于高压终止。根据要制备的器件是否是高压器件，来选择是否使用该掩膜。第二个掩膜是一个沟槽掩膜，用于为栅极和其他器件结构，制备沟槽。第三个掩膜是一个本体掩膜，它也可用于制备终止区，保护栅极滑道中的栅极氧化物不会由于暴露于漏极电势而受到破坏，并屏蔽栅极垫/电极不受漏极电压的影响。第四个掩膜是一个源极掩膜，将源极区移至远离栅极滑道以及终止区的地方，使击穿电流转移出这些区域，提高非钳位感应开关(Unclamped inductive switching，简称UIS)性能。第四个掩膜也可用于制备通道终点。第五个掩膜是一个接触掩膜，用于制备源极/本体和栅极接头，第六个掩膜是一个金属掩膜，用于将金属层分成栅极和源极金属区。
图1表示由上述传统的六掩膜工艺制备的沟槽MOSFET 100的剖面图。如图1所示，沟槽MOSFET 100包括位于有源区中的有源单元102和栅极滑道104。栅极滑道连接到有源单元102中的栅极上。略有风险的是，沿N-外延层111的顶面可能会形成一个接近晶片末端的p-反演通道(P-inversion channel)。这个p-反演通道如果从结终止108开始，触及晶片边缘112，就会在源极/本体和漏极之间，引起泄露。在晶片边缘112处，可将一个重掺杂的N+通道终点106短接至漏极，从而阻止这种p-反演通道触及晶片边缘112。
正是在这一前提下，我们提出了本发明的各种实施例。
发明内容
鉴于上述问题，本发明提供一种用于制备绝缘终止半导体器件的方法，包括：
步骤a：在半导体衬底上，使用沟槽掩膜；
步骤b：通过沟槽掩膜，刻蚀半导体衬底，形成第一沟槽TR1、第二沟槽TR2和第三沟槽TR3，宽度分别为W1、W2和W3，其中第三沟槽TR3是最窄的沟槽，其中第一沟槽TR1包围着第三沟槽TR3；
步骤c：在第三沟槽TR3中制备导电材料，以构成栅极电极，在第二沟槽TR2中制备导电材料，以构成栅极滑道；
步骤d：用绝缘材料填充第一沟槽TR1，以构成包围着栅极电极的绝缘隔绝沟槽；
步骤e：在整个衬底顶部，制备一个本体层；
步骤f：在整个本体层顶部，制备一个源极层；
步骤g：在半导体衬底上方，应用一个绝缘层；
步骤h：在绝缘层上方，应用一个接触掩膜；
步骤i：穿过绝缘层，形成到源极层和到栅极滑道的接触开口；并且
步骤j：在绝缘层上，形成源极和栅极金属区，分别与源极和栅极滑道接头电接触。
上述的方法，步骤j包括：
在绝缘层上方，沉积一个金属层；
在金属层上方，使用一个金属掩膜；并且
通过金属掩膜，刻蚀金属层，以形成栅极金属和源极金属。
上述的方法，步骤c包括：
在第一沟槽TR1、第二沟槽TR2和第三沟槽TR3中，制备一个栅极电介质；
在第一沟槽TR1、第二沟槽TR2和第三沟槽TR3中，沉积导电材料，其中选取导电材料的厚度填满第二沟槽TR2和第三沟槽TR3，但不填满第一沟槽TR1；并且
各向同性地回刻导电材料，以便在第三沟槽TR3中形成栅极电极，在第二沟槽TR2中形成栅极滑道，其中第一沟槽TR1中的导电材料被完全除去。
上述的方法，进行步骤e和步骤f无需使用额外的掩膜。
上述的方法，还包括：
在第一沟槽TR1的底部，植入一个通道终点。
上述的方法，被绝缘隔绝沟槽包围着的区域内部的源极和本体层，处于源极电势，绝缘隔绝沟槽外部的源极和本体区，处于漏极电势。
上述的方法，有源栅极形成在有源区中，绝缘隔绝沟槽邻近所述的有源区。
上述的方法，半导体衬底还包括一个重掺杂的底层和一个次重掺杂的顶层，其中
制备第一沟槽TR1，使第一沟槽TR1向下触及到所述的重掺杂的底层中。
上述的方法，进行步骤a和步骤b仅使用一个单独的掩膜，并且根据单独掩膜中的开口，同时刻蚀第一沟槽TR1、第二沟槽TR2、第三沟槽TR3。
上述的方法，进行步骤a和步骤b包括：
在半导体衬底上，使用第一沟槽掩膜；
刻蚀半导体衬底，以形成第一沟槽TR1和第二沟槽TR2；
在半导体衬底上，使用第二沟槽掩膜；并且
刻蚀半导体衬底，以形成第三沟槽TR3。
上述的方法，还包括：
用绝缘材料填充第一沟槽TR1和第二沟槽TR2；并且
制备第四沟槽TR4，其中第四沟槽TR4形成在第二沟槽TR2中的绝缘材料顶部。
上述的方法，制备第四沟槽TR4是利用所述的第二沟槽掩膜。
上述的方法，步骤c包括：
在第三沟槽TR3中，制备一个栅极电介质；并且
在第三沟槽TR3和第四沟槽TR4中，制备导电材料，以便在第三沟槽TR3中形成栅极电极，在第四沟槽TR4中形成栅极滑道。
本发明所提供的一个绝缘终止半导体器件，包括：
多个位于有源区中的栅极沟槽，每个栅极沟槽都含有一个导电栅极电极；
一个栅极滑道；以及
一个绝缘隔绝沟槽，位于包围着有源区的终止区中，其中用绝缘材料填充绝缘隔绝沟槽，以形成半导体器件的绝缘终止。
上述的绝缘终止半导体器件，还包括遍及整个器件的源极和本体区。
上述的绝缘终止半导体器件，有源区中的源极和本体区处于源极电势，绝缘隔绝沟槽外部的源极和本体区处于漏极电势。
上述的绝缘终止半导体器件，栅极滑道形成在栅极滑道沟槽中。
上述的绝缘终止半导体器件，还包括一个栅极接头，其中栅极接头和栅极滑道沟槽位于栅极沟槽之间的有源区中。
上述的绝缘终止半导体器件，还包括一个植入到绝缘隔绝沟槽底部的通道终点。
上述的绝缘终止半导体器件，半导体器件还包括一个半导体衬底，该衬底具有一个重掺杂的底层和一个次重掺杂的顶层，其中绝缘隔绝沟槽触及重掺杂的底层。
上述的绝缘终止半导体器件，一部分栅极滑道形成在绝缘隔绝沟槽中的绝缘材料中。
上述的绝缘终止半导体器件，还包括一个栅极接头，其中栅极接头和部分栅极滑道位于被绝缘隔绝沟槽包围的区域之外。
上述的绝缘终止半导体器件，绝缘隔绝沟槽邻近有源区。
上述的绝缘终止半导体器件，栅极沟槽与绝缘隔绝沟槽部分合并。
上述的绝缘终止半导体器件，在绝缘隔绝沟槽中形成一个额外的栅极滑道。
本领域的技术人员阅读以下较佳实施例的详细说明，并参照附图之后，本发明的这些和其他方面的优势无疑将显而易见。
附图说明
阅读以下详细说明并参照以下附图之后，本发明的其他特征和优势将显而易见。
图1表示一种传统的沟槽MOSFET器件的剖面图。
图2表示依据本发明的第一实施例，一种氧化物终止沟槽MOSFET的剖面图。
图3A表示依据本发明的第一实施例，氧化物终止沟槽MOSFET布局的俯视图。
图3B表示图3A中所示的氧化物终止沟槽MOSFET沿线A-A和B-B的合并剖面图。
图3C表示图3A中所示的氧化物终止沟槽MOSFET沿线A-A的剖面图。
图3D表示图3A中所示的氧化物终止沟槽MOSFET的交叉点C处的透视图。
图4A表示依据本发明的第一实施例，氧化物终止沟槽MOSFET的第一可选布局的俯视图。
图4B表示图4A中所示的氧化物终止沟槽MOSFET沿线A-A和B-B的合并剖面图。
图5A表示依据本发明的第一实施例，氧化物终止沟槽MOSFET的第二可选布局的俯视图。
图5B表示图5A中所示的氧化物终止沟槽MOSFET沿线A-A和B-B的合并剖面图。
图6表示图3B所示的氧化物终止沟槽MOSFET的剖面图，其通道终点植入在终止沟槽底部。
图7表示依据本发明的第二实施例，一种氧化物终止沟槽MOSFET的剖面图。
图8A表示依据本发明的第二实施例，氧化物终止沟槽MOSFET布局的剖面图。
图8B表示图8A中所示的氧化物终止沟槽MOSFET沿线A-A和B-B的合并剖面图，其通道终点植入在终止沟槽底部。
图9A-9O表示依据本发明的第一实施例，图2和图3A中所示的氧化物终止沟槽MOSFET的制备过程的剖面图。
图10A-10K表示依据本发明的第二实施例，图7和图8A中所示类型的氧化物终止沟槽MOSFET的制备过程的剖面图。
具体实施方式
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的任何技术人员都应理解基于以下细节的多种变化和修正都属本发明的范围。因此，本发明的典型实施例的提出，对于请求保护的发明没有任何一般性的损失，而且不附加任何限制。
在本发明的实施例中，用氧化物终止代替传统沟槽MOSFET中的结终止，从而消除了结终止击穿，提高了UIS性能，并且由于氧化物所需的空间比传统的结终止所需的空间小得多，从而节省了原来被结终止所占的空间。此外，通过将嵌入式二极管限制在有源区，改善了反向恢复。
依据第一实施例，栅极滑道位于氧化物终止中。图2表示氧化物终止沟槽MOSFET200的剖面图。如图2所示，氧化物终止沟槽MOSFET 200包括一个位于有源区中的有源单元202，以及一个位于大型氧化物填充沟槽206内部的栅极滑道(Gate runner)204，大型氧化物填充沟槽206位于终止区中。含有硼酸的硅玻璃(BPSG)等电介质207，以及/或大型氧化物填充沟槽206，可用于使栅极垫213与漏极电压绝缘。氧化物填充沟槽206，也称为氧化物终止沟槽或绝缘沟槽，向下触及到重掺杂衬底208中。氧化物终止沟槽206阻止p-反演层穿过它，从而不需要使用单独带掩膜的通道终点。氧化物终止沟槽MOSFET 200的氧化物终止结构消除了结终止击穿，从而提高了UIS性能。如图下图9A-9O所示，制备氧化物终止沟槽MOSFET 200的方法仅仅需要四个掩膜：一个绝缘沟槽掩膜、一个栅极沟槽掩膜、一个接触掩膜以及一个金属掩膜。在本方法中，不再需要深势阱掩膜、本体掩膜和源极掩膜。
图3A表示依据本发明的第一实施例的一种可选版本，氧化物终止沟槽MOSFET 300布局的俯视图，图3B表示氧化物终止沟槽MOSFET 300沿线A-A和B-B的合并剖面图。
氧化物终止沟槽MOSFET 200和氧化物终止沟槽MOSFET 300的不同之处在于，氧化物终止沟槽MOSFET 200中的大型氧化物填充沟槽206被氧化物终止沟槽MOSFET 300中的较小的氧化物填充沟槽308和绝缘氧化物沟槽304代替，绝缘氧化物沟槽304作为氧化物终止沟槽MOSFET 300中的通道终点和器件终止。较小的氧化物填充沟槽308和绝缘氧化物沟槽304比氧化物终止沟槽MOSFET 200中的大型氧化物填充沟槽206更加易于制备。如图3A-3B所示，氧化物终止沟槽MOSFET300包括一个位于有源区中的有源栅极沟槽302，一个位于终止区中的绝缘氧化物沟槽304，以及一个位于终止区中的氧化物填充沟槽308内部的栅极滑道306。根据预设的所需电压，选择栅极滑道306的一侧和氧化物填充沟槽308的外壁之间的距离t，t通常约为几千埃。电压越高，所需的距离t越厚。例如，所加电压为60V的话，距离t约为2000埃。通常，击穿场约为10MV/cm，为了运行稳定，计算厚度时，击穿场要小于7MV/cm。如图3B所示，由于在晶片边缘312处短接，绝缘氧化物沟槽304外部的源极319和本体318区域，包括栅极滑道306周围的区域，都处于漏极电势。由于绝缘沟槽外部的本体区318处于漏极电势，不会构成嵌入式体二极管(与有源区本体区318相反)，因此不会增加体二极管电荷，从而提高了器件的反向恢复。
所形成的BPSG层307足够厚，使栅极垫313与漏极电势绝缘。氧化物终止沟槽MOSFET 300的大多数结构都形成在N-外延层316上方，N-外延层316位于N+衬底317上。略有风险的是，沿绝缘沟槽304的侧壁，在N-外延层316中可能会形成一个P-反演通道，从而在绝缘氧化物沟槽304的底部附近引起泄露。通过使沟槽深至N+衬底317中，重掺杂的N+衬底317可作为通道终点，阻止这种泄露。如图3A和3B所示，绝缘氧化物沟槽304临近有源区，MOSFET单元和有源栅极就形成在绝缘氧化物沟槽304上。
图3C表示图3A所示的线A-A的剖面图，以及附近的晶片边缘312。如图可知，与原有技术的结终止相比，绝缘氧化物沟槽304使有源区形成在更靠近晶片边缘312的地方。
图3D表示一部分氧化物终止沟槽MOSFET 300，在终止区中，绝缘氧化物沟槽304和氧化物填充沟槽308之间的交叉点C处的透视图。以绝缘氧化物沟槽304为界的内部区域314是一个有源区，其中源极319和本体318区域(图3D中没有表示出)处于源极电势。在以绝缘氧化物沟槽304为界的区域外部的外部区域315(终止区)中，源极319和本体318区域(图3D中没有表示出)处于漏极电势。如图3D所示，在内部区域314上的多晶硅310是一个具有栅极氧化物的栅极多晶硅。在外部区域315上，多晶硅310为栅极滑道306，并通过绝缘氧化物沟槽304和氧化物填充沟槽308的氧化物电绝缘。
图4A表示依据本发明的第一实施例，氧化物终止沟槽MOSFET 400的一个可选布局的俯视图，图4B表示氧化物终止沟槽MOSFET 400沿线A-A和B-B的剖面图。
与氧化物终止沟槽MOSFET 300类似，沟槽MOSFET 400含有栅极沟槽302和绝缘氧化物沟槽304，以及一个位于氧化物填充沟槽308中的栅极滑道306，其中绝缘氧化物沟槽304形成得足够深，穿过N-外延层316触及N+衬底317，作为终止结构，为MOSFET器件提供通道终点。此外，沟槽MOSFET 400还含有一个位于栅极沟槽302外部的额外的栅极沟槽402，靠近绝缘氧化物沟槽304，这个额外的栅极沟槽402的大约一半的宽度，都与绝缘氧化物沟槽304重叠。在图3B所示的氧化物终止沟槽MOSFET300中，略有风险的是，由于绝缘沟槽另一侧上的漏极电势，形成在绝缘氧化物沟槽304的侧壁内部的有源区(P-)的本体区318中的(n-)通道，可能会产生漏电流。这个额外的栅极沟槽402屏蔽该区域不受漏极电势的影响，并阻止该通道开启。
图5A表示依据本发明的第一实施例，氧化物终止沟槽MOSFET 500的另一个可选实施例布局的俯视图，图5B表示氧化物终止沟槽MOSFET 500沿线A-A和B-B的剖面图。
与氧化物终止沟槽MOSFET 300类似，沟槽MOSFET 500含有栅极沟槽302和绝缘氧化物沟槽304，以及一个位于氧化物填充沟槽308中的栅极滑道306，其中绝缘氧化物沟槽304作为终止结构，为MOSFET器件提供通道终点。此外，沟槽MOSFET 500还含有一个位于栅极沟槽302外部、并在绝缘氧化物沟槽304中的额外的栅极滑道502。与沟槽MSOFET 400的额外的栅极沟槽402相类似，额外的栅极滑道502也屏蔽了形成在绝缘沟槽304内部的寄生n-通道。
图6表示氧化物终止沟槽MOSFET 600的剖面图，氧化物终止沟槽MOSFET 600与氧化物终止沟槽MOSFET 300相类似，还含有一个植入在氧化物填充沟槽308底部的通道终点(Channel stop)602，以及一个植入在绝缘氧化物沟槽304底部的通道终点604。在本实施例中，氧化物填充沟槽308和绝缘沟槽304都没有深至触及N+衬底619(无论沟槽是比之前更浅，还是外延层618比之前更深)，因此，可以在氧化物填充沟槽308、绝缘氧化物沟槽304的底部中形成自对准的N+植入物，以构成通道终点602和604。
在第二实施例中，可以用一个具有栅极滑道的氧化物终止，代替传统的沟槽MOSFET的结终止，其中栅极滑道位于有源单元区中。图7表示氧化物终止沟槽MOSFET 700的剖面图。如图7所示，氧化物终止沟槽MOSFET 700含有有源单元702以及栅极滑道704，其中栅极滑道704位于有源单元702之间的有源区中。氧化物终止706位于终止区中。通道终点708植入在氧化物终止706的底部。沟槽MOSFET 700的氧化物终止结构消除了结终止击穿，从而提高了UIS性能。如同下图10A-10K所示，制备氧化物终止沟槽MOSFET 700的方法仅仅需要三个掩膜：一个栅极沟槽掩膜、一个接触掩膜以及一个金属掩膜。在本方法中，省去了深势阱掩膜、本体掩膜以及源极掩膜。
沟槽MOSFET 700和沟槽MOSFET 800的不同之处在于，沟槽MOSFET 700中的大型氧化物终止706，被沟槽MOSFET 800中较小的氧化物绝缘沟槽804代替。图8A表示氧化物终止沟槽MOSFET 800布局的俯视图，图8B表示氧化物终止沟槽MOSFET800沿线A-A和B-B的剖面图。
如图8A-8B所示，沟槽MOSFET 800含有位于有源区中的栅极沟槽802，每个栅极沟槽802都含有一个栅极电极，以及一个位于终止区的氧化物绝缘沟槽804，用于终止有源单元。栅极滑道808沉积在有源区中，位于有源栅极沟槽802的中心。如果通道终点806没有深至触及衬底(图中没有表示出)的话，就可以植入到氧化物绝缘沟槽804的底部。
图9A-9O表示用于制备上述图3A-3B所示类型的氧化物终止沟槽MOSFET的四掩膜工艺的剖面图。如图9A所示，提出了一种半导体衬底，该衬底含有例如位于重掺杂衬底902上方，相对轻掺杂的外延层904。外延层904可以掺杂n-，衬底902可以掺杂n+，这仅作为示例，不作为局限。氧化层906可以形成在外延层904的顶面上。作为示例，可以通过热氧化作用和低温氧化物沉积或高密度等离子(HDP)相结合，制备氧化物。如图9B所示，在氧化层906上方，使用第一掩膜908，也就是绝缘沟槽掩膜，该掩膜带有开口图案，限定了绝缘和栅极滑道沟槽。通过穿过氧化层906、外延层904，还可选择衬底902的顶部，刻蚀形成沟槽910、911。这是通过利用氧化物刻蚀，穿过氧化层906，随后利用硅刻蚀，刻蚀到外延层904中，来实现的。氧化物刻蚀后，氧化层906可以用作硅刻蚀的硬掩膜。沟槽910将在制备过程中，形成栅极滑道。为了简便，沟槽910指的就是栅极滑道沟槽。另一个沟槽911可用于为有源区制备绝缘氧化物终止。为了简便，该沟槽911指的就是绝缘氧化物沟槽。如果沟槽911没有触及(n+)衬底，那么通道终点植入物(图中没有表示出)就可以在此时形成在沟槽底部。
沟槽910、911的宽度约为1.5微米，这仅作为示例，不作为局限。如图9C所示，可以除去第一掩膜908，用氧化物912填充沟槽910、911，然后压实致密，并进行化学-机械-抛光(CMP)。
如图9D所示，薄氧化层914可以生长或沉积在沟槽910和外延层904的上方。在薄氧化层914上方，使用第二掩膜916，即沟槽掩膜，该掩膜带有开口图案，限定了沟槽。如图9E所示，通过穿过薄氧化层914以及掩膜开口920中的部分氧化物912的刻蚀，在沟槽910中形成栅极滑道空腔918，最好选择氧化物刻蚀，而不是硅刻蚀。然后，如图9F所示，利用同一个掩膜916，通过硅刻蚀，刻蚀外延层904，制备沟槽922。稍后，在制备过程中，利用沟槽922制备栅极垫/电极。为了简便，这些沟槽922指的就是栅极沟槽。沟槽910比沟槽922更宽，以便形成栅极滑道空腔918。通常，栅极滑道空腔也比沟槽922更宽，以便增强传导，并为栅极金属接触留出空间。典型的栅极滑道空腔918的宽度约为1.0微米，沟槽922的宽度约为0.4至0.8微米。
然后，如图9G所示，除去第二个掩膜916，并形成牺牲氧化物(之后会被除去)以及栅极氧化物。如图9H所示，导电材料926(例如多晶硅)可以沉积在沟槽918和922中，以及栅极氧化物924上方。可以用掺杂物(例如n+型掺杂物)掺杂导电材料926，使其导电性能更强。然后，如图9I所示，回刻导电材料926，以便在沟槽918中形成栅极滑道930，在沟槽922中形成栅极电极928。
如图9J所示，无需使用掩膜，就可在外延层904的顶部形成本体层932。例如通过整体垂直或带角度的植入以及扩散，与外延层的掺杂物类型相反的适宜的掺杂物，可以制成本体层932。掺杂离子可以穿过氧化层924植入。作为示例，如果外延层为n-掺杂，那么可以用p-型掺杂物掺杂本体层，反之亦然。如图9K所示，无需使用掩膜，源极层934形成在本体层932顶部。例如通过氧化层924进行整体垂直或带角度的植入适宜的掺杂物，并退火，可以制成源极层934。制备源极层所植入的掺杂物，其类型通常与本体层932的类型相反。例如，如果本体层932所掺杂的为p-型，那么源极层934将掺杂n-型，反之亦然。
如图9L所示，绝缘层936，例如一个低温氧化层和含有硼酸的硅玻璃(BPSG)，形成在该结构上方，然后压实致密，并进行CMP平整化。
如图9M所示，接触掩膜938形成在绝缘层936上，并形成带有开口的图案，开口限定接触孔。接触掩膜938是该工艺中所用的第三个光掩膜。绝缘层936、源极层934以及部分本体层932，都可以通过掩膜中的开口刻蚀，以形成源极/本体接触孔942，例如通过氧化物刻蚀以及硅刻蚀，向下刻蚀沟槽918中的氧化物以及一部分栅极滑道930，以形成栅极接触孔940。
如图9N所示，可以在接触孔940和942中沉积一个势垒材料(例如Ti/TiN)层944。然后，利用导电(例如钨(W))插头946，填满接触孔940和942。在源极区934上方，接触孔942中的势垒金属944和钨插头946提供源极/本体接头。在栅极滑道930上方，接触孔940中的势垒金属944和钨插头946提供栅极接头。金属层948，例如Al-Si，可以沉积在制成的结构上方。
在金属层948上，形成一个带图案的金属掩膜(图中没有表示出)，形成图案并制备，通过金属刻蚀，将金属层948分成多个电绝缘部分，这些电绝缘部分构成栅极和源极金属(例如栅极金属950和源极金属952)，从而制成类似于图3A-3B所示的半导体器件氧化物终止沟槽MOSFET300的器件。金属掩膜是该工艺中所用的第四个光掩膜。在源极区上方，接触孔942中的势垒金属944和钨插头946，提供从源极层934和本体层932到源极金属952的源极/本体接头。在沟槽910上方，接触孔940中的势垒金属944和钨插头946提供从栅极滑道930到栅极金属950的垂直栅极滑道接头。此后，无需使用额外的掩膜，就可以在器件的背面，形成漏极金属(图中没有表示出)。
在一个可选实施例中，可以利用三掩膜工艺，制备氧化物终止沟槽MOSFET。作为示例，图10A-10K表示用于制备上述图8A-8B所示类型的氧化物终止沟槽MOSFET的三掩膜工艺的剖面图。如图10A所示，提出了一种半导体衬底，该衬底含有一个位于重掺杂(例如n+)衬底1002上方的相对轻掺杂(例如n-)的外延层1004。氧化层1006形成在外延层1004的顶面上。作为示例，可以通过热氧化作用和低温氧化物沉积或高密度等离子(HDP)相结合，制备氧化物。如图10B所示，在氧化层1006上方，使用第一掩膜1008，也就是沟槽掩膜，该掩膜带有开口图案，限定了沟槽。通过穿过氧化层1006、外延层1004，还可选择衬底1002的顶部，刻蚀形成沟槽1010、1012、1014。沟槽开口越宽，制成的沟槽就越深，因此利用同一个掩膜刻蚀过程，可以同时形成不同宽度的沟槽。随后，可以利用沟槽1014，在工艺中制成有源栅极电极。为了简便，沟槽1012指的就是栅极沟槽。随后，可以利用沟槽1012，在工艺中制成栅极滑道沟槽。为了简便，该沟槽1012指的就是栅极滑道沟槽。可以利用另一个沟槽1010，制备有源区的绝缘氧化物终止。为了简便，该沟槽1010指的就是绝缘氧化物沟槽。
栅极滑道沟槽1012比栅极沟槽1014更宽，例如1.2微米。氧化物终止沟槽1010比栅极滑道沟槽1012更宽，例如1.5微米。对于一个特定的刻蚀过程，掩膜开口越宽，通过各向异性刻蚀工艺(例如干刻蚀)刻蚀的沟槽越深。
然后，如图10C所示，除去第一个掩膜1008，并在沟槽侧壁上形成牺牲氧化物和栅极氧化物1016。如图10D所示，在栅极氧化物1016上方，导电材料(例如多晶硅)1018可以沉积在沟槽1010、1012和1014中。选取导电材料1018的厚度，使其可以填满所有较小的沟槽1012和1014，但不填满最宽的沟槽1010。最宽的沟槽1010仅仅内衬有导电材料1018。可以用掺杂物，例如n+型掺杂物，掺杂导电层1018，以增强其导电性能。
如图10E所示，可以各向同性地回刻导电层1018，刻蚀终点在外延层1004的顶面以下，以便在沟槽1012中形成栅极滑道1022，在沟槽1014中形成栅极电极1020。在该刻蚀过程中，完全除去沟槽1010中的导电材料1018。如果通道终点1024没有触及衬底1002，那么可以选择在沟槽1010的底部植入通道终点1024。如图10F所示，氧化物1026沉积在所制成的结构上方，以便填充在沟槽1010中以及沟槽1012和1014的顶部，然后进行化学-机械-抛光(CMP)。
如图10G所示，在外延层1004的顶部，形成本体层1030。例如通过垂直或带角度的植入和扩散，与外延层1004的类型相反的掺杂物，来制备本体层1030。如图10H所示，可以在本体层1030的顶部形成一个源极层1032。通过垂直或带角度的植入和扩散，与本体层的类型相反的掺杂物，并退火，来制备源极层1032。
如图10I所示，绝缘层1034，例如低温氧化层和含有硼酸的硅玻璃(BPSG)，可以形成在该结构上方，然后压实致密，并进行CMP平整化。接触掩膜1036可以形成在绝缘层1034上，形成带有限定接触孔图案的开口。接触掩膜1036是该过程中所用的第二个光掩膜。通过掩膜中的开口，刻蚀绝缘层1034、源极层1032以及本体层1030的顶部，以形成源极/本体接触孔1038。通过掩膜中的开口，刻蚀绝缘层1034和栅极滑道1022的顶部，以形成栅极接触孔1039。
如图10J所示，导电势垒材料(例如Ti/TiN)层1040可以沉积在接触孔1038和1039内，以及绝缘层1034上方。然后，利用导电(例如钨(W))插头1042填满接触孔1038和1039。源极区1032上方，接触孔1038中的势垒材料1040和导电插头1042，提供源极/本体接头。栅极滑道1022上方，接触孔1039中的势垒材料1040和导电插头1042，提供栅极接头。金属层1044，例如Al-Si，可以沉积在制成的结构上方。
带图案的金属掩膜(图中没有表示出)沉积在金属层1044上，并通过金属刻蚀，将金属层1044分成多个电绝缘部分，这些电绝缘部分构成栅极和源极金属(例如栅极金属1048和源极金属1046)，从而制成类似于图8A-8B所示的半导体器件800的器件。金属掩膜是该过程中所用的第三个光掩膜。无需额外的掩膜，就可以在器件的背部形成漏极金属。源极区上方，接触孔1038中的势垒材料1040和导电插头1042，提供从源极层1032和本体层1030到源极金属1046的源极/本体接头。沟槽1012上方，接触孔1039中的势垒金属1040和导电插头1042，提供从栅极滑道1022到栅极金属1048的垂直栅极滑道接头。
由此可知，通过本发明的实施例制备沟槽MOSFET器件，比传统工艺所用的掩膜要少。所制成的结构消除了结终止击穿，提高了UIS性能，并且由于氧化物所占的空间比传统的结终止所占的空间小得多，从而节省了结终止所占的空间。另外，通过将嵌入式体二极管限定在有源区，提高了反向恢复。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在其他版本。例如，上述示例所示的是一种n-通道MOSFET器件，但是只要转换各区域的导电类型，就可应用于p-通道MOSFET。而且，尽管所述的是MOSFET，但本领域的技术人员也应理解，同样的原理也适用于IGBT器件。此外，氧化物也可以用另一种合适的绝缘物替代。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义和功能的局限。

Claims (25)

1.一种用于制备绝缘终止半导体器件的方法，其特征在于，包括：
步骤a：在半导体衬底上，使用沟槽掩膜；
步骤b：通过沟槽掩膜，刻蚀半导体衬底，形成第一沟槽TR1、第二沟槽TR2和第三沟槽TR3，宽度分别为W1、W2和W3，其中第三沟槽TR3是最窄的沟槽，其中第一沟槽TR1包围着第三沟槽TR3；
步骤c：在第三沟槽TR3中制备导电材料，以构成栅极电极，在第二沟槽TR2中制备导电材料，以构成栅极滑道；
步骤d：用绝缘材料填充第一沟槽TR1，以构成包围着栅极电极的绝缘隔绝沟槽；
步骤e：在整个衬底顶部，制备一个本体层；
步骤f：在整个本体层顶部，制备一个源极层；
步骤g：在半导体衬底上方，应用一个绝缘层；
步骤h：在绝缘层上方，应用一个接触掩膜；
步骤i：穿过绝缘层，形成到源极层和到栅极滑道的接触开口；并且
步骤j：在绝缘层上，形成源极和栅极金属区，分别与源极和栅极滑道接头电接触。
2.如权利要求1所述的方法，其特征在于，步骤j包括：
在绝缘层上方，沉积一个金属层；
在金属层上方，使用一个金属掩膜；并且
通过金属掩膜，刻蚀金属层，以形成栅极金属和源极金属。
3.如权利要求1所述的方法，其特征在于，步骤c包括：
在第一沟槽TR1、第二沟槽TR2和第三沟槽TR3中，制备一个栅极电介质；
在第一沟槽TR1、第二沟槽TR2和第三沟槽TR3中，沉积导电材料，其中选取导电材料的厚度填满第二沟槽TR2和第三沟槽TR3，但不填满第一沟槽TR1；并且
各向同性地回刻导电材料，以便在第三沟槽TR3中形成栅极电极，在第二沟槽TR2中形成栅极滑道，其中第一沟槽TR1中的导电材料被完全除去。
4.如权利要求1所述的方法，其特征在于，进行步骤e和步骤f无需使用额外的掩膜。
5.如权利要求1所述的方法，其特征在于，还包括：
在第一沟槽TR1的底部，植入一个通道终点。
6.如权利要求1所述的方法，其特征在于，被绝缘隔绝沟槽包围着的区域内部的源极和本体层，处于源极电势，绝缘隔绝沟槽外部的源极和本体区，处于漏极电势。
7.如权利要求1所述的方法，其特征在于，有源栅极形成在有源区中，绝缘隔绝沟槽邻近所述的有源区。
8.如权利要求1所述的方法，其特征在于，半导体衬底还包括一个重掺杂的底层和一个次重掺杂的顶层，其中
制备第一沟槽TR1，使第一沟槽TR1向下触及到所述的重掺杂的底层中。
9.如权利要求1所述的方法，其特征在于，进行步骤a和步骤b仅使用一个单独的掩膜，并且根据单独掩膜中的开口，同时刻蚀第一沟槽TR1、第二沟槽TR2、第三沟槽TR3。
10.如权利要求1所述的方法，其特征在于，进行步骤a和步骤b包括：
在半导体衬底上，使用第一沟槽掩膜；
刻蚀半导体衬底，以形成第一沟槽TR1和第二沟槽TR2；
在半导体衬底上，使用第二沟槽掩膜；并且
刻蚀半导体衬底，以形成第三沟槽TR3。
11.如权利要求1所述的方法，其特征在于，还包括：
用绝缘材料填充第一沟槽TR1和第二沟槽TR2；并且
制备第四沟槽TR4，其中第四沟槽TR4形成在第二沟槽TR2中的绝缘材料顶部。
12.如权利要求11所述的方法，其特征在于，制备第四沟槽TR4是利用所述的第二沟槽掩膜。
13.如权利要求11所述的方法，其特征在于，步骤c包括：
在第三沟槽TR3中，制备一个栅极电介质；并且
在第三沟槽TR3和第四沟槽TR4中，制备导电材料，以便在第三沟槽TR3中形成栅极电极，在第四沟槽TR4中形成栅极滑道。
14.一个绝缘终止半导体器件，其特征在于，包括：
多个位于有源区中的栅极沟槽，每个栅极沟槽都含有一个导电栅极电极；
一个栅极滑道；以及
一个绝缘隔绝沟槽，位于包围着有源区的终止区中，其中用绝缘材料填充绝缘隔绝沟槽，以形成半导体器件的绝缘终止。
15.如权利要求14所述的绝缘终止半导体器件，其特征在于，还包括遍及整个器件的源极和本体区。
16.如权利要求15所述的绝缘终止半导体器件，其特征在于，有源区中的源极和本体区处于源极电势，绝缘隔绝沟槽外部的源极和本体区处于漏极电势。
17.如权利要求14所述的绝缘终止半导体器件，其特征在于，栅极滑道形成在栅极滑道沟槽中。
18.如权利要求17所述的绝缘终止半导体器件，其特征在于，还包括一个栅极接头，其中栅极接头和栅极滑道沟槽位于栅极沟槽之间的有源区中。
19.如权利要求14所述的绝缘终止半导体器件，其特征在于，还包括一个植入到绝缘隔绝沟槽底部的通道终点。
20.如权利要求14所述的绝缘终止半导体器件，其特征在于，半导体器件还包括一个半导体衬底，该衬底具有一个重掺杂的底层和一个次重掺杂的顶层，其中绝缘隔绝沟槽触及重掺杂的底层。
21.如权利要求14所述的绝缘终止半导体器件，其特征在于，一部分栅极滑道形成在绝缘隔绝沟槽中的绝缘材料中。
22.如权利要求14所述的绝缘终止半导体器件，其特征在于，还包括一个栅极接头，其中栅极接头和部分栅极滑道位于被绝缘隔绝沟槽包围的区域之外。
23.如权利要求14所述的绝缘终止半导体器件，其特征在于，绝缘隔绝沟槽邻近有源区。
24.如权利要求23所述的绝缘终止半导体器件，其特征在于，栅极沟槽与绝缘隔绝沟槽部分合并。
25.如权利要求23所述的绝缘终止半导体器件，其特征在于，在绝缘隔绝沟槽中形成一个额外的栅极滑道。
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