經濟部中央標準局貝工消費合作社印製 308735 A7 一 B7 五、發明説明（） 本發明係有闞於溝榷式DMOS之结構及製程，特別 是有闞於一新穎及改良溝榷DMOS霣晶體的結構及製程 ，在溝槽的终端處有新穎的«極接線法，用Μ達成高崩潰 電颳效應*並可省略多晶矽光軍數，因之可降低成本。 習知技術： 一般生產習知的溝槽式雙擴散金羼氧化物半導體（D M0S)的技術中仍有其雞處所在，在溝槽的终點附近底 下*閘極接觸點的閘择氧化層有些脆弱的地方而造成的技 術上之困難。由於在終端匾多晶矽W極下面的閘氧化曆的 特別組態•埴些脃弱的終點易因崩潰電壓而受損。為了要 提供「閘極延長線」來形成阐/極接觸點，多晶矽閛極在终 點附近的組態是覆蓋在溝的邊緣Μ及角落上，Μ致在閘槿 下的閘極氧化層形成了一些脆弱點•當加Μ閛極電壓時即 常提前崩潰。瑄些脆弱點影響了 DMOS元件的可靠度* 而相對提高了元件測試和生產時之費用。 為更易了解本發明的技術背景，首先描述一個一般溝 槽式DMOS電晶體。第一_顯示一在核心單元區内一儷 典型的DMO S單元1 0的截面圖。此核心區在一個Ν + 基髓1 5上，其上並形成一涸Ν-晶瞑層20，單元1 0 含有一深的Ρ體區25，一源極區30在其中包圍著一閘 極溝榷40，並藉Κ閘捶氧化層3 5來諶兩者絕緣。此D MOS單元10上有一PSG或BPSG保護層45覆蓋 並Μ閘極接觸點55，源極和體接觸點50和一汲極接觭 點60來向外連接。此满權式閛極结構的優點在於可Μ不 -3 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 經濟部中央標準局貝工消费合作社印製Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 308735 A7-B7 V. Description of the invention () This invention is based on the structure and process of the DMOS-type DMOS, especially the novel and improved DMOS-type crystal The structure and manufacturing process have a novel «polar connection method at the end of the trench, which uses M to achieve a high breakdown electric scraping effect * and can omit the polysilicon optical force, so that the cost can be reduced. Conventional technology: The general production of the conventional trench double-diffusion gold oxide semiconductor (D MOS) technology still has its place, and the gate selective oxidation of the gate contact point under the trench near the end point Technical difficulties caused by some fragile areas. Due to the special configuration of the gate oxidation calendar under the terminal plaque polysilicon W poles, some weak end points are easily damaged by the breakdown voltage. In order to provide the "gate extension line" to form the gate / pole contact point, the polysilicon electrode is arranged near the end point to cover the edge and corner of the trench, M resulting in the formation of the gate oxide layer under the gate Some fragile points • When the M electrode voltage is applied, it often collapses in advance. These weak points affect the reliability of DMOS components * and relatively increase the cost of component testing and production. For easier understanding of the technical background of the present invention, a general trench DMOS transistor is first described. First_shows a cross-sectional view of a typical DMOS cell 10 in the core cell area. This core region is on a N + basal medulla 15 and a Ν-crystal layer 20 is formed thereon. The unit 10 contains a deep P body region 25, and a source region 30 surrounds a gate electrode therein Discuss 40, and use the K gate oxide layer 35 to insulate the two. The D MOS cell 10 has a PSG or BPSG protective layer 45 covering the gate contact 55, the source and body contact 50 and a drain junction 60 to connect outward. The advantage of this full-power dynamite structure is that it can not be -3-This paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X297mm) (please read the precautions on the back before filling in this page) Printed by the Beigong Consumer Cooperative of the Ministry of Central Standards
308735 A7 B7五、發明説明（） 必受到平面型DMO S在縮短多晶矽長度時所造成J F E T電阻增大的限制，而可Μ縮短多晶矽的長度來增加單元 的密度。溝槽式DMOS電晶艘的另一優點是高單元密度 可使通路電阻降低。 第二圖係一DMOS電晶體70在终端區75附近的 截面圖。在核心單元區含有複數個如第一圖所示DMOS 單元10的單元*包含源極區30 > Ρ體區25 ·在溝槽 中形成的多晶矽閘極，源極接觸點50，汲極接觸酤60 。在終端區75處•為了要製造閘極接觸黏55·從核心 區閘極40延伸出來在溝80內的閘搔跑道（runner) 8 5 特為增長至高於溝播80的表面之上，來形成一個多晶矽 接觸墊88。此墊可提供較大的面積來和閘極接觸點55 接觸。但是•在形成多晶矽接觭墊時需要在溝榷80的邊 緣和角落上形成一氧化絕緣層（即.閘極氧化層）來使多晶 矽8 5和PSI區2 5間互相絕緣。這一氧化絕緣曆產生一 特別的問題而影響DMO S元件的可靠度。由於邊緣和角 落的特別的型態·此一氧化絕緣層形成後常常不均勻•厚 度較薄，而品質也差，尤其在角落三度空間的闞係，比起 在邊緣上只有兩度空間的情況•品質更差，Μ致於這些胎 弱的部位成了過早崩潰的主要原因。角落和邊緣點90就 成為DMO S元件的脆弱點。 伯陸西亞（Bulucea)等在美画專利5,072,266案「具有 場形體分佈和三度空間的满襦式DMOSj中揭露（一九 九一年十二月十日發表）一有多角形溝槽的M0SFET (請先閱讀背面之注意事項再填寫本頁) -4 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） 308735 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 功率元件，其中閛極的位置即為颳抑閘極傍氧化物介質的 崩潰而定。此專利中採用一深的體接面，一半位在溝槽之 下來將崩潰電壓専離溝槽表面而引到半導趙的主體。 伯陸西亞等所揭露的元件结構和製程可控制半導暖主 體的崩潰。原因係利用在溝槽中閘極的位置並利用二度空 間有整場形作用的摻雜劑的分佈情況•其含有一中央深的 P +層横向與P體區2 5接連·縱向與晶膜層20接連。 此發明所揭露的元件具有在核心單元部位設計上和製程上 的改進，卻沒有解決Μ上所述在终端區溝權的《緣及角落 上的技術困難。 鄺（Kwan)等在另一美國專利案5,316,759「用六個光 軍製造满槽式DMOS法」揭露一種可以減少所需光軍數 的满榷式DM0 S製程。但此專利中亦沒有提到上述因辱 溝槽的邊緣和角落二度及三度空間造成氧化曆提早崩潰的 問題•反之，此專利中所揭露之元件在其终靖區中的多晶 矽環有浮動電壓而可能造成崩潰電屋之不穩定性。 故在功率元件之製造技術上，尤其有翡DM0S之設 計及製程，埴些限制仍有待解決。爰是* 本發明之主要目的在於提供一改良的溝檐式DMO S 结構和製程來克眼上述因為溝槽的邊緣各角落處二度及三 度空間效應而造成在閘極氧化曆中過早崩潰的困難。 具體而言，本發明在於提供一改良的DMOS结構和 製程，其中第一個改良的结構是在溝榷終點沿多晶矽指（ fingers)之上除去多晶矽曆而打開一個閘極窗口，使W極 -5 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨〇父297公釐） (請先閱讀背面之注意事項再填寫本頁) -β308735 A7 B7 V. Description of the invention () It must be limited by the increase in the J F E T resistance caused by the planar DMOS in shortening the polysilicon length, and the length of the polysilicon can be shortened to increase the cell density. Another advantage of trench DMOS transistors is that the high cell density reduces the via resistance. The second diagram is a cross-sectional view of the DMOS transistor 70 near the termination region 75. In the core cell area, there are a plurality of cells as shown in the first figure. DMOS cell 10 includes source area 30 > Ρ body area 25. Polysilicon gate formed in the trench, source contact 50, drain contact酤 60. In the terminal area 75 • In order to make the gate contact adhesive 55 • The gate runner 5 8 extending from the core area gate 40 in the trench 80 is specially grown above the surface of the trench 80. A polysilicon contact pad 88 is formed. This pad provides a larger area to contact the gate contact 55. However, when forming the polysilicon contact pad, it is necessary to form an oxide insulating layer (ie, gate oxide layer) on the edges and corners of the trench 80 to insulate the polysilicon 8 5 and the PSI region 25 from each other. This oxidative insulation history creates a special problem that affects the reliability of DMOS components. Due to the special shape of the edges and corners • This oxidized insulating layer is often uneven after it is formed • The thickness is thin and the quality is also poor, especially in the three-dimensional corner of the Kan system, compared to the two-dimensional space on the edge Situation • The quality is worse, and the weak parts of these fetuses have become the main cause of premature breakdown. The corner and edge points 90 become the weak points of DMOS components. Bulucea et al. Disclosed in the US Patent No. 5,072,266 "Full-shaped DMOSj with field shape distribution and three-dimensional space (published on December 10, 1991). A polygonal trench M0SFET (Please read the precautions on the back before filling out this page) -4-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public daughter) 308735 A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs () Power element, where the position of the prism pole is determined by the collapse of the oxide dielectric near the gate electrode. This patent uses a deep body junction, half of which is below the trench to separate the breakdown voltage from the trench The surface leads to the body of the semi-conducting Zhao. The component structure and process disclosed by Borussia and others can control the collapse of the semi-conducting warm body. The reason is to use the position of the gate electrode in the trench and use the second-degree space to have a full field shape. Distribution of active dopants • It contains a central deep P + layer laterally connected to the P body region 25 and vertically connected to the crystal film layer 20. The device disclosed in this invention has the design and manufacturing process of the core unit on Improvement, but did not solve the technical difficulties in the edge and corner of the right of the terminal area mentioned in M. Kwan et al. Disclosed in another US Patent 5,316,759 "Using the Six Light Army to Make a Full-Slot DMOS Method" A full-blown DM0 S process that can reduce the number of optical troops required. However, this patent does not mention the problem of the early collapse of the oxidation calendar caused by the second and third degree spaces of the edges and corners of the trench. On the contrary, the components disclosed in this patent have polysilicon rings in their final area Floating voltage may cause instability of the collapsed electric house. Therefore, in the manufacturing technology of power components, especially the design and manufacturing process of DM0S, some limitations still need to be resolved.焰 是 * The main purpose of the present invention is to provide an improved trench eaves type DMOS structure and process to overcome the above-mentioned premature oxidation of the gate due to the second and third spatial effects at the corners of the trench edge The difficulty of collapse. Specifically, the present invention is to provide an improved DMOS structure and process. The first improved structure is to remove the polysilicon calendar along the polysilicon fingers at the end of the trench and open a gate window to make the W- 5-This paper scale is applicable to China National Standard (CNS) Α4 specification (297mm 2). (Please read the precautions on the back before filling this page) -β
A7 A7 經濟部中央標隼局員工消費合作社印製 1'發明説明（） 氧化層與溝槽角落重叠的三度空間效應得Μ除去·而產生 的脆弱黏所造成的困難得Μ解決。 本發明的另一個目的，在於提供一改良的溝槽式DM OS结構和製程，其中第二個改良结構是形成一終端閘極 接觸跑道並在其中開閘窗口，因此可解決在脆弱點崩溃的 困難。 本發明的另一個目的，在於提供一改良的溝槽式DM OS结構和製程*其中第三個改良结構是形成一特寬的終 端閘棰跑道和在此特寬跑埴之上開閘極接觸窗口可供做閘 掻接觸黏•因之可以免去把閘棰多晶矽提升到溝槽之上的 必要性，而解決了在脆弱點處提前崩潰和閘極接觸點不良 的困難。 本發明另一目的，在於提供一改良的满播式DMOS 结構和製程•其中採用一簡化的製程即K植入特寬的閘極 跑道Μ減少製程中所需的光罩數而降低成本支出。 為使貴審査委員瞭解本發明之目的、特戡及功效， 玆》由下述具體之實施例•並配合所附之圔示，對本發明 做一詳细說明： 圖示之簡單說明： 第一匾為習知技術中一般性DMOS之截面圖； 第二圖為在習知技術中DMOS的终端區附近各暦结構的 截面園，其中因多晶矽閘極的结溝形成了易崩潰的 脃弱點； 第三Α圖和第四Α_顯示本發明中改良的DMO S在终端 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公嫠） (請先閱讀背面之注意事項再填寫本頁) 裝· ,1Τ 經濟部中央標準局員工消費合作社印製 A 7 B7 i、發明説明（） 區附近的结構俯視画，由於開了閘極窗口，消除了 閘極氧化層在溝檐角落覆蓋部份，因之改進了閘極 氧化層的可靠度； 第三B圖和第四B圖分別為第三A圓和第四A騸相對的截 面國； 第五圖和第六圖為改良的DMOS结構在終端區附近的俯 視圖，其中在終端區中形成一特寬的閘棰跑道Μ供 放置閘極接觸點而消除閘極氧化層满槽邊緣和角落 的覆葚部份，因之改進了閘棰氧化層的可靠度； 第七圖是本發明中改良的DMOS元件的截面蹰，其中脃 弱點所造成的崩漬問題得以解決；和 、’ 第八Α_至第八Η圖顯示生產第三圖至第七圖中的DMO S元件的各步驟。 首先*請參閱第三Α圖係為本發明第一實施例的DM OS電晶雔100的俯視圖。電晶體100含有一核心單 元區1 05，其中又包含有複數個的單元1 1 0，每一個 單元有源惲接點115和在溝中形成的多晶矽閘極120 。此閘棰做「多晶矽指」狀從核心區1 05延伸至終端區 1 25。在此終端區開了複數個閘極窗口，是用加K特別 組態的多晶矽光罩從窗口中除去多晶矽屜而成的。第三B 圖為沿A-A >媒的截面匾。DM0S電晶體1 00是形 成在基體102上的晶膜盾104的表面上。满榷形成後 在其上沉横一層多晶矽層1 2.0，此暦和晶膜曆1 04之 間並有一閘槿氧化層1 2 1絕緣。其後，用一多晶矽光罩 表紙張尺度逋用中國國家標準（CNS )八4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 装- 訂 經濟部中央標準局負工消费合作社印製 308735 A7 B7 i、發明説明（） 來把核心單元部份105溝槽上的多晶矽除去。在終端區 125靠近_榷終點130處的光罩上也開了複數涸窗口 來除去多晶矽Μ形成窗口 1 40。電晶»1 00也含有一 PSG或BPSB層122形成於多晶矽層120和窗口 1 40之上，然後用接觭光單來形成源極接觸點1 24和 閘極接觸點1 26，其中閘棰接觸骷1 26和终端區1 2 5以及閘棰跑道128有専霣接觸。 因在终點130附近開了多晶矽窗口140·故多晶 矽靥1 20在近终點處不會提升在溝權之上。因之在近終 點處的溝榷角落處的閘極多晶矽下面形成閘極氧化層1 2 1造成的三度空間效懕就可消除。所Μ在溝槽角落最常見 的提早崩潰問題得以因應用開窗口使多晶矽層120姐態 不覆蓋角落之新穎结構而解決。而傳統的在角落處常有的 脆弱點之缺憾也完全消除了。 第四Α圖為本發明之實施例DΜ 0 S 100>的俯 視圖，其中除了多晶矽指在终端區的組態不同之外，DM 0S 100'和上述的DMOS 100完全相同。多 晶矽指和「终點跑道j 1 30相連K取代DM0S 10 0中複數偁的终端點。终點跑道為和多晶矽溝1 20 <垂 直的溝權由核心單元區1 0 5 z延伸而來。類似與第三圓 所示，接觸窗口 140 —是開在終點跑道1 30 -之上。 第四B圖是DM0S電晶髖1 00 —沿B-B *線的截面 圖，和第三B画所示相同，多晶矽1 20 -在满榷上终點 跑道1 30 >上的窗口逋被除去，因之提早崩潰的問題亦 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） ---------一'装— (請先鬩讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印聚 Μ Β7 五、發明説明（） 得Μ解決。 第五圖及第六豳為本發明中兩個不同的DMOS元件 200和250的俯視圈。其核心單元區205與255 分別食有單元210和260並含源極接觸點215和2 65，和第三圖及第四圖中所示相同。多晶矽閘極220 和270是形成在溝槽中延伸到终端區Μ利對外接線。元 件200和250更分別含有一特寬的終端閘極跑道23 0和280連接到延伸到終端區的多晶矽指，且和多晶矽 指垂直Κ便保持連接。此特寬跑道230和280較多晶 矽指的寬度約1.0 wm大約更寬兩到三倍*即2.0〜4.Οϋ m，在特寬终端跑道230和280上方置一接觸光軍來 開窗口Μ便做閛掻接觸點對外連接。在第五圖中接觸窗口 235成橢圓形，而在第六圖中則為複數個p方形窗口· 設計者可Κ任選一拓樸。特寬的终端跑道2 3 0和2 8 0 有下列優點：①因為多晶矽閘極220不必覆蓋溝榷邊緣 和角辖，閘極氧化層的可靠度得Μ改良。在實施例中满榷 上的多晶矽被完全去除。因之，具有此新穎組態的DMO S電晶顦就不會有在溝槽的邊緣和角落有二度空間和三度 空間的不良效應，而且也完全除去在邊緣和角落可能造成 提早崩潰的脆弱點。②由於使用特寬的终端跑道230和 2 8 0可Μ免去用多晶矽光罩，因之可Μ更節省生產成本 。因為在此新穎的電晶體结構中·閘極接觸點可Μ直接在 特寛的終端跑道230和280形成，就不需要在溝槽之 上形成多晶砂層。 本紙張尺度適用中國國家抒準（CNS ) A4規格（210X297公釐） I —^^1 —^1 ^^^1 I —II I 1.~'- .. - I— I In—----- (請先閱讀背面之注意事項再填寫本筲) 經濟部中央標隼局貝工消费合作社印聚 308735 五、發明説明（） 第七圖為DMO S電晶體3 0 0的截面圈。此電晶體 形成在一n +基體305和一 η晶膜曆3 1 0之上，在電 晶體300的核心單元中有複數個單元，每單元有一 Ρη接 面區，其中在一深的Ρ體區3 2 0上形成有η +的源搔區 3 1 5。此DMOS更含有一閘極325，是由在晶膜層 310上的溝槽中沉積一多晶矽靨而形成的。從源極區3 15經過卩趙中沿閘極32 5的通道（(^811^1)並延伸到 Ν +基體305的汲極處構成一電流通路。在終端區，有 一特寬的终端跑道340和閘極325可通電，此跑道是 由在特寬（約2.0至3.0//m)的溝檐中沉積多晶矽而形成 的。在這所有活性區（active are,a)之上更形成一 P S G 或BP SG的絕緣層345，然後在核心單元區加上一接 觸光罩，Μ便在源極區3 1 5和P +區335上開窗口來 形成源極接觸點350。在終端區特寬的終端跑道340 之上也開了窗口以利形成閘極接觸點360。此DMOS 電晶體300的截面圖很清楚地願示出在满槽邊緣和角落 上都巳免除了氧化層。閘極接觸點3 6 0是直接在特寬的 終端跑道340之上Μ確保有良好和安全的接觸。用特寬 的終端跑道埋有Κ下其他優點•如用一普通寬度（約1w m)的跑道，由於受到在PSG或BPSG層345上Μ 蝕刻開窗口的處理上的限制，在Μ蝕刻開窗口時需要格外 的謹慎。當蝕刻不夠謹慎時往往會往横向延伸Μ致穿透到 Ρ體而造成短路，當把終端跑道340加得特寬時不但使 閛極的接觸良好，同時也可Κ避免造成短路，更況且因使 -10 - 本紙張尺度適用中國國家樣準（CNS ) Α4規格（2丨0X297公釐） 5 (請先閲讀背面之注意事項再填寫本頁)A7 A7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 1 'Description of the invention () The three-dimensional spatial effect of the overlap of the oxide layer and the corner of the trench can be removed by M. The difficulties caused by the fragile stickiness can be solved. Another object of the present invention is to provide an improved trench DM OS structure and process, wherein the second improved structure is to form a terminal gate contacting the runway and opening the gate window in it, so it can solve the problem of collapse at the vulnerable point difficult. Another object of the present invention is to provide an improved trench DM OS structure and process * wherein the third improved structure is to form an extra-wide terminal gate runway and open the gate contact on the extra-wide run The window can be used for the contact adhesion of the gate. Because of this, the necessity of lifting the gate polysilicon above the trench can be eliminated, and the difficulty of premature collapse at the weak point and poor gate contact can be solved. Another object of the present invention is to provide an improved full-broadcast DMOS structure and process. Among them, a simplified process, that is, K implanting a very wide gate raceway M is used to reduce the number of masks required in the process and reduce cost. In order to make your examination committee understand the purpose, special features and effects of the present invention, hereby is a detailed description of the present invention by the following specific examples and the accompanying indications: A brief description of the illustration: First The plaque is the cross-sectional view of the general DMOS in the conventional technology; the second picture is the cross-sectional garden of the various structures near the terminal area of the DMOS in the conventional technology, in which the junction of the polysilicon gate forms a weak point that is easy to collapse; The third Α and fourth Α_ show that the improved DMO S in the present invention is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297) in the paper size of the terminal (please read the precautions on the back and fill in this page) ·, 1Τ The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printed A 7 B7 i. Description of the structure near the area (). The top view of the structure near the area. Since the gate window was opened, the gate oxide layer covering the corner of the ditch eaves was eliminated. As a result, the reliability of the gate oxide layer has been improved; Figures 3B and 4B are the relative cross-sections of the third A circle and the fourth A-Kiao, respectively; the fifth and sixth pictures show the improved DMOS structure in The top view near the terminal area, its A very wide gate runway M is formed in the terminal area for placing the gate contact point to eliminate the covering part of the gate groove full edge and corner of the gate oxide layer, thus improving the reliability of the gate oxide layer; seventh The figure is the cross-section of the improved DMOS device in the present invention, in which the problem of chipping caused by the weak point is solved; and, the eighth A_ to the eighth diagrams show the production of DMO S in the third to seventh diagrams. The steps of the component. First of all, please refer to the third graph A which is a top view of the DM OS transistor 100 according to the first embodiment of the present invention. The transistor 100 contains a core unit region 105, which includes a plurality of units 1 10, each unit has an active contact 115 and a polysilicon gate 120 formed in the trench. This gate is shaped like a "polysilicon finger" extending from the core area 105 to the terminal area 125. In this terminal area, a plurality of gate windows are opened, which are formed by removing the polysilicon drawer from the window with a polysilicon mask specially configured to add K. The third picture B is a cross-section plaque along A-A > medium. The DMOS transistor 100 is formed on the surface of the crystal shield 104 formed on the base 102. After formation, a layer of polysilicon layer 1 2.0 was deposited on top of it, and there was a gate oxide layer 1 2 1 between the wall and the crystal film 1 04 for insulation. After that, use a polysilicon mask sheet to use the Chinese National Standard (CNS) 84 specifications (210X297 mm) (please read the precautions on the back before filling this page). The consumer cooperative printed 308735 A7 B7 i. Description of the invention () to remove the polysilicon on the trench 105 of the core unit part. A plurality of blind windows are also opened on the photomask at the terminal area 125 near the end point 130 to remove the polysilicon M to form a window 140. Transistor »1 00 also contains a PSG or BPSB layer 122 formed on the polysilicon layer 120 and the window 140, and then use the light source to form the source contact point 1 24 and the gate contact point 1 26, in which the gate Contact Skull 1 26 is in close contact with Terminal Zone 1 2 5 and Gate Runway 128. Since the polysilicon window 140 is opened near the end point 130, the polysilicon 120 will not be raised above the ditch right near the end point. Therefore, the three-dimensional spatial effect caused by the formation of the gate oxide layer 1 2 1 under the gate polysilicon at the corner of the trench near the end point can be eliminated. Therefore, the most common premature collapse problem in the corners of the trenches can be solved by applying a novel structure in which the opening of the polysilicon layer 120 does not cover the corners. And the traditional shortcomings often found in corners are completely eliminated. The fourth Α-diagram is a top view of an embodiment of the present invention DM 0 S 100>, except that the configuration of the polysilicon fingers in the terminal area is different, the DM OS 100 'is completely the same as the DMOS 100 described above. The polysilicon finger is connected to the "final runway j 1 30 and K replaces the terminal point of the complex number in DM0S 10 0. The final runway is a vertical trench right extending from the polysilicon trench 1 20 < 10 5 z from the core unit area. Similar to that shown in the third circle, the contact window 140 is opened above the finish runway 1 30. The fourth image B is a cross-sectional view along the BB * line of the DMOS electronic crystal hip 100, and the third image B shows The same, polysilicon 1 20-the window on the final runway 1 30 > was removed, and the problem of premature collapse is also applicable to this paper standard. China National Standard (CNS) A4 specification (210X297 mm)- -------- 一 '装 — (please read the precautions on the back and fill in this page first) Order the Central Standardization Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperatives to print and print Μ Β7 V. Description of invention () Get solved by Μ. The fifth and sixth figures are top-down circles of two different DMOS devices 200 and 250 in the present invention. The core cell regions 205 and 255 respectively contain cells 210 and 260 and contain source contact points 215 and 265, and The third and fourth figures are the same. The polysilicon gates 220 and 270 are formed in the trench and extend to the terminal area. External wiring. Components 200 and 250 also contain a very wide terminal gate runway 230 and 280 connected to the polysilicon fingers extending to the terminal area, and remain connected to the polysilicon fingers perpendicular to the K. This extra wide runway 230 and 280 The width of the polysilicon finger is about 1.0 wm, which is about two to three times wider *, that is, 2.0 ~ 4.0 mm, a contact light army is placed above the ultra-wide terminal runways 230 and 280 to open the window M, and then connect the contact points to the outside. In the fifth picture, the contact window 235 is elliptical, and in the sixth picture, there are a plurality of p-square windows. The designer can choose any topology. The extra wide terminal runways 2 3 0 and 2 8 0 have the following Advantages: ① Because the polysilicon gate 220 does not need to cover the edge and corner of the trench, the reliability of the gate oxide layer is improved by M. In the embodiment, the polysilicon is completely removed. Therefore, with this novel configuration DMO S transistors will not have the undesirable effect of having two-dimensional space and three-dimensional space at the edges and corners of the groove, and also completely remove the vulnerable points that may cause early collapse at the edges and corners. ② Due to the use of extra wide Terminal runways 230 and 280 can be used free of charge Crystalline silicon photomask, so it can save more production cost. In this novel transistor structure, the gate contact can be formed directly on the terminal runways 230 and 280 of the special belt, so there is no need to be above the trench A polycrystalline sand layer is formed. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) I — ^^ 1 — ^ 1 ^^^ 1 I —II I 1. ~ '-..-I— I In —----- (please read the precautions on the back before filling in this note) The Central Standard Falcon Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative Printed and Collected 308735 V. Description of the invention () The seventh picture shows the DMO S transistor 3 0 0 Section circle. The transistor is formed on an n + substrate 305 and an n-crystal film 3 1 0, there are a plurality of cells in the core unit of the transistor 300, each unit has a pn junction area, in which a deep p-body On the region 3 2 0, a source scratch region 3 1 5 of η + is formed. The DMOS further includes a gate 325, which is formed by depositing a polysilicon in the trench on the crystalline film layer 310. From the source area 3 15 through the channel ((^ 811 ^ 1) along the gate 325 of Zhao Zhong and extending to the drain of the N + substrate 305 to form a current path. In the terminal area, there is a very wide terminal runway 340 and The gate 325 can be energized. This runway is formed by depositing polysilicon in a very wide (approximately 2.0 to 3.0 // m) eaves. A PSG or more is formed above all active areas (a) BP SG insulation layer 345, and then add a contact mask in the core unit area, M will open a window in the source area 315 and P + area 335 to form the source contact 350. In the terminal area is very wide A window is also opened above the terminal runway 340 to facilitate the formation of the gate contact 360. The cross-sectional view of this DMOS transistor 300 is clearly intended to show that the oxide layer is eliminated on the edges and corners of the full trench. Gate contact 3 6 0 is directly above the extra-wide terminal runway 340 to ensure good and safe contact. Using the extra-wide terminal runway to bury other advantages under K • If you use a normal width (about 1w m) runway, because Restricted by the processing of the M etching opening on the PSG or BPSG layer 345, a grid is required during the M etching opening When the etching is not careful enough, it tends to extend laterally to penetrate the P body and cause a short circuit. When the terminal runway 340 is widened, not only does the contact of the prosthesis pole be good, but also can avoid short circuit , Moreover because of -10-This paper scale is applicable to China National Standards (CNS) Α4 specification (2 丨 0X297mm) 5 (Please read the precautions on the back before filling this page)
經濟部中央標準局員工消费合作社印策 A7 ___B7 五、發明説明（） 用特寬終端跑道上的窗口可Μ免去光罩，堪可Μ更節省成 本。 第八Α圔至第八Η圄顯示出DMO S功率元件4 0 0 之製程。第八Α圔顯示首先在一η +基體405之上生長 一電阻率為0.1至1.0 ohn-CBi之η晶膜層4 1 Ο。基趙4 0 5之電姐率為0.001至0.007 oh-c·。晶膜層4 1 0的 厚度和II阻率係依通路電阻和崩潰電壓的要求而定。在一 實施例中*其厚度約_3至20 wm · —光電阻被用來做 溝播光罩，而後用乾性不専向蝕刻處理來形成1.0至2.0« m寬和1.0至2.Otf m深的溝播。之後施Μ —乾性或濕性的 「犧牲打」氧化處理在900至1 1001C溫度下來形成 厚約300 — 2000Α的氧化層•接著再施Μ—「释牲 打」氧化蝕刻處理。之後在800至1 ιοου溫度下， 來形成一厚約200至1 000Α之氧化蘑，再沉積一厚 約1.5至3.0«m的多晶矽層42 0。在此沉積層上再施Κ 平面蝕刻至約0.2至0.5«m ·皤後在950¾溫度下KP OCL3摻雜處理K使多晶矽曆420的平面電阻為20 —40〇ha/cm2 。第八B圖顯示Μ乾性蝕刻把多晶矽層4 20表面除去而保留終點直到满槽Μ上的多晶矽層都除去 為止。 第八C圖顯示應用Ρ體光罩425及30-1 00 Kev 離子通量密度為2x 1 013至2X 1 014/cb2的硼離子 的硼離子束做P體植入。光阻4 2 5隨後即被除去。其後 如第八D圖所示，在1 COO — 1 200¾溫度下進行十 -11 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） n -i I I -HI - - I-I- ·: 士民-I— I - I— n n 丁 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央梯準局員工消费合作杜印製 A 7 B7 i、發明説明（）Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ___B7 V. Description of the invention () The window on the runway of the extra-wide terminal can be used to eliminate the photomask, which can save costs. The eighth to eighth ohms show the manufacturing process of the DMOS power device 400. The eighth A shows that an η crystal film layer 4 1 Ο having a resistivity of 0.1 to 1.0 ohn-CBi is grown on an η + substrate 405 first. The rate of base sister 4 0 5 is 0.001 to 0.007 oh-c ·. The thickness and II resistivity of the crystal film layer 4 1 0 depend on the requirements of the path resistance and breakdown voltage. In one embodiment, the thickness is about _3 to 20 wm.-The photoresist is used as a trench mask, and then dry etching process is used to form 1.0 to 2.0 m wide and 1.0 to 2.0 m. Deep trench sowing. Then apply M-dry or wet "sacrificial" oxidation treatment at 900 to 1 1001C to form an oxide layer with a thickness of about 300-2000A. Then apply M- "Release" oxidation etching process. Then, at a temperature of 800 to 1 ιοου, an oxidizing mushroom with a thickness of about 200 to 1 000 A is formed, and then a polysilicon layer 420 with a thickness of about 1.5 to 3.0 mm is deposited. On this deposited layer, K-plane etching is performed to about 0.2 to 0.5 mm. After the KP OCL3 doping treatment is performed at a temperature of 950¾, the polysilicon calendar 420 has a plane resistance of 20-40 ha / cm2. Figure 8B shows that the dry etching of M removes the surface of the polysilicon layer 4 20 and retains the end point until the polysilicon layer on the full trench M is removed. Figure 8C shows a P-body implantation using a P-body mask 425 and a boron ion beam with a 30-1000 Kev ion flux density of 2x 1 013 to 2X 1 014 / cb2. The photoresist 4 2 5 is then removed. Afterwards, as shown in the eighth D figure, at a temperature of 1 COO-1 200¾ 10-11-This paper scale applies the Chinese National Standard (CNS) A4 specifications (210X297 mm) n -i II -HI--II- ·: Shimin-I-I-I-nn Ding (please read the precautions on the back and then fill in this page) Employee's consumption cooperation of the Central Escalation Bureau of the Ministry of Economic Affairs, A 7 B7 i, invention description ()
分鐘至三小時的擴散處理Μ把P®區430的深度加到 1.0 - 2.Owm。然後加上一 η +阻隔光罩4 3 5來植入η + Μ形成η +區440。此植入是用40 — 400 Kev，通 量密度為5X 1 015至1 X 1 0ie/cB2的砷或瞵離子束 完成，然後再把光阻（即n+胆隔光罩435)除去。第 八E圈顯示在900 — 1 000*0溫度下十分鐘至兩小時 而把N +源極區440以擴散達到0.2至l.Owm深度，然 後在表面上形成一低壓化學汽沉積（LPCVD)氮化雇4 38，其後再沉稹PSG或BPSG來形成約5000-1 5000A厚的一靥445，這一層PSG或BPSG 4 4 5再在90 0 _ 9 5 0 TC溫度情況下進行3 0分鐘至 一小時加以緊密化•然後加上一接觸光罩做乾性蝕刻來界 定接觸窗口Μ供形成源極和閘極接觸點。接著施以20— 5 0 Kev，1 X 1 0 15 至 1 X 1 0 1B / cb2 的硼離子全面 植入，Ρ+區在900 — 9501的氧化或惰性氣體中即 可活化。第八F圖中顯示用金屬沉積處理來形成一金靨層 ，在其上加Μ金饜光單來形成源極接觸點（S) 450、閛 極接觸（G)點460、場板（FP)4 7 0和通道站（channel stop，CS) 480,而完成了最終的DMOS電晶體40 0。第八F圈至第八Η園顯示出特霣閘極跑道4 8 5之形 成。第八F圖顯示浮動場環（FR)區488和一通道站 (CS)4 8 0之形成。在第八G圖中因為有不同的崩潰電懕 的要求，因此不需要有浮動場環（FR) 488。第八Η 圓顯示出因為有另外不同的崩潰電屋的要求而使用一系列 -12 - 本紙張尺度適用中國國家標隼（CNS )八和以|· ( 210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 装· 訂 A7 B7 308735 五、發明説明（） 的浮動環和通道（CS)，所κ不需要有場板（FP)。由於流動 離子完全被LPCVD氮化層所阻隔而不能進入電晶體內 ，所Μ也不需要有鈍化層。因為在DMOS 400的製 程中可Μ免除墊襯（pad)光罩，和一般DMOS製程中必 需用墊襯光罩來形成鈍化層相較，又更可Μ節省費用。 雎然本發明Μ上述之實施例敘逑•但Μ上所揭露及說 明之具體描述，並不作為解釋本發明播利範圃之侷限。一 旦関謓本發明所揭露之內容•對具有一般技藝人士，各樣 之變化、修改即已明白。因之，下列專利輯圃要求項目· 只要變化及修改不出本發明的精意及內容•都應被納入包 含在本發明的權利範鬮內。 (請先閱讀背面之注意事項再填寫本頁) 装· 訂 經濟部中央標一-Τ'局負工消費合作社印製 3 11 本紙張尺度適用中國國家橾準（CNS ) Α4規格（2丨0'乂297公釐）The diffusion process from minute to three hours M increases the depth of the P® zone 430 to 1.0-2.0 Wm. Then an η + blocking mask 4 3 5 is added to implant η + M to form η + region 440. This implantation is done with 40-400 Kev, flux density of 5X 1 015 to 1 X 1 0ie / cB2 arsenic or strontium ion beam, and then the photoresist (ie, n + gallbladder shield 435) is removed. The eighth circle E shows that the N + source region 440 is diffused to a depth of 0.2 to 1.0 Wm at a temperature of 900-1 000 * 0 for ten minutes to two hours, and then a low pressure chemical vapor deposition (LPCVD) is formed on the surface Nitrogen nitride 4 38, and then Shen Zhen PSG or BPSG to form a thick 445 about 5000-1 5000A thick, this layer of PSG or BPSG 4 4 5 and then at 90 0 _ 9 5 0 TC temperature 3 0 From minute to hour to be compacted • A contact mask is then added for dry etching to define the contact window M for forming source and gate contacts. Then 20-20 Kev, 1 X 1 0 15 to 1 X 1 0 1B / cb2 of boron ions are implanted, and the P + region can be activated in the oxidation or inert gas of 900-9501. Figure 8F shows a metal deposition process to form a gold layer, and then add M gold coating on it to form the source contact point (S) 450, the gate electrode contact (G) point 460, the field plate (FP) 4 70 and channel stop (channel stop, CS) 480, and completed the final DMOS transistor 40. From the eighth circle F to the eighth garden, the formation of the special gate runway 4 8 5 is shown. Figure 8F shows the formation of the floating field ring (FR) area 488 and a channel station (CS) 480. In the eighth G figure, there are different requirements for crashing, so there is no need for a floating field ring (FR) 488. The eighth circle shows the use of a series of -12 because of the different requirements of the collapsed electric house-this paper scale is applicable to the Chinese national standard falcon (CNS) Baheyi | (210X297mm) (please read the back side first (Notes and then fill out this page) Binding · Order A7 B7 308735 5. The floating ring and channel (CS) of the invention description (), so the field plate (FP) is not required. Since the mobile ions are completely blocked by the LPCVD nitride layer and cannot enter the transistor, no passivation layer is required. Because the pad mask can be eliminated in the DMOS 400 process, compared with the general DMOS process, a pad mask is necessary to form a passivation layer, which can save costs. Although the above-mentioned embodiments of the present invention are described in detail, the detailed descriptions disclosed and explained on the above are not intended to explain the limitations of the present invention. Once the content of the present invention is disclosed to the person of ordinary skill, various changes and modifications will be understood. Therefore, the following items required by the patent series: As long as the essence and content of the present invention cannot be changed or modified, they should be included in the scope of rights of the present invention. (Please read the precautions on the back before filling out this page) Binding · Order Printed by the Ministry of Economic Affairs Central Standard-T 'Bureau Negative Work Consumer Cooperative 3 11 This paper size is applicable to China National Standard (CNS) Α4 specifications (2 丨 0 'Yi 297 mm)