CN101295687B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101295687B
CN101295687B CN2008100935954A CN200810093595A CN101295687B CN 101295687 B CN101295687 B CN 101295687B CN 2008100935954 A CN2008100935954 A CN 2008100935954A CN 200810093595 A CN200810093595 A CN 200810093595A CN 101295687 B CN101295687 B CN 101295687B
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China
Prior art keywords
lead
pad
semiconductor device
manufacturing
gate
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Expired - Fee Related
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CN2008100935954A
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Chinese (zh)
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CN101295687A (zh
Inventor
武藤邦治
波多俊幸
佐藤仁久
冈浩伟
池田靖
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NEC Corp
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Renesas Technology Corp
Renesas Electronics Corp
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    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
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    • H10W72/853—On the same surface
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/874—On different surfaces
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
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    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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