CN102163562B - 一种功率半导体管芯的安装方法和同步降压转换器 - Google Patents

一种功率半导体管芯的安装方法和同步降压转换器 Download PDF

Info

Publication number
CN102163562B
CN102163562B CN201110066085A CN201110066085A CN102163562B CN 102163562 B CN102163562 B CN 102163562B CN 201110066085 A CN201110066085 A CN 201110066085A CN 201110066085 A CN201110066085 A CN 201110066085A CN 102163562 B CN102163562 B CN 102163562B
Authority
CN
China
Prior art keywords
power semiconductor
semiconductor die
substrate
grid
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110066085A
Other languages
English (en)
Other versions
CN102163562A (zh
Inventor
段志华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Juxin Technology Co Ltd
Original Assignee
Juxin Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Juxin Technology Co Ltd filed Critical Juxin Technology Co Ltd
Priority to CN201110066085A priority Critical patent/CN102163562B/zh
Publication of CN102163562A publication Critical patent/CN102163562A/zh
Application granted granted Critical
Publication of CN102163562B publication Critical patent/CN102163562B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明实施例公开了一种功率半导体管芯的安装方法和同步降压转换器,在本发明实施例中,由于安装第一功率半导体管芯和第二功率半导体管芯与基板的接触面不同,第一功率半导体管芯的源极和第二功率半导体管芯的漏极处于同一层表面上,故可以只采用一个导电夹片即可完成连接,简化了工艺结构和制作过程,降低了制造成本,另外由于采用的是一个导电夹片直接连接处于同一层表面的第一功率半导体管芯的源极和第二功率半导体管芯的漏极,故不需要较大的空间,有利于设备的小型化。

Description

一种功率半导体管芯的安装方法和同步降压转换器
技术领域
本发明涉及电子技术领域,尤其涉及一种功率半导体管芯的安装方法和同步降压转换器。
背景技术
同步降压转换器用于电压调整,典型的同步降压转换器包含功率控制器电路芯片,高侧功率场效应管和低侧功率场效应管,同步降压转换器经常用半桥电路来实现,如图1所示,为典型的简化半桥电路图,其中,101为同步降压转换器,102为高侧功率场效应管,103为低侧功率场效应管,104为功率控制器电路芯片,105为同步降压转换器的外接电感,高侧功率场效应管的源极S与低侧功率场效应管的漏极D相连,功率控制器电路可控制高侧功率场效应管的栅极G和低侧功率场效应管的栅极G。
在对功率场效应管的安装过程中,常用的现有技术一是:两个功率场效应管均采用传统的漏极朝下,源极和栅极朝上进行安装,如图2所示,201为高侧功率场效应管,202为低侧功率场效应管,203为功率控制器电路芯片,204和205分别为两个导电夹片。但是,在实现本发明的过程中,发明人发现该现有技术至少存在以下问题:需要两个导电夹片,而导致增加了制造成本;连接高侧功率场效应管的源极和低侧功率场效应管的漏极的导电夹片需要搭接到两个功率场效应管的公共节点,需要较大的空间,不利于整个设备的小型化。
在对功率场效应管的安装过程中,常用的现有技术二是:将高侧功率场效应管和低侧功率场效应管分别贴装在印制电路板(PCB,Printed CircuitBoard)结构基板和金属基板上,制成单独的子封装,再与功率控制器电路芯片一起贴装到引线框架结构上。如图3所示,低侧功率场效应管301的源极和栅极采用凸块处理,漏极贴装到带凸块的金属基板上,即将低侧功率场效应管的源极、栅极、漏极都转到同一平面上,且金属基板背面为漏极,作为公共节点;高侧功率场效应管302采用一个PCB结构基板,将源极、栅极转接到PCB的焊球结构上,且焊球的高度与漏极高度相同,PCB的另外一侧为源极,用作公共节点;将低侧功率场效应管和高侧功率场效应管的子封装和功率控制器电路芯片贴装在引线框架结构上,使用金线键合工艺将功率控制器电路芯片303与引线框架结构连接,再用一个阶梯结构的导电夹片把两个功率场效应管的公共节点连接起来。但是,在实现本发明的过程中,发明人发现该现有技术至少存在以下问题:由于高侧功率场效应管和低侧功率场效应管需要分别封装且需要将功率场效应管的三个极转接到一个面上,导致封装结构及工艺复杂,流程较多,使用材料较多,增加了制造成本。
发明内容
本发明实施例提供了一种功率半导体管芯的安装方法和同步降压转换器,用于简化工艺结构和制作过程,降低制造成本,实现设备的小型化。
本发明实施例提供的功率半导体管芯的安装方法,包括:
将第一功率半导体管芯安装到基板上,其中,第一功率半导体管芯的上表面为源极和栅极,第一功率半导体管芯的下表面为漏极,漏极与基板的第一芯片焊盘相连接;
将第二功率半导体管芯安装到基板上,其中,第二功率半导体管芯的下表面为源极和栅极,源极与基板的第二芯片焊盘相连接,栅极与基板的第三芯片焊盘相连接,第二功率半导体管芯的上表面为漏极;
采用导电夹片连接第一功率半导体管芯的源极和第二功率半导体管芯的漏极;
将功率控制器电路芯片安装到基板上,采用键合线分别将第一功率半导体管芯的栅极和第二功率半导体管芯的栅极连接到功率控制器电路芯片。
本发明实施例提供的一种同步降压转换器,包括:第一功率半导体管芯、第二功率半导体管芯和功率控制器电路芯片,其中,
第一功率半导体管芯的上表面为源极和栅极,第一功率半导体管芯的下表面为漏极,漏极与基板的第一芯片焊盘相连接;
第二功率半导体管芯的下表面为源极和栅极,源极与基板的第二芯片焊盘相连接,栅极与基板的第三芯片焊盘相连接,第二功率半导体管芯的上表面为漏极;
第一功率半导体管芯的源极和第二功率半导体管芯的漏极采用导电夹片连接;
功率控制器电路芯片通过键合线分别连接第一功率半导体管芯的栅极和第二功率半导体管芯的栅极。
从以上技术方案可以看出,本发明实施例具有以下优点:
在本发明实施例中,由于安装第一功率半导体管芯和第二功率半导体管芯与基板的接触面不同,第一功率半导体管芯的源极和第二功率半导体管芯的漏极处于同一层表面上,故可以只采用一个导电夹片即可完成连接,简化了工艺结构和制作过程,降低了制造成本,另外由于采用的是一个导电夹片直接连接处于同一层表面的第一功率半导体管芯的源极和第二功率半导体管芯的漏极,故不需要较大的空间,有利于设备的小型化。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域的技术人员来讲,还可以根据这些附图获得其他的附图。
图1是典型的简化半桥电路图;
图2是现有技术一中的功率场效应管的安装示意图;
图3是现有技术二中的功率场效应管的安装示意图;
图4是本发明实施例提供的一种功率半导体管芯的安装方法示意图;
图5是本发明实施例提供的引线框架结构的示意图;
图6-a是本发明实施例提供的一种集成封装模块的切面视图;
图6-b是本发明实施例提供的另一种集成封装模块的切面视图;
图6-c是本发明实施例提供的另一种集成封装模块的切面视图;
图7-a是本发明实施例提供的一种同步降压转换器的示意图;
图7-b是本发明实施例提供的另一种同步降压转换器的示意图;
图8是本发明实施例提供的一种功率半导体管芯的安装过程示意图;
图9是本发明实施例提供的另一种功率半导体管芯的安装过程示意图。
具体实施方式
本发明实施例提供了一种功率半导体管芯的安装方法和同步降压转换器,用于简化工艺结构和制作过程,降低制造成本,实现设备的小型化。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,下面所描述的实施例仅仅是本发明一部分实施例,而非全部实施例。基于本发明中的实施例,本领域的技术人员所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供的一种功率半导体管芯的安装方法,参见图4,具体步骤包括:
401、将第一功率半导体管芯安装到基板上,其中,第一功率半导体管芯的上表面为源极和栅极,第一功率半导体管芯的下表面为漏极,漏极与基板的第一芯片焊盘相连接;
在实际应用中,功率半导体管芯可以包含任何类别的垂直半导体器件,具体可以为功率场效应管,功率半导体管芯具有三个区,分别是源极S、栅极G和漏极D,其中,源极S和栅极G位于功率半导体管芯的一面上,漏极D位于功率半导体管芯的另一面上,本发明实施例中为了简化工艺结构和制作过程,不需要像现有技术二中将三个区转接到一个面上,而使用的是普通的功率半导体管芯结构。
本步骤中,将第一功率半导体管芯安装到基板上,也就是将第一功率半导体管芯的下表面(漏极D)与基板的第一芯片焊盘相连接,具体在实际应用中可以采用焊球或焊柱等焊料,或者导电胶实现,此处不作限定。
需要说明的是,基板可以是引线框架结构,引线框架结构是指从引线框获得的结构,引线框架可以是通过冲压工艺得到,也可以是采用蚀刻导电板得到的预定图形或结合冲压工艺和蚀刻工艺而得到,本实施例中的基板可以是连续或者不连续的金属结构。引线框架最初是以通过系杆连接在一起的引线框架陈列中的许多单元中的一个,在制造半导体管芯封装的工艺期间,引线框架陈列可以被切割或者冲切使各个封装相互分离,此外,引线框架结构可以具有多个可形成芯片焊盘(DAP,Die Attach Pad),引线可以与DAP的表面共面或者不共面,引线框结构可以为任何适当的材料,可以具有任何适当的形式和厚度,还包含引线框架上的金属镀层如银镀层,镍金镀层,镍钯金镀层等,引线框架材料可以包括铜,铝及其合金,铁镍合金等。如图5所示,为引线框架结构的示意图,501表示引线框架结构,502表示第一芯片焊盘,503表示第二芯片焊盘,504表示第三芯片焊盘,505表示将功率控制器电路芯片安装到基板上的芯片焊盘,封装输入输出的引脚用缩写表示,如SW为开关节点,S1为第一功率半导体管芯的源极,S2为第二功率半导体管芯的源极,G1为第一功率半导体管芯的栅极,G2为第二功率半导体管芯的栅极,C为功率控制器电路芯片的引脚,D1为第一功率半导体管芯的漏极。
402、将第二功率半导体管芯安装到基板上,其中,第二功率半导体管芯的下表面为源极和栅极,源极与基板的第二芯片焊盘相连接,栅极与基板的第三芯片焊盘相连接,第二功率半导体管芯的上表面为漏极;
在实际应用中,第二功率半导体管芯安装到基板上的方向和第一半导体管芯安装到基板上的方向相反,将第二功率半导体管芯下表面的源极S与基板的第二芯片焊盘相连,将第二功率半导体管芯下面的栅极G与基板的第三芯片焊盘相连,具体可以采用焊球或焊柱等焊料,或者导电胶实现。
403、采用导电夹片连接第一功率半导体管芯的源极和第二功率半导体管芯的漏极;
在本发明实施例中,由步骤401和402可知,第一功率半导体管芯的源极和第二功率半导体管芯的漏极均处于同一层表面上,直接使用导电夹片连接即可,导电夹片可以采取蚀刻或者冲压的方式得到,导电夹片的材料可以是铜,铝或其合金等。
404、将功率控制器电路芯片安装到基板上,采用键合线分别将第一功率半导体管芯的栅极和第二功率半导体管芯的栅极连接到功率控制器电路芯片。
在实际应用中,可以使用导电胶将功率控制器电路芯片安装到基板的芯片焊盘上,然后,采用键合线分别将第一功率半导体管芯的栅极G和第二功率半导体管芯的栅极G连接到功率控制器电路芯片。
需要说明的是,在本发明实施例中,步骤401和步骤402之间没有先后顺序之分,可以先完成步骤401再进行步骤402,也可以先完成402再进行步骤401,另外,步骤403和步骤404之间也没有先后顺序之分,可以先完成步骤403再进行步骤404,也可以先完成404再进行步骤403,此处不作限定。
需要说明的是,在本发明实施例中,完成上述安装方法之后,还可以进行如下步骤:采用封模材料覆盖基板、第一功率半导体管芯、第二功率半导体管芯和导电夹片;或,采用封模材料覆盖基板、第一功率半导体管芯、第二功率半导体管芯,而将导电夹片的全部表面或预置的部分表面露出封模材料,接下来将分别作出说明。
在本发明实施例中,第一种实现方式采用封模材料覆盖基板、第一功率半导体管芯、第二功率半导体管芯和导电夹片,故使用本发明方法制作出的设备在工作过程中产生的热量能够经过基板传导到PCB铜皮散热。但在实际应用中,第二种实现方式采用封模材料也可以覆盖导电夹片的全部表面和预置的部分表面,但是具体需要覆盖的部分表面的大小由具体应用环境决定,由于按照本方式除了由基板传导散热外,还可以通过导电夹片没有被封模材料覆盖的表面散热,可以达到双通道散热传导的效果,如图6-a、图6-b和图6-c所示,分别为集成封装模块的切面视图,其中,图6-a中封模材料601覆盖了导电夹片604,图6-b中封模材料602没有覆盖导电夹片605,图6-c中封模材料603覆盖了导电夹片606的部分表面。
封模材料具体可以采用多功能交联环氧树脂复合材料等,封模材料以固定料饼形态,在高温下软化成固液共存的胶体状态,通过转移注入模具与放置在模具中的基板结合成型,并发生交联反应后固化成型。
按照本发明实施例中步骤401至404的安装方法,然后再采用封模材料进行封装可得到同步降压转换器,如图7-a和图7-b所示,701表示第一功率半导体管芯,702表示第二功率半导体管芯,703表示导电夹片,704表示功率控制电路芯片,705表示基板,706表示第二功率半导体管芯下表面的焊球。图7-a和图7-b都是按照本发明实施例方法安装半导体管芯后得到的同步降压转换器示意图,区别在于在图7-a中使用了焊球将第二功率半导体管芯的下表面的源极和栅极安装在了基板上,图7-a的切面视图可参见图6-c,而图7-b中没有使用焊球,直接将第二功率半导体管芯贴装到基板上,图7-b的切面视图可参见图6-a和图6-b。
在本发明实施例中,由于安装第一功率半导体管芯和第二功率半导体管芯与基板的接触面不同,第一功率半导体管芯的源极和第二功率半导体管芯的漏极处于同一层表面上,故可以只采用一个导电夹片即可完成连接,简化了工艺结构和制作过程,降低了制造成本,另外由于采用的是一个导电夹片直接连接处于同一层表面的第一功率半导体管芯的源极和第二功率半导体管芯的漏极,故不需要较大的空间,有利于设备的小型化。
下面将以一实际的应用场景来说明本发明实施例中的功率半导体管芯的安装方法,请参阅图8,采用锡膏焊接功率半导体管芯时,首先制作好基板,然后在基板上采用Dispense工艺点锡膏或者使用钢网印刷锡膏到基板上,然后再贴装两个功率半导体管芯,其中,两个功率半导体管芯安装到基板上的方向相反,保证功率半导体管芯上的焊球与基板的对应位置接好,接着在功率半导体管芯的上表面及基板上的SW引脚用Dispense工艺点上锡膏并贴装好导电夹片,然后清洗焊剂(Flux),Flux清洗完毕后,采用常规的导电胶贴装工艺把功率控制器电路芯片贴装到基板上,并把导电胶固化,进行等离子清洗和使用键合线完成基板与功率控制器电路芯片、两个功率半导体管芯的电性连接,最后采用封模材料对整个基板、两个功率半导体管芯进行塑封,并且将导电夹片的表面露出后切割成单个器件,即得到一个集成封装模块。
下面将以另一实际的应用场景来说明本发明实施例中的功率半导体管芯的安装方法,请参阅图9,采用导电胶粘接功率半导体管芯时,首先制作好基板,然后在基板上采用Dispense工艺点到导电胶或者使用钢网印刷导电胶到基板上,然后再贴装两个功率半导体管芯,其中,两个功率半导体管芯安装到基板上的方向相反,保证功率半导体管芯上的焊球与基板的对应位置接好,接着在功率半导体管芯的上表面及基板上的SW引脚用Dispense工艺点上导电胶并贴装好导电夹片,并把导电胶固化,进行等离子清洗和使用键合线完成基板与功率控制器电路芯片、两个功率半导体管芯的电性连接,最后采用封模材料对整个基板、两个功率半导体管芯进行塑封,并且将导电夹的表面露出后切割成单个器件,即得到一个集成封装模块。
以上实施例介绍了功率半导体管芯的安装方法,下面将介绍使用本发明实施例的功率半导体管芯的安装方法制成的同步降压转换器。
本发明实施例中的同步降压转换器,包括:第一功率半导体管芯、第二功率半导体管芯和功率控制器电路芯片,其中,
第一功率半导体管芯的上表面为源极和栅极,第一功率半导体管芯的下表面为漏极,漏极与基板的第一芯片焊盘相连接;
第二功率半导体管芯安的下表面为源极和栅极,源极与基板的第二芯片焊盘相连接,栅极与基板的第三芯片焊盘相连接,第二功率半导体管芯的上表面为漏极;
第一功率半导体管芯的源极和第二功率半导体管芯的漏极采用导电夹片连接;
功率控制器电路芯片通过键合线分别连接第一功率半导体管芯的栅极和第二功率半导体管芯的栅极。
需要说明的是,本发明实施例中的同步降压转换器还包括:基板、第一功率半导体管芯、第二功率半导体管芯和导电夹片都覆盖有封模材料;或,基板、第一功率半导体管芯、第二功率半导体管芯都覆盖有封模材料,导电夹片的全部表面或预置的部分表面没有覆盖封模材料。
本发明实施例中的同步降压转换器,具体可以为图7-a和图7-b中所示的集成封装模块,第一功率半导体管芯和第二功率半导体管芯在实际应用中可以为功率场效应管。在实际应用中,第一种实现方式采用封模材料覆盖基板、第一功率半导体管芯、第二功率半导体管芯和导电夹片,故使用本发明方法制作出的设备在工作过程中产生的热量能够经过基板传导到PCB铜皮散热。但在实际应用中,第二种实现方式采用封模材料也可以覆盖导电夹片的全部表面和预置的部分表面,但是具体需要覆盖的部分表面的大小由具体应用环境决定,由于按照本方式除了由基板传导散热外,还可以通过导电夹片没有被封模材料覆盖的表面散热,可以达到双通道散热传导的效果,具体可以如图6-a、图6-b和图6-c所示。
在本发明实施例中,同步降压转换器中由于安装第一功率半导体管芯和第二功率半导体管芯与基板的接触面不同,第一功率半导体管芯的源极和第二功率半导体管芯的漏极处于同一层表面上,故可以只采用一个导电夹片即可完成连接,简化了工艺结构和制作过程,降低了制造成本,另外由于采用的是一个导电夹片直接连接处于同一层表面的第一功率半导体管芯的源极和第二功率半导体管芯的漏极,故不需要较大的空间,有利于同步降压转换器的小型化。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成,该程序可以存储于一计算机可读存储介质中,存储介质可以包括:ROM、RAM、磁盘或光盘等。
以上对本发明实施例提供的一种功率半导体管芯的安装方法和同步降压转换器进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。

Claims (10)

1.一种功率半导体管芯的安装方法,其特征在于,包括:
将第一功率半导体管芯安装到基板上,其中,所述第一功率半导体管芯的上表面为源极和栅极,所述第一功率半导体管芯的下表面为漏极,所述漏极与所述基板的第一芯片焊盘相连接;
将第二功率半导体管芯安装到所述基板上,其中,所述第二功率半导体管芯的下表面为源极和栅极,所述源极与所述基板的第二芯片焊盘相连接,所述栅极与所述基板的第三芯片焊盘相连接,所述第二功率半导体管芯的上表面为漏极;
采用导电夹片连接所述第一功率半导体管芯的源极和所述第二功率半导体管芯的漏极,所述第一功率半导体管芯的源极和所述第二功率半导体管芯的漏极处于同一层表面上;
将功率控制器电路芯片安装到所述基板上,采用键合线分别将所述第一功率半导体管芯的栅极和所述第二功率半导体管芯的栅极连接到所述功率控制器电路芯片。
2.根据权利要求1所述的功率半导体管芯的安装方法,其特征在于,所述采用键合线分别将所述第一功率半导体管芯的栅极和所述第二功率半导体管芯的栅极连接到所述功率控制器电路芯片之后包括:
采用封模材料覆盖所述基板、所述第一功率半导体管芯、所述第二功率半导体管芯和所述导电夹片;
或;
采用封模材料覆盖所述基板、所述第一功率半导体管芯、所述第二功率半导体管芯,而将所述导电夹片的全部表面或预置的部分表面露出封模材料。
3.根据权利要求1所述的功率半导体管芯的安装方法,其特征在于,所述第一功率半导体管芯的漏极通过焊球或焊柱或导电胶与所述基板的第一芯片焊盘相连接;
所述第二功率半导体管芯的源极通过焊球或焊柱或导电胶与所述基板的第二芯片焊盘相连接;
所述第二功率半导体管芯的栅极通过焊球或焊柱或导电胶与所述基板的第三芯片焊盘相连接。
4.根据权利要求1所述的功率半导体管芯的安装方法,其特征在于,所述第一功率半导体管芯和所述第二功率半导体管芯为功率场效应管。
5.根据权利要求1所述的功率半导体管芯的安装方法,其特征在于,所述导电夹片是通过蚀刻或者冲压的方式制成。
6.一种同步降压转换器,其特征在于,包括:第一功率半导体管芯、第二功率半导体管芯和功率控制器电路芯片,
所述第一功率半导体管芯的上表面为源极和栅极,所述第一功率半导体管芯的下表面为漏极,所述漏极与基板的第一芯片焊盘相连接;
所述第二功率半导体管芯的下表面为源极和栅极,所述源极与所述基板的第二芯片焊盘相连接,所述栅极与所述基板的第三芯片焊盘相连接,所述第二功率半导体管芯的上表面为漏极;
所述第一功率半导体管芯的源极和所述第二功率半导体管芯的漏极采用导电夹片连接,所述第一功率半导体管芯的源极和所述第二功率半导体管芯的漏极处于同一层表面上;
所述功率控制器电路芯片通过键合线分别连接所述第一功率半导体管芯的栅极和所述第二功率半导体管芯的栅极。
7.根据权利要求6所述的同步降压转换器,其特征在于,所述基板、所述第一功率半导体管芯、所述第二功率半导体管芯和所述导电夹片都覆盖有封模材料;
或,
所述基板、所述第一功率半导体管芯、所述第二功率半导体管芯都覆盖有封模材料,所述导电夹片的全部表面或预置的部分表面没有覆盖封模材料。
8.根据权利要求6所述的同步降压转换器,其特征在于,所述第一功率半导体管芯的漏极通过焊球或焊柱或导电胶与所述基板的第一芯片焊盘相连接;
所述第二功率半导体管芯的源极通过焊球或焊柱或导电胶与所述基板的第二芯片焊盘相连接;
所述第二功率半导体管芯的栅极通过焊球或焊柱或导电胶与所述基板的第三芯片焊盘相连接。
9.根据权利要求6所述的同步降压转换器,其特征在于,所述第一功率半导体管芯和所述第二功率半导体管芯为功率场效应管。
10.根据权利要求6所述的同步降压转换器,其特征在于,所述导电夹片是通过蚀刻或者冲压的方式制成。
CN201110066085A 2011-03-18 2011-03-18 一种功率半导体管芯的安装方法和同步降压转换器 Expired - Fee Related CN102163562B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110066085A CN102163562B (zh) 2011-03-18 2011-03-18 一种功率半导体管芯的安装方法和同步降压转换器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110066085A CN102163562B (zh) 2011-03-18 2011-03-18 一种功率半导体管芯的安装方法和同步降压转换器

Publications (2)

Publication Number Publication Date
CN102163562A CN102163562A (zh) 2011-08-24
CN102163562B true CN102163562B (zh) 2012-09-19

Family

ID=44464716

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110066085A Expired - Fee Related CN102163562B (zh) 2011-03-18 2011-03-18 一种功率半导体管芯的安装方法和同步降压转换器

Country Status (1)

Country Link
CN (1) CN102163562B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609424A (zh) * 2015-12-24 2016-05-25 江苏长电科技股份有限公司 一种框架外露的夹芯封装工艺方法
CN105489508A (zh) * 2015-12-24 2016-04-13 江苏长电科技股份有限公司 一种防止芯片偏移的夹芯封装工艺方法
CN117832177A (zh) * 2024-03-04 2024-04-05 深圳市沃芯半导体技术有限公司 开关电源模块封装系统及封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1691327A (zh) * 2004-04-19 2005-11-02 株式会社瑞萨科技 半导体器件
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
JP2008177588A (ja) * 2008-02-12 2008-07-31 Renesas Technology Corp 半導体装置
CN101295687A (zh) * 2007-04-27 2008-10-29 株式会社瑞萨科技 半导体器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
CN1691327A (zh) * 2004-04-19 2005-11-02 株式会社瑞萨科技 半导体器件
CN101295687A (zh) * 2007-04-27 2008-10-29 株式会社瑞萨科技 半导体器件
JP2008177588A (ja) * 2008-02-12 2008-07-31 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
CN102163562A (zh) 2011-08-24

Similar Documents

Publication Publication Date Title
JP6919134B2 (ja) モジュールとして構成されるマルチレベルリードフレームを有するパッケージングされた半導体デバイス
CN101356633B (zh) 半导体裸片的封装方法以及通过该方法形成的裸片封装
CN101859755B (zh) 一种功率mosfet封装体及其封装方法
CN101312162B (zh) 一种制造半导体器件的方法
KR101643332B1 (ko) 초음파 웰딩을 이용한 클립 본딩 반도체 칩 패키지 및 그 제조 방법
EP2802064B1 (en) Power module and encapsulation method thereof
US8399997B2 (en) Power package including multiple semiconductor devices
CN101681897A (zh) 双侧冷却集成功率装置封装和模块及其制造方法
US20130026616A1 (en) Power device package module and manufacturing method thereof
US8063472B2 (en) Semiconductor package with stacked dice for a buck converter
KR101354894B1 (ko) 반도체 패키지, 그 제조방법 및 이를 포함하는 반도체 패키지 모듈
CN103608917A (zh) 超薄功率晶体管和具有定制占位面积的同步降压变换器
CN103681369A (zh) 半导体器件及其制造方法
JP5262983B2 (ja) モールドパッケージおよびその製造方法
CN102163562B (zh) 一种功率半导体管芯的安装方法和同步降压转换器
CN102270589A (zh) 半导体元件的制造方法和相应的半导体元件
CN102412225A (zh) Bga半导体封装及其制造方法
CN101183673A (zh) 堆叠式多芯片半导体封装结构及封装方法
JP2008235859A (ja) 半導体装置とその製造方法
US7649746B2 (en) Semiconductor device with inductor
US11705387B2 (en) Multi-layer interconnection ribbon
CN114899182A (zh) 微型led器件的封装结构及方法以及显示装置
JP4600130B2 (ja) 半導体装置およびその製造方法
TW201332031A (zh) 用於一半導體封裝之基板製程、封裝方法、封裝結構及系統級封裝結構
CN106469707B (zh) 晶片封装制程及具有晶片封装体的可挠性线路载板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120919

Termination date: 20130318