JP2008177588A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008177588A JP2008177588A JP2008030458A JP2008030458A JP2008177588A JP 2008177588 A JP2008177588 A JP 2008177588A JP 2008030458 A JP2008030458 A JP 2008030458A JP 2008030458 A JP2008030458 A JP 2008030458A JP 2008177588 A JP2008177588 A JP 2008177588A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- electrode pad
- source
- gate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 239000011347 resin Substances 0.000 claims abstract description 37
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 description 48
- 239000000758 substrate Substances 0.000 description 43
- 239000010410 layer Substances 0.000 description 30
- 238000004519 manufacturing process Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 239000004020 conductor Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- NLYAJNPCOHFWQQ-UHFFFAOYSA-N kaolin Chemical compound O.O.O=[Al]O[Si](=O)O[Si](=O)O[Al]=O NLYAJNPCOHFWQQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 金属製のヘッダと、このヘッダ上に固定されるパワーMOSFETを構成する半導体チップと、半導体チップやヘッダ等を被う絶縁性樹脂からなる封止体とを有し、ヘッダに連なり封止体の一側面から突出するドレインリードと、封止体の一側面から並んで突出するソースリードおよびゲートリードと、封止体内に位置し半導体チップの上面の電極とソースリードおよびゲートリードを接続するワイヤとを有する半導体装置であって、ゲートリード及びソースリードのリードポストに対して、ゲート電極パッドは近い位置にあり、ソース電極パッドは遠い位置にある。
【選択図】 図1
Description
本発明の一つの目的は、支持基板上により大きいサイズの半導体チップを固定できる半導体装置を提供することにある。
本発明の一つの目的は、電気的信頼性の高い半導体装置の製造方法を提供することにある。
(1)低オン抵抗の半導体装置を提供することができる。
(2)支持基板上により大きいサイズの半導体チップを固定できる半導体装置を提供することができ、高出力の半導体装置を提供することができる。
(実施形態1)
図1乃至図8は本発明の一実施形態(実施形態1)である半導体装置に係わる図である。図1は樹脂封止体を取り除いた半導体装置の模式的平面図、図2は半導体装置の断面図、図3は半導体装置に組み込まれる半導体チップの模式的平面図、図4は図3のA−A線に沿う断面図、図5はゲート電極パッドをチップのコーナに配置した状態を示すチップの一部を示す平面図、図6はゲート電極パッドをチップの辺の途中に配置した状態を示すチップの一部を示す平面図である。
本実施形態1によれば、以下の効果を奏する。
図9は本発明の他の実施形態(実施形態2)である半導体装置の樹脂封止体を取り除いた模式的平面図、図10は半導体装置の断面図である。
図11は本発明の他の実施形態(実施形態3)である半導体装置の樹脂封止体を取り除いた模式的平面図、図12は半導体装置の断面図である。
図13は本発明の他の実施形態(実施形態4)である半導体装置の樹脂封止体を取り除いた模式的平面図である。
図14は本発明の他の実施形態(実施形態5)である半導体装置の樹脂封止体を取り除いた模式的平面図、図15は半導体装置の断面図、図16は半導体装置の製造で使用するリードフレームの平面図である。
図17は本発明の他の実施形態(実施形態6)である半導体装置の樹脂封止体を取り除いた模式的平面図、図18は半導体装置の断面図である。
図19は本発明の他の実施形態(実施形態7)である半導体装置の樹脂封止体を取り除いた模式的平面図、図20は半導体装置の断面図である。
図21は本発明の他の実施形態(実施形態8)である半導体装置の樹脂封止体を取り除いた模式的平面図である。
図22は本発明の他の実施形態(実施形態9)である半導体装置の模式的断面図である。本実施形態9は、実施形態1のパワートランジスタ1において、封止体2の端面から突出するドレインリード4,ソースリード5,ゲートリード6の3本のリードを、途中で折れ曲がるように成形し、先端は支持基板3の下面と略同じ高さに位置させて延在させた構造になっている。この先端の延在部分60は、パワートランジスタ1を実装基板等に支持基板3を固定する際、3本のリードの先端の延在部分60は実装基板に設けた配線との接続部分になる。実施形態9のパワートランジスタ1は面実装構造になっている。なお、ドレインリード4は支持基板3と同じ電位になることから、封止体2から突出する付け根部分で切断して実装基板には接続しない構造としてもよい。本実施形態8のパワートランジスタ1も実施形態1のパワートランジスタ1と同様の効果を有する。
Claims (2)
- MOSFETを含み、上面に前記MOSFETのゲート電極パッドおよびソース電極パッドが形成され下面にドレイン電極パッドが形成された半導体チップと、
前記半導体チップが搭載され、かつ前記ドレイン電極パッドと電気的に接続されたヘッダと、
前記ヘッダと電気的に接続されたドレインリードと、
前記ゲート電極パッドと導電性ワイヤを介して電気的に接続されたゲートリードと、
前記ソース電極パッドと金属板を介して電気的に接続されたソースリードと、
前記ヘッダ、ドレインリード、ソースリード、ゲートリードの一部、前記導電性ワイヤ、前記金属板および前記半導体チップを覆う絶縁性樹脂を有し、
前記ヘッダの下面は前記絶縁性樹脂の下面から露出し、
前記ドレインリード、ゲートリードおよびソースリードの一部は前記絶縁性樹脂の側面から露出し、
前記絶縁性樹脂の側面から露出したソースリードは、前記絶縁性樹脂の側面から露出したゲートリードとドレインリードの間に位置していることを特徴とする半導体装置。 - MOSFETを含み、上面に前記MOSFETのゲート電極パッドおよびソース電極パッドが形成され下面にドレイン電極パッドが形成された半導体チップと、
前記半導体チップが搭載され、かつ前記ドレイン電極パッドと電気的に接続されたヘッダと、
前記ヘッダと電気的に接続されたドレインリードと、
前記ゲート電極パッドと第1導電性ワイヤを介して電気的に接続されたゲートリードと、
前記ソース電極パッドと複数の第2導電性ワイヤを介して電気的に接続されたソースリードと、
前記ヘッダ、ドレインリード、ソースリード、ゲートリードの一部、前記第1導電性ワイヤ、第2導電性ワイヤおよび前記半導体チップを覆う絶縁性樹脂を有し、
前記ソースパッドと前記ゲートリードの距離は、前記ソースパッドと前記ソースリードの距離よりも長く、
前記ヘッダの下面は前記絶縁性樹脂の下面から露出し、
前記ドレインリード、ゲートリードおよびソースリードの一部は前記絶縁性樹脂の側面から露出し、
前記絶縁性樹脂の側面から露出したソースリードは、前記絶縁性樹脂の側面から露出したゲートリードとドレインリードの間に位置していることを特徴とすることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008030458A JP4746061B2 (ja) | 2008-02-12 | 2008-02-12 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008030458A JP4746061B2 (ja) | 2008-02-12 | 2008-02-12 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003187377A Division JP4248953B2 (ja) | 2003-06-30 | 2003-06-30 | 半導体装置およびその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011086201A Division JP5388235B2 (ja) | 2011-04-08 | 2011-04-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008177588A true JP2008177588A (ja) | 2008-07-31 |
JP4746061B2 JP4746061B2 (ja) | 2011-08-10 |
Family
ID=39704319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008030458A Expired - Fee Related JP4746061B2 (ja) | 2008-02-12 | 2008-02-12 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4746061B2 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102163562A (zh) * | 2011-03-18 | 2011-08-24 | 聚信科技有限公司 | 一种功率半导体管芯的安装方法和同步降压转换器 |
JP2012227432A (ja) * | 2011-04-21 | 2012-11-15 | Fujitsu Semiconductor Ltd | 半導体装置 |
JP2013093444A (ja) * | 2011-10-26 | 2013-05-16 | Rohm Co Ltd | 高速スイッチング動作回路 |
JP2014130896A (ja) * | 2012-12-28 | 2014-07-10 | Toyota Motor Corp | 半導体装置 |
JP2016129192A (ja) * | 2015-01-09 | 2016-07-14 | 株式会社デンソー | 半導体装置 |
CN105789307A (zh) * | 2015-01-13 | 2016-07-20 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
JP2017017995A (ja) * | 2016-10-12 | 2017-01-19 | ローム株式会社 | 高速スイッチング動作回路を備えたワイヤレス給電装置およびac/dc電源回路 |
JP2021166297A (ja) * | 2020-07-13 | 2021-10-14 | ローム株式会社 | スイッチング素子 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5991045B2 (ja) | 2012-06-28 | 2016-09-14 | 住友電気工業株式会社 | 半導体装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05166984A (ja) * | 1991-12-16 | 1993-07-02 | Hitachi Ltd | 半導体装置 |
JPH0864634A (ja) * | 1994-08-23 | 1996-03-08 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000049184A (ja) * | 1998-05-27 | 2000-02-18 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2001068502A (ja) * | 1999-08-30 | 2001-03-16 | Nec Kansai Ltd | 半導体装置 |
JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
JP2002314018A (ja) * | 2001-04-18 | 2002-10-25 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2003068961A (ja) * | 2001-08-20 | 2003-03-07 | Chie Kan Pan Tao Teii Kofun Yugenkoshi | 電力用半導体パッケージ及びその製造方法 |
-
2008
- 2008-02-12 JP JP2008030458A patent/JP4746061B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05166984A (ja) * | 1991-12-16 | 1993-07-02 | Hitachi Ltd | 半導体装置 |
JPH0864634A (ja) * | 1994-08-23 | 1996-03-08 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000049184A (ja) * | 1998-05-27 | 2000-02-18 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2001068502A (ja) * | 1999-08-30 | 2001-03-16 | Nec Kansai Ltd | 半導体装置 |
JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
JP2002314018A (ja) * | 2001-04-18 | 2002-10-25 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2003068961A (ja) * | 2001-08-20 | 2003-03-07 | Chie Kan Pan Tao Teii Kofun Yugenkoshi | 電力用半導体パッケージ及びその製造方法 |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102163562B (zh) * | 2011-03-18 | 2012-09-19 | 聚信科技有限公司 | 一种功率半导体管芯的安装方法和同步降压转换器 |
CN102163562A (zh) * | 2011-03-18 | 2011-08-24 | 聚信科技有限公司 | 一种功率半导体管芯的安装方法和同步降压转换器 |
JP2012227432A (ja) * | 2011-04-21 | 2012-11-15 | Fujitsu Semiconductor Ltd | 半導体装置 |
JP2013093444A (ja) * | 2011-10-26 | 2013-05-16 | Rohm Co Ltd | 高速スイッチング動作回路 |
JP2014130896A (ja) * | 2012-12-28 | 2014-07-10 | Toyota Motor Corp | 半導体装置 |
JP2016129192A (ja) * | 2015-01-09 | 2016-07-14 | 株式会社デンソー | 半導体装置 |
CN105789307B (zh) * | 2015-01-13 | 2021-04-02 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
CN105789307A (zh) * | 2015-01-13 | 2016-07-20 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
JP2016131183A (ja) * | 2015-01-13 | 2016-07-21 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10236371B2 (en) | 2015-01-13 | 2019-03-19 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10475918B2 (en) | 2015-01-13 | 2019-11-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
JP2017017995A (ja) * | 2016-10-12 | 2017-01-19 | ローム株式会社 | 高速スイッチング動作回路を備えたワイヤレス給電装置およびac/dc電源回路 |
JP2021166297A (ja) * | 2020-07-13 | 2021-10-14 | ローム株式会社 | スイッチング素子 |
JP7161582B2 (ja) | 2020-07-13 | 2022-10-26 | ローム株式会社 | スイッチング素子 |
JP2022185146A (ja) * | 2020-07-13 | 2022-12-13 | ローム株式会社 | スイッチング素子およびスイッチング電源回路 |
JP7394944B2 (ja) | 2020-07-13 | 2023-12-08 | ローム株式会社 | スイッチング素子およびスイッチング電源回路 |
Also Published As
Publication number | Publication date |
---|---|
JP4746061B2 (ja) | 2011-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4248953B2 (ja) | 半導体装置およびその製造方法 | |
JP4746061B2 (ja) | 半導体装置 | |
JP4294405B2 (ja) | 半導体装置 | |
US7763967B2 (en) | Semiconductor device with surface mounting terminals | |
US8629467B2 (en) | Semiconductor device | |
JP2008294384A (ja) | 半導体装置 | |
JP2009147103A (ja) | 半導体装置およびその製造方法 | |
JP5271778B2 (ja) | 半導体装置の製造方法 | |
JP5665206B2 (ja) | 半導体装置 | |
JP2013016837A (ja) | 半導体装置 | |
JP2005243685A (ja) | 半導体装置 | |
JP2015019115A (ja) | 半導体装置 | |
JP5388235B2 (ja) | 半導体装置 | |
JP2005101293A (ja) | 半導体装置 | |
JP2020113721A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2016040839A (ja) | 半導体装置の製造方法 | |
JP5512845B2 (ja) | 半導体装置 | |
WO2022153902A1 (ja) | 半導体装置 | |
JP4246598B2 (ja) | 電力用半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100511 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110215 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110408 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110510 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110512 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4746061 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |