JP2016131183A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2016131183A JP2016131183A JP2015004147A JP2015004147A JP2016131183A JP 2016131183 A JP2016131183 A JP 2016131183A JP 2015004147 A JP2015004147 A JP 2015004147A JP 2015004147 A JP2015004147 A JP 2015004147A JP 2016131183 A JP2016131183 A JP 2016131183A
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Abstract
【解決手段】例えば、パワートランジスタのソース電極SEと容量素子CAPの上部電極UEとが重なる部分を有する。言い換えれば、パワートランジスタのソース電極SE上に、容量絶縁膜CILを介して、容量素子CAPの上部電極UEが形成されている。つまり、半導体チップCHPの厚さ方向にパワートランジスタと容量素子CAPとが積層配置されている。これにより、半導体チップCHPの平面サイズの増大を抑制しながら、パワートランジスタと電気的に接続される容量素子CAPを追加することができる。
【選択図】図3
Description
<半導体装置の回路構成>
まず、本実施の形態1における半導体装置の回路構成について説明する。図1(a)は、一般的なパワートランジスタ(電界効果トランジスタ)を示す回路記号である。図1(a)において、パワートランジスタQ1は、互いに離間して配置されたソースSとドレインDとを有し、ドレインDとソースSとの間を流れる電流のオン/オフ制御をゲートGで行なうように構成されている。すなわち、ソースSとドレインDとの間に電位差を生じさせた状態で、ゲートGにしきい値電圧以上のゲート電圧を印加すると、ゲートGの直下領域に反転層からなるチャネルが形成され、このチャネルを介して、ドレインDとソースSとの間に電流が流れる。一方、ゲートGにしきい値電圧未満のゲート電圧を印加する場合、反転層からなるチャネルが消滅するため、ドレインDとソースSとの間に電流は流れなくなる。このようにして、ゲートGに印加するゲート電圧によって、ドレインDとソースSとの間を流れる電流のオン/オフ制御を行なうことができる。
図2は、本実施の形態1における半導体チップCHPの平面構成を示す図である。図2において、本実施の形態1における半導体チップCHPは、例えば、矩形形状をしており、中央部に形成されているアクティブ領域(活性領域)にパワートランジスタと容量素子が形成されている。具体的に、図2に示すように、アクティブ領域内には、複数のゲート電極GEが互いに並行するように形成されており、複数のゲート電極GEのそれぞれは、例えば、y方向に延在するように配置されている。つまり、個々のゲート電極GEは、単位トランジスタの構成要素となっており、複数の単位トランジスタを並列接続することにより、パワートランジスタが形成されることになる。すなわち、パワートランジスタは、複数の単位トランジスタから構成されていることになる。
続いて、本実施の形態1における半導体装置の実装構成について説明する。図4は、本実施の形態1における半導体装置PKG1の実装構成を示す平面図である。
続いて、本実施の形態1における特徴点について説明する。本実施の形態1における第1特徴点は、例えば、図2に示すように、パワートランジスタのソース電極SEと容量素子CAPの上部電極UEとが重なる部分を有する点にある。言い換えれば、本実施の形態1における第1特徴点は、例えば、図3に示すように、パワートランジスタのソース電極SE上に、容量絶縁膜CILを介して、容量素子CAPの上部電極UEが形成されている点にある。つまり、本実施の形態1における第1特徴点は、半導体チップCHPの厚さ方向にパワートランジスタと容量素子CAPとが積層配置されている点にある。
本実施の形態1における半導体装置は、上記のように構成されており、以下に、その製造方法について、図面を参照しながら説明する。
次に、本変形例1における半導体装置PKG2の実装構成について説明する。図14は、本変形例1における半導体装置PKG2の実装構成を示す平面図である。図14において、本変形例1では、上部電極UE(上部電極露出領域)とチップ搭載部TABとが、ワイヤW3で直接接続されている。これにより、本変形例1によれば、半導体チップCHPの表面にドレインパッドを設ける必要がなくなる分だけ、半導体チップCHPの平面サイズを縮小することができる。つまり、本変形例1における半導体装置PKG2の実装構成によれば、半導体装置PKG2の小型化を推進することができる。
続いて、本変形例2における半導体装置PKG3の実装構成について説明する。図15は、本変形例2における半導体装置PKG3の実装構成を示す平面図である。図15において、本変形例2では、半導体チップCHPの平面サイズの増加を抑制しながら、容量素子の上部電極UEの平面積をできるだけ増加する思想が具現化されている。具体的には、図15に示すように、ソース電極SEのうち、複数のワイヤW1と接続する領域を除いて、その他の部分を覆うように、上部電極UEの平面積を大きくしている。例えば、図15に示すように、上部電極UEの一部に平面的な凹凸形状を形成することにより、ソース電極SEに複数のワイヤW1と接続する領域を確保しながら、ソース電極SEの平面積に近づくように、上部電極UEの平面積をできるだけ大きくすることができる。
次に、本変形例3における半導体装置PKG4の実装構成について説明する。図16は、本変形例3における半導体装置PKG4の実装構成を示す平面図である。図16において、本変形例3では、半導体チップCHPの表面にドレインパッドDP1およびドレインパッドDP2が形成されており、ドレインパッドDP1およびドレインパッドDP2のそれぞれは、上部電極UEと電気的に接続されている。
前記実施の形態1では、パワートランジスタの一例として、パワーMOSFETを例に挙げて説明したが、前記実施の形態1における技術的思想は、これに限らず、IGBT(絶縁ゲートバイポーラトランジスタ)にも適用することができる。
まず、IGBTのデバイス構造について説明する。図17は、本実施の形態2におけるIGBTのデバイス構造を示す断面図である。図17において、IGBTは、半導体チップCHPの裏面に形成されたコレクタ電極CE(コレクタ電極パッド)を有し、このコレクタ電極CE上に半導体基板1S(ここでは、p型半導体基板)が形成されている。半導体基板1S上にはp型半導体層PLが形成され、このp型半導体層PL上にドリフト層EPが形成されている。そして、ドリフト層EP上にはチャネル層CHが形成され、このチャネル層CHを貫通し、ドリフト層EPに達するトレンチTRが形成されている。さらに、トレンチTRに整合してn+型半導体領域からなるエミッタ領域ERが形成されている。トレンチTRの内部には、例えば、酸化シリコン膜よりなるゲート絶縁膜GOXが形成され、このゲート絶縁膜GOXを介してゲート電極GEが形成されている。このゲート電極GEは、例えば、ポリシリコン膜から形成され、トレンチTRを埋め込むように形成されている。そして、エミッタ領域ERに隣接するチャネル層CHの表面には、ボディコンタクト領域BCが形成されている。
次に、本実施の形態2におけるIGBTの動作について説明する。まず、IGBTがターンオンする動作について説明する。図17において、ゲート電極GEと、エミッタ領域ERとの間に充分な正の電圧を印加することにより、トレンチゲート構造をしたMOSFETがターンオンする。この場合、コレクタ領域であるp型半導体層PLとドリフト層EPとの間が順バイアスされ、p型半導体層PLからドリフト層EPへ正孔注入が起こる。続いて、注入された正孔のプラス電荷と同じだけの電子がドリフト層EPに集まる。この結果、ドリフト層EPの抵抗低下が起こり(伝導度変調)、IGBTはオン状態となる。
以上のようにして、本実施の形態2における半導体チップにパワートランジスタの一例であるIGBTが形成されている。そして、本実施の形態2においても、半導体チップの厚さ方向において、IGBT上に容量素子CAPが積層配置されている。
CHP 半導体チップ
CIL 容量絶縁膜
DE ドレイン電極
GE ゲート電極
Q1 パワートランジスタ
SE ソース電極
UE 上部電極
Claims (15)
- パワートランジスタと、前記パワートランジスタと電気的に接続された容量素子とが形成された半導体チップを備え、
前記パワートランジスタは、
前記半導体チップの厚さ方向において、互いに離間して配置されたソース電極およびドレイン電極と、
前記ドレイン電極と前記ソース電極との間を流れる電流のオン/オフを制御するゲート電極と、
を有し、
前記容量素子は、
下部電極である前記ソース電極と、
前記ソース電極上に形成された容量絶縁膜と、
前記容量絶縁膜上に形成され、かつ、前記ドレイン電極と電気的に接続された上部電極と、
を有し、
平面視において、前記ソース電極と前記上部電極とは重なる部分を有する、半導体装置。 - 請求項1に記載の半導体装置において、
平面視において、前記上部電極は、前記ソース電極に内包される、半導体装置。 - 請求項1に記載の半導体装置において、
前記パワートランジスタと前記容量素子とは、前記半導体チップの厚さ方向に積層配置されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記パワートランジスタは、
半導体基板と、
前記半導体基板の裏面に形成された前記ドレイン電極と、
前記半導体基板の表面上に形成されたドリフト層と、
前記ドリフト層上に形成されたチャネル層と、
前記チャネル層を貫通して前記ドリフト層に達するトレンチと、
前記トレンチの内壁に形成されたゲート絶縁膜と、
前記ゲート絶縁膜を介して前記トレンチに埋め込まれたゲート電極と、
前記トレンチに接し、かつ、前記チャネル層の表面に形成されたソース領域と、
前記ソース領域と電気的に接続された前記ソース電極と、
を有する、半導体装置。 - 請求項4に記載の半導体装置において、
前記ソース電極は、前記ソース領域上から前記ゲート電極上にわたって形成され、
前記ソース電極と前記ゲート電極との間に絶縁膜が介在する、半導体装置。 - 請求項1に記載の半導体装置において、
チップ搭載部と、
前記チップ搭載部上に搭載された前記半導体チップと、
を有し、
前記半導体チップの裏面には、前記ドレイン電極が形成され、
前記半導体チップの表面には、前記ゲート電極と電気的に接続されたゲートパッドと前記ソース電極と前記上部電極とが形成され、
平面視において、前記半導体チップの表面には、前記上部電極が露出している上部電極露出領域と、前記ソース電極が露出しているソース電極露出領域とが形成され、かつ、前記ゲートパッドが露出している、半導体装置。 - 請求項6に記載の半導体装置において、
前記チップ搭載部と連結されたドレインリードと、
前記チップ搭載部と離間して配置されたソースリードと、
前記チップ搭載部と離間して配置されたゲートリードと、
を有する、半導体装置。 - 請求項7に記載の半導体装置において、
前記ソース電極露出領域と前記ソースリードとは第1導電性部材で接続され、
前記ゲートパッドと前記ゲートリードとは第2導電性部材で接続され、
前記上部電極露出領域と前記チップ搭載部とは第3導電性部材で接続されている、半導体装置。 - 請求項8に記載の半導体装置において、
前記ソース電極露出領域と前記ソースリードとは複数の第1導電性部材で接続され、
前記上部電極露出領域と前記チップ搭載部とは複数の第3導電性部材で接続されている、半導体装置。 - 請求項7に記載の半導体装置において、
前記ソース電極露出領域と前記ソースリードとは第1導電性部材で接続され、
前記ゲートパッドと前記ゲートリードとは第2導電性部材で接続され、
前記半導体チップの表面には、前記上部電極と電気的に接続されたドレインパッドが露出し、
前記ドレインパッドと前記チップ搭載部とは第3導電性部材で接続されている、半導体装置。 - 請求項10に記載の半導体装置において、
前記半導体チップの表面には、前記上部電極と電気的に接続された前記ドレインパッドが複数存在する、半導体装置。 - 請求項1に記載の半導体装置において、
前記容量絶縁膜の膜厚は、50nm以上250nm以下である、半導体装置。 - パワートランジスタと前記パワートランジスタと電気的に接続された容量素子とが形成された半導体チップを備え、
前記パワートランジスタは、
前記半導体チップの厚さ方向において、互いに離間して配置されたエミッタ電極およびコレクタ電極と、
前記コレクタ電極と前記エミッタ電極との間を流れる電流のオン/オフを制御するゲート電極と、
を有し、
前記容量素子は、
下部電極である前記エミッタ電極と、
前記エミッタ電極上に形成された容量絶縁膜と、
前記容量絶縁膜上に形成され、かつ、前記コレクタ電極と電気的に接続された上部電極と、
を有し、
平面視において、前記エミッタ電極と前記上部電極とは重なる部分を有する、半導体装置。 - 請求項13に記載の半導体装置において、
前記パワートランジスタは、絶縁ゲートバイポーラトランジスタである、半導体装置。 - パワートランジスタと前記パワートランジスタと電気的に接続された容量素子とを備え、
前記パワートランジスタは、
互いに離間して配置されたソース電極およびドレイン電極と、
前記ドレイン電極と前記ソース電極との間を流れる電流のオン/オフを制御するゲート電極と、
を有し、
前記容量素子は、
下部電極である前記ソース電極と、
前記ソース電極上に形成された容量絶縁膜と、
前記容量絶縁膜上に形成され、かつ、前記ドレイン電極と電気的に接続された上部電極と、
を有し、
平面視において、前記ソース電極と前記上部電極とは重なる部分を有する、半導体装置の製造方法であって、
(a)表面上に形成されたドリフト層と前記ドリフト層上に形成されたチャネル層とを有する半導体基板を用意する工程、
(b)前記チャネル層を貫通して前記ドリフト層に達するトレンチを形成する工程、
(c)前記トレンチの内壁にゲート絶縁膜を形成する工程、
(d)前記ゲート絶縁膜を介して前記トレンチを埋め込むゲート電極を形成する工程、
(e)前記(d)工程の後、前記トレンチに接するように、前記チャネル層の表面にソース領域を形成する工程、
(f)前記(e)工程の後、前記ゲート電極の上面を覆う絶縁膜を形成する工程、
(g)前記(f)工程の後、前記ソース領域と接続される前記ソース電極を形成する工程、
(h)前記ソース電極上に前記容量絶縁膜を形成する工程、
(i)前記容量絶縁膜上に前記上部電極を形成する工程、
(j)前記半導体基板の裏面に前記ドレイン電極を形成する工程、
を有する、半導体装置の製造方法。
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JP2019195013A (ja) * | 2018-05-01 | 2019-11-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP7097742B2 (ja) | 2018-05-01 | 2022-07-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2020136808A1 (ja) * | 2018-12-27 | 2020-07-02 | 三菱電機株式会社 | 半導体素子構造 |
JPWO2020136808A1 (ja) * | 2018-12-27 | 2021-09-30 | 三菱電機株式会社 | 半導体素子構造 |
JP7076576B2 (ja) | 2018-12-27 | 2022-05-27 | 三菱電機株式会社 | 半導体素子構造 |
JP7388015B2 (ja) | 2019-07-02 | 2023-11-29 | セイコーエプソン株式会社 | 集積回路装置、発振器、電子機器及び移動体 |
JP6999776B2 (ja) | 2020-10-21 | 2022-01-19 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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US9564426B2 (en) | 2017-02-07 |
US10236371B2 (en) | 2019-03-19 |
EP3046140A2 (en) | 2016-07-20 |
CN105789307A (zh) | 2016-07-20 |
US20160204099A1 (en) | 2016-07-14 |
JP6462367B2 (ja) | 2019-01-30 |
EP3046140A3 (en) | 2016-08-10 |
US10475918B2 (en) | 2019-11-12 |
US20190165165A1 (en) | 2019-05-30 |
CN105789307B (zh) | 2021-04-02 |
EP3046140B1 (en) | 2021-09-22 |
US20170125581A1 (en) | 2017-05-04 |
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