CN105789307B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN105789307B
CN105789307B CN201510821859.3A CN201510821859A CN105789307B CN 105789307 B CN105789307 B CN 105789307B CN 201510821859 A CN201510821859 A CN 201510821859A CN 105789307 B CN105789307 B CN 105789307B
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electrode
power transistor
semiconductor device
gate
source
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CN105789307A (zh
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河合徹
中柴康隆
秋山丰
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

在不增加半导体芯片的面积尺寸的情况下，改善了半导体器件的性能。例如，功率晶体管的源极电极和电容元件的上部电极具有重叠部分。换而言之，电容元件的上部电极通过电容绝缘膜在功率晶体管的源极电极之上形成。即，功率晶体管和电容元件在半导体芯片的厚度方向上以层压的方式布置。结果就是，可以在抑制半导体芯片的平面尺寸增加的同时增加与功率晶体管电连接的电容元件。

Description

半导体器件及其制造方法
相关申请的交叉引用
通过引用将2015年1月13日提交的第2015-004147号日本专利申请的全部公布内容，包括说明书、附图和摘要，并入本文。
技术领域
本发明涉及半导体器件及其制造技术，并且具体涉及应用于具有功率晶体管的半导体器件及其制造技术的有效的技术。
背景技术
日本专利特开第2004-186634号(专利文献1)公开了下述技术：允许高频噪声分量流入连接在结型FET(结型场效应晶体管)的源极电极和漏极电极之间充当旁路的电容器。
[专利文献1]
日本专利特开第2004-186634号
发明内容
根据专利文献1描述的技术，如专利文献1的图2所示，在平面视图中，电容器形成在与形成结型FET的区域不同的区域。为此，可以想到的是会出现形成结型FET和电容器的半导体芯片的平面尺寸增大的问题。
本发明的目的在于提供一种在不增加半导体器件的尺寸的情况下改善半导体器件的性能的技术。
根据本说明书的描述和附图，本发明的上述目的和其他目的以及新颖特征将会清楚。
根据一种实施方式的半导体器件包括：功率晶体管；以及电容元件，该电容元件电连接在该功率晶体管的第一电极和第二电极之间。该电容元件和该功率晶体管布置为在平面视图中至少有部分重叠。
进一步地，制造根据上述一种实施方式的半导体器件的方法包括下述步骤：形成功率晶体管的源极电极，该源极电极还充当该电容元件的下部电极；在所述源极电极之上形成该电容元件的电容绝缘膜；以及在所述电容绝缘膜之上形成该电容元件的上部电极。
根据一种实施方式，可以在不增加半导体芯片的面积尺寸的情况下改善半导体器件的性能。
附图说明
图1A和图1B是电路图，其中，图1A示出了表示通常采用的功率晶体管的电路符号，图1B示出了根据第一实施方式的半导体器件的电路结构；
图2示出了根据第一实施方式的半导体芯片的平面结构；
图3是沿着图2中的线A-A截取的横截面视图；
图4是示出根据第一实施方式的半导体器件的封装结构的平面视图；
图5是沿着图4中的A-A截取的横截面视图；
图6是示出制造根据第一实施方式的半导体器件的工序的横截面视图；
图7是示出继图6之后的制造半导体器件的工序的横截面视图；
图8是示出继图7之后的制造半导体器件的工序的横截面视图；
图9是示出继图8之后的制造半导体器件的工序的横截面视图；
图10是示出继图9之后的制造半导体器件的工序的横截面视图；
图11是示出继图10之后的制造半导体器件的工序的横截面视图；
图12是示出继图11之后的制造半导体器件的工序的横截面视图；
图13是示出继图12之后的制造半导体器件的工序的横截面视图；
图14是示出根据变形例1的半导体器件的封装结构的平面视图；
图15是示出根据变形例2的半导体器件的封装结构的平面视图；
图16是示出根据变形例3的半导体器件的封装结构的平面视图；
图17是示出根据第二实施方式的IGBT的设备结构的横截面视图。
具体实施方式
若为了方便需要，下面的实施方式将分成多个部分或多个实施方式描述。除了特别明示的情形之外，它们不是彼此不相关的，而是具有关系的，例如，一者是另一者的部分或全部的变形、具体说明以及补充说明。
在下面的实施方式中，当涉及元件的数字等(包括数目、数值、总数、范围等)，它们不限于特定的数，而是可以大于或小于该特定的数，除了它们特别清楚地指出以及它们理论上明显地限于特定的数的情形之外。
而且，在下面的实施方式中，无需说明，元件(包括构成步骤等)不一定是不可缺少的，除了清楚地指出以及从理论的角度来看认为是明显不可缺少的情形之外。
类似地，在下面的实施方式中，当涉及元件等的形状、位置关系等时，除了特别清楚地指出以及从理论的角度来看认为明显不对的情形之外，包括与所述形状等相似或类似的形状等。本声明还适用于上面描述的数值和范围。
在解释实施方式的所有附图中，原则上，相同部件附上相同的符号，省略其重复说明。为了使附图容易理解，即使在平面视图中也可以附上阴影线。
第一实施方式
<半导体器件的电路结构>
首先，将说明根据第一实施方式的半导体器件的电路结构。图1A示出了表示通常使用的功率晶体管(场效应晶体管)的电路符号。在图1A中，功率晶体管Q1具有彼此间隔开的源极S和漏极D，以及栅极G，该栅极控制导通/断开漏极D和源极S之间流动的电流。即，在源极S和漏极D之间产生电势差的状态下，当等于或大于阈值电压的栅极电压施加于栅极G时，在直接位于栅极G之下的区域形成包括反型层的沟道，并且电流通过该沟道在漏极D和源极S之间流动。另一方面，当小于阈值电压的栅极电压施加于栅极G时，包括反型层的沟道消失，导致没有电流在漏极D和源极S之间流动。因此，能够通过施加于栅极G的栅极电压控制导通/断开漏极D和源极S之间流动的电流。
在如上配置的通常使用的功率晶体管Q1中，例如，当高频噪声从漏极D输入功率晶体管Q1时，由于功率晶体管Q1中存在的寄生电阻而可能在功率晶体管Q1中产生噪声。因此，为了改善半导体器件的性能，需要抑制由于高频噪声而在功率晶体管Q1中产生噪声。
因此，在根据第一实施方式的半导体器件中，采用下面所示的电路结构。更为具体而言，图1B示出了根据第一实施方式的半导体器件的电路结构。如图1B所示，在根据第一实施方式的半导体器件中，电容元件CAP与功率晶体管Q1并联。即，电容元件CAP连接在功率晶体管Q1的漏极D和源极S之间。
因此，根据第一实施方式的半导体器件，可以抑制功率晶体管Q1由于高频噪声而产生噪声。因为从功率晶体管Q1的漏极D输入的高频噪声不会经过功率晶体管Q1，例如，而是经过电容元件CAP并且从源极S输出。即，由于对于高频噪声而言电容元件CAP的阻抗变得较小，高频噪声流过小阻抗的电容元件CAP而不流过由于寄生电阻而使阻抗较大的功率晶体管Q1。结果就是，根据第一实施方式的半导体器件，可以抑制由于高频噪声而在功率晶体管Q1中产生噪声。而且，根据第一实施方式的电路结构具有平滑噪声的优势，所述平滑噪声是通过电容元件CAP，归因于功率晶体管Q1开关时的电压变化。结果就是，根据图1B所示的电路结构，可以改善包括功率晶体管Q1的半导体器件的性能。因此，根据第一实施方式，从改善包括功率晶体管Q1的半导体器件的性能的方面来看，采用图1B所示的电路结构。在下文中，将说明包含图1B所示电路结构的半导体器件的装置结构。
<半导体器件的装置结构>
图2示出了第一实施方式的半导体芯片CHP的平面结构。在图2中，根据第一实施方式的半导体芯片CHP是，例如，矩形的。功率晶体管和电容元件形成在中央部分形成的有源区。更为具体而言，如图2所示，在有源区中，多个栅极电极GE形成为彼此并行。栅极电极GE布置为，例如，分别沿着Y方向延伸。即，栅极电极GE包含在单元晶体管中，并且通过连接并行的多个单元晶体管形成所述功率晶体管。即，所述功率晶体管包括这些单元晶体管。
同样，如图2所示，在栅极电极GE之上，形成功率晶体管的源极电极SE。而且，根据第一实施方式，电容元件的上部电极UE形成为与源极电极SE部分重叠。具体而言，在图2中，在形成栅极电极GE的整个有源区之上，形成功率晶体管的源极电极SE。在平面视图中，电容元件的上部电极UE形成为包含在源极电极SE中。换而言之，功率晶体管的源极电极SE的平面面积变得比电容元件的上部电极UE的平面面积大。
在远离有源区的角部，如图2所示，形成漏极焊盘DP。在有源区形成的电容元件的上部电极UE与该漏极焊盘DP电连接。而且，在形成漏极焊盘DP的角部的对角的角部形成栅极焊盘GP。尽管图2中未示出，栅极焊盘GP与有源区内形成的多个栅极电极GE电连接。这样，形成了根据第一实施方式的半导体芯片CHP的平面结构。
图3是沿着图2中的线A-A截取的横截面视图。如图3所示，在第一实施方式的半导体芯片CHP中，功率晶体管和与该功率晶体管电连接的电容元件CAP在半导体芯片CHP的厚度方向上是层压的。
而且，功率晶体管具有在半导体芯片CHP的厚度方向上彼此间隔开的源极电极SE和漏极电极DE以及控制导通/断开漏极电极DE和源极电极SE之间的电流流动的栅极电极GE。另一方面，电容元件CAP包括充当下部电极的所述源极电极SE、在该源极电极SE之上形成的电容绝缘膜CIL、在该电容绝缘膜CIL之上形成并且与漏极电极DE电连接的上部电极UE。
更为具体而言，在第一实施方式的半导体芯片CHP中，例如，漂移层EP(外延层)在半导体衬底1S之上形成，该半导体衬底包括含有诸如磷(P)和砷(As)之类的n型杂质的硅。漂移层EP包括，例如，主要含有引入诸如磷(P)和砷(As)之类n型杂质的硅的半导体层。这样，功率晶体管的漏区包括半导体衬底1S和漂移层EP。
在漂移层EP的表面之上，形成沟道区CH。并且，形成穿过沟道层CH并且到达漂移层EP的槽TR。此时，沟道区CH包括：例如，引入诸如硼(B)之类的p型杂质的半导体区域。随后，在槽TR的内壁上，形成栅极绝缘膜GOX。进一步地，栅极电极GE形成为通过栅极绝缘膜GOX填充槽TR。栅极绝缘膜GOX包括：例如，氧化硅膜，但这不是限制性的。例如，栅极绝缘膜GOX可包括比氧化硅膜的介电常数高的高介电常数膜。而且，栅极电极GE包括，例如，多晶硅膜。而且，在与槽TR接触的沟道层CH的表面形成源区SR，并且源区SR包括，例如，引入诸如磷(P)和砷(As)之类的n型杂质的半导体区域。而且，为了覆盖栅极电极GE的上表面，例如，形成包括氧化硅膜的绝缘膜IL1。
在沟道层CH的邻近源区SR的表面之上，形成体接触区域BC。体接触区域BC包括，例如，引入诸如硼(B)之类的p型杂质的半导体区域。体接触区域BC的杂质浓度高于沟道区CH的杂质浓度。
随后，如图3所示，在源区SR和体接触区域BC之上，例如，包括铝膜的源极电极SE形成为与源区SR和体接触区域BC接触。因此，源区SR和体接触区域BC通过源极电极SE电连接。此时，体接触区域BC具有确保与源极电极SE欧姆接触的功能。由于存在体接触区域BC，源区SR和沟道区CH以相同电压电势电连接。因此，可以控制将源区SR作为发射极区域，沟道层CH作为基极区域和漂移层EP作为集电极区域的寄生npn双极型晶体管的通/断操作。如上所述，源区SR和沟道层CH是以同一电压电势电连接。这意味着，在寄生npn双极型晶体管的发射极区域和基极区域之间没有电势差，从而能够控制寄生npn双极型晶体管的通/断操作。
就此而言，源极电极SE形成在从源区SR、体接触区域BC的上面到栅极电极GE的上面的范围内，绝缘膜IL1插在源极电极SE和栅极电极GE之间。因此，源极电极SE和栅极电极GE通过绝缘膜IL1而电绝缘。
另一方面，漏极电极DE形成在半导体衬底1S的背表面之上。因此，功率晶体管的包括半导体衬底1S和漂移层EP的漏区与漏极电极DE电连接。这样，在根据第一实施方式的半导体芯片CHP中形成了所述功率晶体管。进一步地，在根据第一实施方式的半导体芯片CHP中，在半导体芯片CHP的厚度方向上，电容元件CAP层压在功率晶体管之上。
更为具体而言，如图3所示，电容绝缘膜CIL形成在功率晶体管的源极电极SE之上，上部电极UE形成在该电容绝缘膜CIL之上。电容绝缘膜CIL的膜厚度是，例如，大于或等于50nm且小于或等于250nm。
结果就是，在第一实施方式的半导体芯片CHP中，形成有：电容绝缘膜CIL，使用源极电极SE作为下部电极并且位于下部电极之上；以及电容元件CAP，包括位于电容绝缘膜CIL之上的上部电极UE。即，在根据第一实施方式的半导体芯片CHP中，在功率晶体管的上部形成有使用源极电极SE作为下部电极的电容元件CAP。即，在根据第一实施方式的半导体芯片CHP中，在采用允许功率晶体管的源极电极SE还充当电容元件CAP的下部电极的配置的同时，功率晶体管和电容元件CAP在半导体芯片CHP的厚度方向以层压方式布置。
由于电容元件CAP的上部电极UE和功率晶体管的漏极电极DE是电连接的，由此可见，在第一实施方式的半导体芯片CHP中，形成了包含图1B所示电路结构的装置结构(功率晶体管Q1和电容元件CAP)。
<半导体器件的封装结构>
接下来，将说明第一实施方式的半导体器件的封装结构。图4是示出根据第一实施方式的半导体器件PKG1的封装结构的平面视图。
根据图4，第一实施方式的半导体器件PKG1具有芯片安装部分TAB，并且在该芯片安装部分TAB之上安装含有参考图2和图3所述的结构的半导体芯片CHP。此时，半导体芯片CHP安装在芯片安装部分TAB之上以使在半导体芯片CHP的背表面之上形成的漏极电极可以接触芯片安装部分TAB。就此而言，在漏极电极在半导体芯片CHP的背表面之上形成的同时，与多个栅极电极电连接的栅极焊盘GP、源极电极SE和上部电极UE在半导体芯片CHP的主表面之上形成。因此，在根据第一实施方式的半导体器件PKG1中，在平面视图中，在半导体芯片CHP的该主表面之上，形成了露出上部电极UE的上部电极露出区域和露出源极电极SE的源极电极露出区域，而且，露出了栅极焊盘GP。
接下来，如图4所示，漏极引线DL与芯片安装部分TAB连接。第一实施方式中的半导体器件PKG1具有栅极引线GL和源极引线SL，该栅极引线和源极引线与芯片安装部分TAB间隔开并且布置为夹着漏极引线DL且与漏极引线DL间隔开。
源极电极露出区域(源极电极SE)和源极引线SL，例如，使用包括金线的导线W1连接。栅极焊盘GP和栅极引线GL，例如，使用包括金线的导线W2连接。另一方面，与上部电极UE电连接的漏极焊盘DP在半导体芯片CHP的表面之上露出。漏极焊盘DP和芯片安装部分TAB，例如，使用包括金线的导线W3连接。
更为具体而言，图5是沿着图4的线A-A截取的横截面视图。如图5所示，在形成功率晶体管的区域(有源区)之外，电容绝缘膜CIL形成在半导体衬底1S之上。在功率晶体管上方形成的电容元件的上部电极UE通过例如在电容绝缘膜CIL的上部形成的线路与布置在有源区之外的电容绝缘膜CIL之上的漏极焊盘DP连接。可以看出，漏极焊盘DP通过导线W3与芯片安装部分TAB的上表面连接。因此，电容元件的上部电极UE通过漏极焊盘DP和导线W3与芯片安装部分TAB电连接。并且，当考虑到芯片安装部分TAB与漏极电极DE接触时，可以看出，电容元件的上部电极UE与在半导体芯片的背表面之上形成的漏极电极DE电连接。如此，完成了半导体器件PKG1的封装。
<第一实施方式的特征>
现在，将说明第一实施方式的特征。第一实施方式的第一特征在于，例如，如图2所示，功率晶体管的源极电极SE和电容元件CAP的上部电极UE具有重叠部分。换而言之，第一实施方式的第一特征在于，例如，如图3所示，电容元件CAP的上部电极UE通过电容绝缘膜CIL形成在功率晶体管的源极电极SE之上。也就是说，根据第一实施方式的第一特征，功率晶体管和电容元件CAP在半导体芯片CHP的厚度方向上以层压的方式布置。
因此，根据第一实施方式，在抑制半导体芯片CHP的平面尺寸增大的同时，可以增加与功率晶体管电连接的电容元件CAP。例如，当在平面中将电容元件与功率晶体管并列布置时，半导体芯片的平面尺寸会增加。具体而言，从允许高频噪声容易进入电容元件的旁路通路的角度而言，期望使电容元件的电容尽可能的大并且使阻抗对高频噪声而言较小。也就是说，为了抑制由于高频噪声而在功率晶体管中产生噪声，期望使与功率晶体管并联的电容元件的电容更大。
然而，例如，电容元件的电容与电极的相向面积成比例。因此，为了增加电容元件的电容，需要增加电容元件的平面尺寸。因此，倘若在平面视图中将电容元件与功率晶体管并排放置，在增加电容元件的电容的同时，半导体芯片的平面尺寸会显著增加。在这样的情形下，使半导体芯片微型化变得困难。并且，当半导体芯片的平面尺寸变大时，安装和密封半导体芯片的封装(半导体器件)的尺寸也会变大。而且，需要设计和研发新封装来安装和密封更大平面尺寸的半导体芯片，使得半导体器件的制造成本增加。
另一方面，根据第一实施方式，例如，如图3所示，功率晶体管和电容元件CAP在半导体芯片CHP的厚度方向上以层压的方式布置。结果就是，根据第一实施方式，可以在增加与功率晶体管电连接的电容元件CAP的同时抑制半导体芯片CHP的平面尺寸的增加。上述是通过将功率晶体管的源极电极SE和电容元件CAP的上部电极UE以重叠方式布置实现的。这样，与在平面视图将电容元件和功率晶体管并列布置情形下的平面尺寸相比，功率晶体管和电容元件CAP的平面尺寸的总和锐减。具体而言，如图2所示，在平面视图中，通过将电容元件CAP的上部电极UE布置为包含在功率晶体管的源极电极SE中，可以使得功率晶体管和电容元件CAP的平面尺寸的总和与单个功率晶体管的平面尺寸基本相等。
进一步地，如第一实施方式所示，在将功率晶体管的源极电极SE和电容元件CAP的上部电极UE以重叠方式布置的结构中，在抑制功率晶体管和电容元件CAP的平面尺寸的总和增加的同时，增加电容元件CAP的电容变得容易。设定：功率晶体管的源极电极SE的面积为“S1”并且电容元件CAP的上部电极UE的面积为“S2(<S1)”，根据第一实施方式的第一特征，可以在保持功率晶体管和电容元件CAP的平面尺寸的总和为“S1”的同时能够使电容元件CAP的平面尺寸(电极的正对面积)为“S2”。另一方面，当在平面视图中将电容元件与功率晶体管并列放置时，为了使电容元件CAP的平面尺寸(电极的正对面积)为“S2”，需要使功率晶体管和电容元件的平面尺寸的总和为“S1+S2”。因此，根据第一实施方式的第一特征，可以看出，可以在增加电容元件CAP的电容的同时有效抑制功率晶体管和电容元件CAP的平面尺寸的总和的增加。
因此，根据第一实施方式的第一特征，可以看出，可以在增加电容元件CAP的同时使半导体芯片微型化。结果就是，根据第一实施方式的第一特征，还可以抑制安装和密封半导体芯片的封装(半导体器件)的尺寸的增加。这意味着，容易将增加电容元件CAP之前已使用的封装再用作安装和密封增加了电容元件CAP的半导体芯片CHP的封装。结果就是，根据第一实施方式的第一特征，不需要设计和研发符合增加了电容元件CAP的半导体芯片CHP的新封装。因此，可以抑制半导体器件的制造成本的增加。
第一实施方式的第二特征在于，例如，如图3所示，功率晶体管的源极电极SE和电容元件CAP的下部电极BE是同一元件。换句话说，第一实施方式的第二特征是一个元件两用，既作为功率晶体管的源极电极SE又作为电容元件CAP的下部电极BE，实际上是功率晶体管的源极电极SE还充当电容元件CAP的下部电极BE。
这样，与不同元件用作功率晶体管的源极电极和电容元件的下部电极的情形相比，可以简化半导体器件的结构。具体而言，作为不同元件用作功率晶体管的源极电极和电容元件的下部电极的例子，可以想到的情形如下：下部电极通过绝缘膜在源极电极之上形成，并且源极电极和下部电极通过穿过绝缘膜的插塞电连接。然而，在这样的情形下，连接源极电极和下部电极的结构变得复杂。而且，由于源极电极和下部电极是使用穿过绝缘膜的插塞电连接，可能会发生寄生电阻的增加。
就此而言，在高频噪声流入功率晶体管中存在的寄生电阻时，为了达到抑制在功率晶体管中产生噪声的目的，设置一个电容元件充当高频噪声旁路通路。
然而，源极电极和下部电极之间寄生电阻的产生意味着高频噪声的旁路通路中寄生电阻的增加。结果就是，即使高频噪声流过旁路通路，由于旁路通路中存在的寄生电阻，也会产生新的噪声。进一步地，旁路通路中寄生电阻的产生意味着旁路通路的阻抗增加，这也使得高频噪声难以流过旁路通路。也就是说，通过使高频噪声流过功率晶体管中存在的寄生电阻，抑制功率晶体管产生噪声。为了实现上述，即使当提供了充当高频噪声的旁路通路的电容元件来抑制功率晶体管中的噪声，如果旁路通路的阻抗由于该旁路通路中新产生的寄生电阻而增加，那么高频噪声也不太可能流入旁路通路。进一步地，即使高频噪声流入旁路通路，也可能由旁路通路中存在的新寄生电阻引起新噪声的产生。因此，根据上面描述的结构示例，难以完全展示出下述技术意义：出于抑制由于高频噪声流过功率晶体管中存在的寄生电阻所引起的功率晶体管中的噪声的目的，设置充当高频噪声的旁路通路的电容元件。
另一方面，根据第一实施方式的第二特征，与上面描述的结构示例不同，一个元件充当功率晶体管的源极电极SE和电容元件CAP的下部电极BE。即，功率晶体管的源极电极SE还充当电容元件CAP的下部电极BE。因此，根据第一实施方式的第二特征，由于源极电极SE和下部电极BE设置为单个部件，可以减小源极电极SE和下部电极BE之间的寄生电阻。因此，根据第一实施方式的第二特征，可以抑制旁路通路中由于源极电极SE和下部电极BE之间的寄生电阻而导致的阻抗的增加。因此，根据第一实施方式的第二特征，可以完全展示出下述技术意义：为了抑制由流入功率晶体管中存在的寄生电阻的高频噪声引起的功率晶体管中的噪声，设置充当高频噪声的旁路通路的电容元件。
进一步地，根据第一实施方式的第二特征，由于一个元件既充当功率晶体管的源极电极SE又充当电容元件CAP的下部电极BE，与源极电极和下部电极分别包括不同元件的情形相比，可以抑制半导体芯片CHP厚度的增加。
接下来，第一实施方式的第三特征如下。即，例如，如图2所示，漏极焊盘DP布置在形成功率晶体管和电容元件的有源区之外。进一步地，漏极焊盘DP和在同一层中形成的上部电极UE电连接。进一步地，第一实施方式的第三特征在于，例如，如图5所示，漏极焊盘DP和芯片安装部分TAB使用导线W3连接。因此，例如，如图5所示，电容元件的上部电极UE依次通过漏极焊盘DP、导线W3和芯片安装部分TAB与漏极电极DE电连接。
此时，根据第一实施方式的第三特征，例如，如图5所示，导线W3与布置在形成功率晶体管和电容元件的有源区之外的漏极焊盘DP连接。结果就是，在导线W3与漏极焊盘DP连接的接合工序中，可以抑制加到功率晶体管和电容元件上的冲击，改善了半导体器件的可靠性。也就是说，根据第一实施方式的第三特征，如图5所示，漏极焊盘DP在半导体衬底1S之上厚厚形成的电容绝缘膜CIL之上形成，并且功率晶体管和电容元件不是形成在漏极焊盘DP的下层中。结果就是，根据第一实施方式的第三特征，可以在不引起在有源区中形成的功率晶体管和电容元件的损坏的情况下，将导线W3与漏极焊盘DP连接。因此，根据第一实施方式的第三特征，可以在不降低半导体器件的可靠性的情况下，将电容元件的上部电极UE和功率晶体管的漏极电极DE进行电连接。
因此，通过包括上述第一特征、第二特征和第三特征，第一实施方式的半导体器件可以实现下述电路结构(参见图1B)：其中，电容元件CAP连接在功率晶体管的漏极电极DE和源极电极SE之间，同时该功率晶体管和电容元件CAP在半导体芯片CHP的厚度方向上以层压方式布置。并且，根据第一实施方式的半导体器件，即使添加了电容元件，也可以在不牺牲半导体器件微型化的情况下改善半导体器件的性能。换句话说，根据第一实施方式，可以在抑制半导体器件平面尺寸增加的情况下实现提供低噪声半导体器件的卓越效果。
<半导体器件的制造方法>
第一实施方式的半导体器件的结构如上所述。下文中，将参考附图说明其制造方法。
首先，如图6所示，例如，提供半导体衬底1S，该衬底含有硅作为主要成分并且包括：漂移层EP；以及沟道层CH，该沟道层在主表面侧上的漂移层EP之上形成。此时，漂移层EP包括引入诸如磷(P)和砷(As)之类的n型杂质的n型半导体层。而且，沟道层CH包括例如引入诸如硼(B)之类的p型杂质的p型半导体层。此外，半导体衬底1S包括至少一个功率半导体元件形成区域，在该区域中形成槽栅型功率MOSFET。而且，除了功率半导体元件形成区域之外，例如，半导体衬底1S可包括形成温度传感二极管等的区域。下文中，具体而言，主要关注形成槽栅型功率MOSFET的功率半导体元件形成区域，将说明根据第一实施方式的半导体器件的制造方法。
在本说明书中，“主要成分”意味着部件(衬底、层或膜)中包含最多的组成材料的材料成分。通过该表达，例如，“半导体衬底1S包括硅作为主要成分”，其意在表达半导体衬底1S的材料含有硅(Si)最多。在本说明书中，通过该术语，“主要成分”，意在表达，例如，半导体衬底1S总体上包括硅，但部件不应理解为排除其中含有的杂质。
而且，在图6中，半导体衬底1S、漂移层EP以及沟道层CH是分别显示。然而，在本说明书中，形成漂移层EP和沟道层CH的半导体衬底1S有时候作为整体称为“半导体衬底”。也就是说，当在本说明书中使用术语“半导体衬底”时，存在下述情形：一种情形是表示用于形成漂移层EP和沟道层CH的基底材料，以及一种情形是意味着基底材料整体上形成漂移层EP。
接下来，如图7所示，使用光刻技术和蚀刻技术，形成穿过沟道层CH并且到达漂移层EP的槽TR。随后，如图8所示，在每个槽TR的内壁之上形成栅极绝缘膜GOX。栅极绝缘膜GOX包括，例如，氧化硅膜，并且可以，例如，使用热氧化方法或CVD(化学气相淀积)方法形成。然而，栅极绝缘膜GOX不限于氧化硅膜。例如，它可包括介电常数高于氧化硅膜的介电常数的高介电常数膜。作为高介电常数膜，例如，可以使用氧化铪膜等。接着，通过栅极绝缘膜GOX，栅极电极GE形成为填充槽TR的内侧。栅极电极GE包括，例如，多晶硅膜，并且可以，例如，通过使用CVD方法形成。
随后，如图9所示，在沟道层CH的表面之上，例如，使用离子注入，通过引入诸如磷(P)和砷(As)之类的n型杂质形成与槽TR接触的源区SR。
接下来，在半导体衬底1S的主表面侧上涂覆抗蚀膜之后，通过执行曝光和显影工序，使抗蚀膜图案化。抗蚀膜图案化为形成仅允许形成体接触区域BC的区域敞开的开口。随后，通过使用图案化后的抗蚀膜作为掩膜进行离子注入，例如，诸如硼(B)之类的p型杂质通过所述开口引入源区SR的露出部分。结果就是，如图9所示，可以形成包括p型半导体区域的体接触区域BC。
接下来，在移除图案化的抗蚀膜之后，如图10所示，在半导体衬底1S的形成槽TR的主表面侧上形成绝缘膜IL1。绝缘膜IL1包括，例如，氧化硅膜，并且，例如，可以使用CVD方法形成。随后，如图11所示，通过光刻技术和蚀刻技术将绝缘膜IL1图案化。绝缘膜IL1图案化为覆盖栅极电极GE嵌入的槽TR的上部并且露出源区SR和体接触区域BC。
随后，如图12所示，在绝缘膜IL1之上(包括露出的源区SR之上和露出的体接触区域BC之上)形成铝膜。铝膜可以，例如，通过使用溅射法形成。随后，通过使用光刻技术和蚀刻技术将铝膜图案化，形成源极电极SE。
接下来，如图13所示，电容绝缘膜CIL在源极电极SE之上形成并且铝膜在电容绝缘膜CIL之上形成。此时，电容绝缘膜CIL包括，例如，氧化硅膜、氮化硅膜或者它们的层压膜，并且可以，例如，通过使用CVD方法形成。而且，铝膜可以，例如，通过使用溅射法形成。
随后，通过使用光刻技术和蚀刻技术，通过使所述铝膜图案化形成上部电极UE。接着，移走露出的电容绝缘膜CIL。从而，可以形成电容元件，在该电容元件中，源极电极用作下部电极并且该电容元件包括电容绝缘膜CIL和上部电极UE。接着，如图3所示，在半导体衬底1S的背表面之上形成漏极电极DE。
因此，可以制造如上所述的具有功率晶体管和电容元件的层压结构的第一实施的半导体器件。
在第一实施方式中，已经给出了源极电极SE和上部电极UE包括铝膜的情形的说明，但其不是限制性的。例如，源极电极SE和上部电极UE可包括由AlSi膜和AlSiCu膜所代表的铝合金膜、钨膜或钨合金膜。
在第一实施方式中，已经说明了通过图案化铝膜形成上部电极UE的情形，但其不是限制性的。例如，上部电极UE还可以通过，例如，使用重新布线的技术形成。也就是说，还可以通过在聚酰亚胺膜中形成开口并且使用电镀法在该开口内形成铜膜来形成包括铜膜的上部电极UE。在这样的情形下，由于在形成上部电极UE时不使用蚀刻技术，可以抑制对上部电极UE的蚀刻损坏。结果就是，根据重新布线技术，可以获得能够形成高可靠上部电极UE的优势。
<变形例1>
接下来，将说明根据变形例1的半导体器件PKG2的封装结构。图14是示出变形例1的半导体器件PKG2的封装结构的平面视图。在图14中，根据变形例1，上部电极UE(上部电极露出区域)使用导线W3与芯片安装部分TAB直接连接。结果就是，根据变形例1，半导体芯片CHP的平面尺寸可以缩减半导体芯片CHP之上省去的漏极焊盘那样多。即，根据变形例1的半导体器件PKG2的封装结构，可以促进半导体器件PKG2的微型化。
而且，在根据变形例1的半导体器件PKG2，如图14所示，不仅源极电极SE和源极引线SL使用多根导线W1连接，而且上部电极UE和芯片安装部分TAB也使用多根导线W3连接。结果就是，根据变形例1，并联的功率晶体管和电容元件的电荷移动变得容易，从可以完全展现电容元件作为高频噪声的旁路通路的功能。而且，通过使用导线W3连接上部电极UE和芯片安装部分TAB，可以减小旁路通路中的寄生电阻和寄生电感。结果就是，根据变形例1的半导体器件PKG2，可以抑制由漏极电极和上部电极UE之间的寄生电阻和寄生电感引起的旁路通路中阻抗的增加。因此，根据变形例1，可以抑制由流入旁路通路中存在的寄生电阻的高频噪声所引起的噪声的产生，并且抑制出现下述情况：由旁路通路中存在的寄生电感所引起的阻碍高频噪声流入旁路通路。因此，根据变形例1，可以完全展现出提供充当高频噪声的旁路通路的电容元件的技术意义。
<变形例2>
接下来，将说明根据变形例2的半导体器件PKG3的封装结构。图15是示出变形例2的半导体器件PKG3的封装结构的平面视图。在图15中，根据变形例2，体现了在抑制半导体芯片CHP的平面尺寸增加的同时使电容元件的上部电极UE的平面面积尽可能地增加的技术思想。更为具体而言，如图15所示，使上部电极UE的平面面积大得覆盖源极电极SE的除了与多根导线W1连接的区域之外的其他部分。例如，如图15所示，通过在上部电极UE的一部分形成凹的和凸的形状，可以尽可能地增加上部电极UE的平面面积以接近源极电极SE的平面面积，同时确保源极电极SE的与导线W1连接的区域。
因此，根据变形例2，源极电极SE和上部电极UE的正对面积可以制作得更大。结果就是，根据变形例2，可以增加设置在旁路通路中的电容元件的电容。这意味着，可以允许旁路通路对高频噪声而言为低阻抗状态。因此，根据变形例2，可以完全展现充当高频噪声的旁路通路的电容元件的技术意义。
<变形例3>
接下来，将说明根据变形例3的半导体器件PKG4的封装结构。图16是示出变形例3的半导体器件PKG4的封装结构的平面图。在图16中，根据变形例3，在半导体芯片CHP的表面之上形成漏极焊盘DP1和漏极焊盘DP2，漏极焊盘DP1和漏极焊盘DP2中的每一者与上部电极UE电连接。
因此，如同在变形例1中，在变形例3中同样可以抑制由于漏极电极和上部电极UE之间的寄生电阻和寄生电感所导致的旁路通路的阻抗增加。因此，在变形例3中，同样可以抑制下述两者的出现：由流入旁路通路中存在的寄生电阻的高频噪声引起的噪声，由旁路通路中存在的寄生电感引起的阻碍高频噪声流入旁路通路。结果就是，根据变形例3，同样可以完全展现设置充当高频噪声的旁路通路的电容元件的技术意义。具体而言，根据变形例3，采用这样的结构：漏极焊盘DP1和漏极焊盘DP2设置在形成功率晶体管和电容元件的有源区之外并且漏极焊盘DP1和漏极焊盘DP2中的每一者与上部电极UE连接。因此，根据变形例3，可以抑制在将导线W3与漏极焊盘DP1和漏极焊盘DP2中的每一者连接的接合步骤中对功率晶体管和电容元件的冲击的同时完全展现设置充当高频噪声的旁路通路的电容元件的技术意义。
第二实施方式
在上面描述的第一实施方式中，尽管已经说明了功率MOSFET作为功率晶体管的一种示例，但第一实施方式的技术思想并不限于此，而是还可以应用于IGBT(绝缘栅双极型晶体管)。
<IGBT的装置结构>
首先，将说明IGBT的装置结构。图17是示出根据第二实施方式的IGBT的装置结构的横截面视图。如图17中所示，IGBT具有在半导体芯片CHP的背表面之上形成的集电极CE(集电极焊盘)，并且在该集电极CE之上形成半导体衬底1S(在图17中，为p型半导体衬底)。在半导体衬底1S之上，形成p型半导体层PL，并且，在p型半导体层PL之上，形成漂移层EP。而且，在漂移层EP之上形成沟道层CH，并且，进一步地，形成穿过沟道层CH并且到达漂移层EP的槽TR。进一步地，形成包括n+型半导体区域的发射极区，匹配槽TR。在槽TR内侧，形成包括例如氧化硅膜的栅极绝缘膜GOX，并且通过该栅极绝缘膜GOX形成栅极电极GE。栅极电极GE包括，例如，多晶硅膜，并且形成为填充槽TR。进一步地，在沟道层CH的邻近发射极区ER的表面之上形成体接触区域BC。
接着，如图17所示，在发射极区ER和体接触区域BC之上，包括例如铝膜的发射极电极EE形成为与发射极区ER和体接触区域BC接触。结果就是，发射极区ER和体接触区域BC通过发射极电极EE电连接。也就是说，根据第二实施方式，如图17所示，发射极电极EE同样在从发射极区ER和体接触区域BC之上到栅极电极GE之上的范围内形成，并且绝缘膜IL1插置在发射极电极EE和栅极电极GE之间。结果就是，通过绝缘膜IL1，发射极电极EE与栅极电极GE电绝缘。
这样构造的IGBT具有功率晶体管的快速开关特性和电压驱动特性和双极型晶体管的低导通电压特性。
在图17中，示出了槽栅结构，但其不是限制性的。例如，尽管未示出，可以是使用在硅衬底之上形成平面栅结构的IGBT。
<IGBT的操作>
接下来，将说明第二实施方式中IGBT的操作。首先，将说明IGBT的导通操作。如图17所示，当在栅极电极GE和发射极区ER之间提供足够的正电压时，具有槽结构的MOSFET导通。在这样的情形下，提供了作为集电极区域的p型半导体层PL和漂移层EP之间的正向偏压，开始了从p型半导体层PL向漂移层EP的空穴注入。随后，与注入的空穴的正电荷一样多的电子聚集在漂移层EP。结果就是，漂移层EP的电阻下降(电导率调制)并且IGBT将导通。
p型半导体层PL和漂移层EP的结电压添加至通态电压。然而，由于电导率调制，漂移层EP的电阻值降低一个位数或更多。因此，在占据导通电阻大部分的高介电强度下，IGBT是低通态电压，而功率MOSFET不是。因此，可以看出，IGBT是对实现高介电强度有效的设备。即，在功率MOSFET中，为了实现高介电强度，需要将用作漂移层的外延层加厚。在这样的情形下，导通电阻也会升高。另一方面，在IGBT中，即使为了实现高介电强度而加厚漂移层EP，在IGBT的导通操作时会产生电导率调制。基于该原因，使得导通电阻低于功率MOSFET的情形。也就是说，根据该IGBT，与功率MOSFET相比，即使当试图实现高介电强度时，也可实现低导通电阻设备。
接下来，将说明IGBT的断开操作。当栅极电极GE和发射极区ER之间的电压减小时，具有槽栅结构的MOSFET断开。在这样的情形下，从p型半导体层PL向漂移层EP的空穴注入停止。进一步地，已经注入的空穴寿命耗尽并且数量减少。剩余的空穴已直接流入发射极电极EE侧(尾电流)。当流动完成之后，IGBT处于断开状态，可以导通/断开IGBT。
<第二实施方式的特征>
如上所述，作为功率晶体管的一种示例的IGBT形成在第二实施方式的半导体芯片中。同样，在第二实施方式中电容元件CAP在半导体芯片的厚度方向上以层压的方式布置在IGBT之上。
更为具体而言，如图17所示，电容绝缘膜CIL在IGBT的发射极电极EE之上形成，并且，在电容绝缘膜CIL之上，形成上部电极UE。
结果就是，在根据第二实施方式的半导体芯片CHP中，形成了下述的电容元件CAP，该电容元件CAP使用发射极电极EE作为下部电极并且包括在下部电极之上形成的电容绝缘膜CIL以及在电容绝缘膜CIL之上形成的上部电极UE。也就是说，在根据第二实施方式的半导体芯片CHP中，同样地，在IGBT的上部形成了使用发射极电极EE还充当下部电极的电容元件CAP。也就是说，在第二实施方式的半导体芯片CHP中，在采用了将IGBT的发射极电极EE还充当电容元件CAP的下部电极的结构的同时，在半导体芯片CHP的厚度方向上，将IGBT和电容元件以层压方式布置。
电容元件CAP的上部电极UE与IGBT的集电极CE电连接。因此，在第二实施方式的半导体芯片CHP中，形成了体现图1B所示电路结构的装置结构(IGBT和电容元件CAP)。
因此，第二实施方式同样具有像第一实施方式一样的上面所述的第一特征、第二特征和第三特征。结果就是，同样，在第二实施方式中，在将IGBT和电容元件CAP在半导体芯片CHP的厚度方向上以层压方式布置的同时，可以获得电容元件CAP连接在IGBT的集电极CE和发射极电极EE之间的电路结构。进一步地，根据第二实施方式的半导体器件，即使增加了电容元件，也可以实现在不牺牲半导体器件的微型化的情况下改善半导体器件的性能。也就是说，根据第二实施方式，可以获得在抑制半导体器件平面尺寸增加的同时提供低噪声半导体器件的突出效果。
尽管已经参考优选实施方式具体描述了本发明的发明人作出的发明，明显本发明并不限于所述实施方式，而是可以在不脱离其实质的范围内进行各种不同的变形。
尽管已经对上面所述的实施方式中作为功率晶体管的示例的功率MOSFET和IGBT进行了说明，但上述实施方式的技术思想并不限于此，而是还可广泛应用于使电流在半导体芯片的厚度方向流动的所谓的立式器件。例如，它还可应用于通过控制从栅极电极延伸的耗尽层的宽度来控制电流的导通和断开的结型FET。
在第二实施方式中，已经描述了含有硅(Si)作为主要材料的功率晶体管。然而，第二实施方式的技术思想并不限于上述的那些。例如，它可应用于主要含有以碳化硅(SiC)和氮化镓(GaN)为代表的带隙比硅的带隙大的材料(宽带隙材料)的功率晶体管。然而，在主要含有氮化镓(GaN)的功率晶体管中，一般采用平面型器件，该平面型器件使用在沟道层(电子渡越层)(例如，GaN)和电子供给层(例如，AlGaN)的界面产生的阱型电势中局部存在的二维电子气(2DEG)。基于该原因，应用于立式器件的第二实施方式的技术思想在应用于含有硅(Si)或碳化硅(SiC)作为主要材料的立式器件时尤其有效。

Claims (15)

1.一种半导体器件，包括：
半导体芯片，所述半导体芯片具有有源区域以及与所述有源区域间隔开的漏极焊盘，在所述有源区域上形成有功率晶体管和与该功率晶体管电连接的电容元件，
其中，所述功率晶体管包括：
源极电极和漏极电极，该源极电极和该漏极电极在所述半导体芯片的厚度方向上彼此间隔开；以及
栅极电极，该栅极电极控制导通/断开所述漏极电极和所述源极电极之间流动的电流，
其中，所述电容元件包括：
所述源极电极作为下部电极；
电容绝缘膜，该电容绝缘膜在所述源极电极之上形成；以及
上部电极，该上部电极在所述电容绝缘膜之上形成并且经由所述漏极焊盘与所述漏极电极电连接，以及
其中，在平面视图中，所述源极电极和所述上部电极具有重叠部分。
2.根据权利要求1所述的半导体器件，其中，在平面视图中，所述上部电极包含在所述源极电极中。
3.根据权利要求1所述的半导体器件，其中，所述功率晶体管和所述电容元件在所述半导体芯片的厚度方向上以层压方式布置。
4.根据权利要求1所述的半导体器件，其中，所述功率晶体管包括：
半导体衬底，所述漏极电极在所述半导体衬底的背表面之上形成；
漂移层，该漂移层在所述半导体衬底的主表面之上形成；
沟道层，该沟道层在所述漂移层之上形成；
槽，该槽穿过所述沟道层并且到达所述漂移层；
栅极绝缘膜，该栅极绝缘膜在所述槽的内壁之上形成，栅极电极通过所述栅极绝缘膜嵌入所述槽；
源区，该源区与所述槽接触并且在所述沟道层的表面之上形成，以及所述源极电极与所述源区电连接。
5.根据权利要求4所述的半导体器件，
其中，所述源极电极形成在从所述源区之上到所述栅极电极之上的范围内，以及
其中，在所述源极电极和所述栅极电极之间插置有绝缘膜。
6.根据权利要求1所述的半导体器件，包括：
芯片安装部分；并且
所述半导体芯片安装在所述芯片安装部分之上，
其中，所述漏极电极在所述半导体芯片的背表面之上形成，
其中，与所述栅极电极电连接的栅极焊盘、所述源极电极和所述上部电极在所述半导体芯片的主表面之上形成，以及
其中，在平面视图中，在所述半导体芯片的主表面之上，形成露出所述上部电极的上部电极露出区域和露出所述源极电极的源极电极露出区域，并且，还露出所述栅极焊盘。
7.根据权利要求6所述的半导体器件，包括：
漏极引线，该漏极引线与所述芯片安装部分连接；
源极引线，该源极引线与所述芯片安装部分间隔开；以及
栅极引线，该栅极引线与所述芯片安装部分间隔开。
8.根据权利要求7所述的半导体器件，
其中，所述源极电极露出区域和所述源极引线通过第一导电部件连接，
其中，所述栅极焊盘和所述栅极引线通过第二导电部件连接，以及
其中，所述漏极焊盘和所述芯片安装部分通过第三导电部件连接。
9.根据权利要求8所述的半导体器件，
其中，所述源极电极露出区域和所述源极引线通过多个第一导电部件连接，以及
其中，所述漏极焊盘和所述芯片安装部分通过多个第三导电部件连接。
10.根据权利要求7所述的半导体器件，
其中，所述源极电极露出区域和所述源极引线通过第一导电部件连接，
其中，所述栅极焊盘和所述栅极引线通过第二导电部件连接，
其中，与所述上部电极电连接的漏极焊盘在所述半导体芯片的表面之上露出，以及
其中，所述漏极焊盘和所述芯片安装部分通过第三导电部件连接。
11.根据权利要求10所述的半导体器件，
其中，在所述半导体芯片的表面之上存在与所述上部电极电连接的多个漏极焊盘。
12.根据权利要求1所述的半导体器件，
其中，所述电容绝缘膜的膜厚度为大于或等于50nm且小于或等于250nm。
13.一种半导体器件，包括：
半导体芯片，所述半导体芯片具有有源区域以及与所述有源区域间隔开的集电极焊盘，在所述有源区域上形成有功率晶体管和与该功率晶体管电连接的电容元件，
其中，所述功率晶体管包括：
发射极电极和集电极电极，该发射极电极和该集电极电极在所述半导体芯片的厚度方向上彼此间隔开；以及
栅极电极，该栅极电极控制导通/断开在所述集电极电极和所述发射极电极之间流动的电流，
其中，所述电容元件包括：
所述发射极电极作为下部电极；
电容绝缘膜，该电容绝缘膜在所述发射极电极之上形成；以及
上部电极，该上部电极在所述电容绝缘膜之上形成并且经由所述集电极焊盘与所述集电极电极电连接，以及
其中，在平面视图中，所述发射极电极和所述上部电极具有重叠部分。
14.根据权利要求13所述的半导体器件，
其中，所述功率晶体管是绝缘栅双极型晶体管。
15.一种制造半导体器件的方法，该半导体器件包括半导体芯片，所述半导体芯片具有有源区域以及与所述有源区域间隔开的漏极焊盘，在所述有源区域上形成有功率晶体管和与该功率晶体管电连接的电容元件，
其中，所述功率晶体管包括：
源极电极和漏极电极，该源极电极和该漏极电极彼此间隔开；以及
栅极电极，该栅极电极控制导通/断开所述漏极电极和所述源极电极之间流动的电流，
其中，所述电容元件包括：
所述源极电极作为下部电极；
电容绝缘膜，该电容绝缘膜在所述源极电极之上形成；以及
上部电极，该上部电极在所述电容绝缘膜之上形成并且经由所述漏极焊盘与所述漏极电极电连接，并且
其中，在平面视图中，所述源极电极和所述上部电极具有重叠部分，
所述方法包括下述步骤：
(a)提供半导体衬底，该半导体衬底具有在该半导体衬底的表面之上形成的漂移层和在该漂移层之上形成的沟道层；
(b)形成穿过所述沟道层并且到达所述漂移层的槽；
(c)在所述槽的内壁之上形成栅极绝缘膜；
(d)形成通过所述栅极绝缘膜嵌入所述槽的栅极电极；
(e)在步骤(d)之后，在所述沟道层的表面之上形成源区以与所述槽接触；
(f)在步骤(e)之后，形成覆盖所述栅极电极的上表面的绝缘膜；
(g)在步骤(f)之后，形成与所述源区连接的所述源极电极；
(h)在所述源极电极之上形成所述电容绝缘膜；
(i)在所述电容绝缘膜之上形成所述上部电极；以及
(j)在所述半导体衬底的背表面之上形成所述漏极电极。
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