JP2009147103A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2009147103A JP2009147103A JP2007322808A JP2007322808A JP2009147103A JP 2009147103 A JP2009147103 A JP 2009147103A JP 2007322808 A JP2007322808 A JP 2007322808A JP 2007322808 A JP2007322808 A JP 2007322808A JP 2009147103 A JP2009147103 A JP 2009147103A
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Abstract
【解決手段】ウェッジツール12の底面は、V溝13によって第1分岐部12Aと第2分岐部12Bとに2分割されている。シリコンチップ3のソースパッド7とリードフレームのソースポスト4PにAlリボン10をボンディングするには、まず、ソースパッド7上のAlリボン10にウェッジツール12の第1分岐部12Aおよび第2分岐部12Bを圧接して超音波振動を印加し、次いで、ソースポスト4P上のAlリボン10に第1分岐部12Aを圧接して超音波振動を印加する。ここで、第1分岐部12Aの幅はソースポスト4Pの幅よりも狭いので、ソースポスト4Pの幅方向の端部表面にはAlリボン10が接合されない。
【選択図】図12
Description
前記ダイパッド部上に搭載された半導体チップと、
前記半導体チップの表面に形成された第1パッドと前記第1リードとを電気的に接続する金属リボンと、
前記半導体チップ、前記第1リードおよび前記金属リボンを封止する樹脂と、
を有し、
前記金属リボンは、前記第1パッドの表面の第1接合部と第2接合部とにおいて前記第1パッドに接続され、
前記第1接合部における前記金属リボンと前記第1パッドとの接続面積は、前記第2接合部における前記金属リボンと前記第1パッドとの接続面積と異なるものである。
(b)表面に第1パッドが形成された半導体チップを用意する工程と、
(c)前記ダイパッド部上に前記半導体チップを搭載する工程と、
(d)超音波振動を利用したウェッジボンディング法によって、前記第1パッドの表面に金属リボンの一端を電気的に接続し、前記第1リードの表面に前記金属リボンの他端を電気的に接続する工程と、
(e)前記半導体チップ、前記第1リードおよび前記金属リボンを樹脂により封止する工程と、
を有し、
前記(d)工程において、前記第1パッドおよび前記第1リードのそれぞれの表面上の前記金属リボンに前記超音波振動を印加するウェッジツールの先端部は、前記第1パッドから前記第1リードへ向かう方向と直交する第1方向に延在する長溝によって分岐されているものである。
本実施の形態の半導体装置は、小型面実装パッケージの一種である「SOP8」に適用したものである。図1は、本実施の形態のSOP8の外観を示す平面図、図2は、このSOP8の外観を示す側面図、図3は、このSOP8の内部構造を示す平面図、図4は、図3のA−A線に沿った断面図、図5は、図3のB−B線に沿った断面図である。
図18は、本実施の形態のSOP8の内部構造を示す平面図である。このSOP8の特徴は、ソースポスト4Pとソースパッド7が複数本のAlリボン10で接続されていることにある。Alリボン10の本数は3本以上であってもよいが、ここでは、2本のAlリボン10で接続された例を示している。
一般に、SOP8のような樹脂封止型半導体装置の製造工程では、図21に示すような、複数のダイパッド部4Dを設けたリードフレームが使用される。なお、ここでは、3個のダイパッド部4Dを設けたリードフレームLFを示している。
図24(a)は、本実施の形態のウェッジツールの先端部近傍を示す側面図、図24(b)は、このウェッジツールの先端部を下方から見た平面図である。
3 シリコンチップ
4 リード
4D ダイパッド部
4P ソースポスト
5 Agペースト
7 ソースパッド(ソース電極)
8 ゲートパッド
10 Alリボン
11 Auワイヤ
12 ウェッジツール
12A 第1分岐部
12B 第2分岐部
13 V溝(長溝)
14 リボンガイド
15 リボンカッター
16 U溝
17 四角溝
18 ウェッジツール
19D ダイパッド部
19S ソースリード
20 n+型単結晶シリコン基板
21 n−型単結晶シリコン層
22 p型ウエル
23 酸化シリコン膜
24 溝
25 酸化シリコン膜(ゲート酸化膜)
26A 多結晶シリコン膜(ゲート電極)
26B ゲート引き出し電極
27 p−型半導体領域
28 p型半導体領域
29 n+型半導体領域(ソース)
30、31 酸化シリコン膜
32、33 接続孔
34 ゲート配線
35 p+型半導体領域
36、37、38 Al配線
40 真空穴
LF リードフレーム
Claims (15)
- ダイパッド部および前記ダイパッド部の近傍に配置された第1リードを有するリードフレームと、
前記ダイパッド部上に搭載された半導体チップと、
前記半導体チップの表面に形成された第1パッドと前記第1リードとを電気的に接続する金属リボンと、
前記半導体チップ、前記第1リードおよび前記金属リボンを封止する樹脂と、
を有し、
前記金属リボンは、前記第1パッドの表面の第1接合部と第2接合部とにおいて前記第1パッドに接続され、
前記第1接合部における前記金属リボンと前記第1パッドとの接続面積は、前記第2接合部における前記金属リボンと前記第1パッドとの接続面積と異なることを特徴とする半導体装置。 - 前記第1接合部から前記第1リードまでの距離は、前記第2接合部から前記第1リードまでの距離よりも長く、前記第1接合部における前記金属リボンと前記第1パッドとの接続面積は、前記金属リボンと前記第1リードとの接続面積に等しいことを特徴とする請求項1記載の半導体装置。
- 前記半導体チップは、Agペーストを介して前記ダイパッド部に接合されていることを特徴とする請求項1記載の半導体装置。
- 前記半導体チップの表面には、前記第1パッドよりも面積が小さい第2パッドがさらに形成され、
前記リードフレームは、前記ダイパッド部の近傍に配置された第2リードをさらに有し、
前記第2パッドと前記第2リードは、Auワイヤを介して電気的に接続されていることを特徴とする請求項1記載の半導体装置。 - 前記金属リボンは、Alからなることを特徴とする請求項1記載の半導体装置。
- 前記第1リードは、前記樹脂の外部に露出した複数本のアウターリードと、前記樹脂の内部において前記複数本のアウターリードを連結する連結部とで構成され、
前記金属リボンは、前記連結部において前記第1リードに接続されていることを特徴とする請求項1記載の半導体装置。 - 前記半導体チップにはパワーMOSFETが形成され、前記第1パッドは、前記パワーMOSFETのソース電極を構成していることを特徴とする請求項1記載の半導体装置。
- (a)ダイパッド部および前記ダイパッド部の近傍に配置された第1リードを有するリードフレームを用意する工程と、
(b)表面に第1パッドが形成された半導体チップを用意する工程と、
(c)前記ダイパッド部上に前記半導体チップを搭載する工程と、
(d)超音波振動を利用したウェッジボンディング法によって、前記第1パッドの表面に金属リボンの一端を電気的に接続し、前記第1リードの表面に前記金属リボンの他端を電気的に接続する工程と、
(e)前記半導体チップ、前記第1リードおよび前記金属リボンを樹脂により封止する工程と、
を有する半導体装置の製造方法であって、
前記(d)工程において、前記第1パッドおよび前記第1リードのそれぞれの表面上の前記金属リボンに前記超音波振動を印加するウェッジツールの先端部は、前記第1パッドから前記第1リードへ向かう方向と直交する第1方向に延在する長溝によって分岐されていることを特徴とする半導体装置の製造方法。 - 前記第1リードは、前記樹脂の外部に露出した複数本のアウターリードと、前記樹脂の内部において前記複数本のアウターリードを連結する連結部とで構成され、
前記金属リボンの前記他端は、前記連結部において前記第1リードに接続されることを特徴とする請求項8記載の半導体装置の製造方法。 - 前記ウェッジツールの底面は、前記長溝を挟んで第1分岐部と第2分岐部とに2分割され、
前記第1方向における前記第1分岐部の幅は、前記第1方向における前記第1リードの幅よりも狭いことを特徴とする請求項8記載の半導体装置の製造方法。 - 前記(c)工程において、前記半導体チップは、Agペーストを介して前記ダイパッド部に接合されることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記半導体チップの表面には、前記第1パッドよりも面積が小さい第2パッドがさらに形成され、
前記リードフレームは、前記ダイパッド部の近傍に配置された第2リードをさらに有し、
前記(d)工程の後、前記(e)工程に先立って、前記第2パッドの表面にAuワイヤの一端を電気的に接続し、前記第2リードの表面に前記Auワイヤの他端を電気的に接続する工程をさらに有することを特徴とする請求項8記載の半導体装置の製造方法。 - 前記金属リボンは、Alからなることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記半導体チップにはパワーMOSFETが形成され、前記第1パッドは、前記パワーMOSFETのソース電極を構成していることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記ウェッジツールは、前記長溝の内部を減圧するための機構を備えていることを特徴とする請求項8記載の半導体装置の製造方法。
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JPWO2020255663A1 (ja) * | 2019-06-20 | 2020-12-24 | ||
JP7451521B2 (ja) | 2019-06-20 | 2024-03-18 | ローム株式会社 | 半導体装置及び半導体装置の製造方法 |
US12062634B2 (en) | 2019-06-20 | 2024-08-13 | Rohm Co., Ltd. | Semiconductor device and production method for semiconductor device |
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