CN101009221A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN101009221A
CN101009221A CNA200610063646XA CN200610063646A CN101009221A CN 101009221 A CN101009221 A CN 101009221A CN A200610063646X A CNA200610063646X A CN A200610063646XA CN 200610063646 A CN200610063646 A CN 200610063646A CN 101009221 A CN101009221 A CN 101009221A
Authority
CN
China
Prior art keywords
metal level
semiconductor wafer
metal
manufacture method
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200610063646XA
Other languages
English (en)
Other versions
CN100524632C (zh
Inventor
松村民雄
辻野忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN101009221A publication Critical patent/CN101009221A/zh
Application granted granted Critical
Publication of CN100524632C publication Critical patent/CN100524632C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/27505—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明的目的是提供可降低由热处理半导体晶片导致的半导体晶片的翘曲量的半导体装置的制造方法。具有背面电极的半导体装置的制造方法，包含：准备具有表面和背面的半导体晶片的工序；在该半导体晶片的背面形成第1金属层，通过热处理在该半导体晶片和该第1金属层之间形成欧姆连接的热处理工序；在该热处理工序后，在该半导体基板的背面上形成Ni组成的第2金属层的工序。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法，具体地说，涉及绝缘栅双极型晶体管等的功率半导体装置的制造方法。
背景技术
图4、5是传统的半导体装置的制造工序，是研磨半导体晶片的背面，形成背面金属的工序。图4是半导体晶片1的顶视图，图5(a)～(d)是从IV-IV方向观察图4时的截面图。图5所示传统的制造工序包含以下的工序1～4。
工序1：如图4及图5(a)所示，在硅等的半导体晶片1上，形成半导体元件2。半导体晶片1的膜厚为t1(研磨前)。
工序2：如图5(b)所示，为了降低半导体元件2的电阻，从背面研磨半导体晶片1，膜厚为t2(研磨后)。
工序3：如图5(c)所示，在半导体晶片1的背面形成例如由Al或Al-Si合金组成的第1金属层3。接着，用蒸镀法和溅射法依次形成由例如Ti、Mo或V组成的金属阻挡层4、由例如Ni组成的第2金属层5、由例如Au、Ag或Au-Ag合金组成的第3金属层6。
工序4：将在背面上形成4层金属膜的半导体晶片1放入保持为300℃～470℃左右的炉中进行烧结。从而，在半导体晶片1和第1金属层之间产生相互扩散，可获得良好的欧姆连接。
[专利文献1]特开平04-072764号公报
发明内容
但是，如图5(d)所示，半导体晶片1在烧结处理后产生背面侧膨胀而弯曲的问题。
图6表示在6英寸的硅晶片的背面形成200nm的第1金属层(Al)3、100nm的金属阻挡层(Ti)4、500nm的第2金属层(Ni)5以及200nm的第3金属层(Au)6时硅晶片的厚度和翘曲量的关系。图6中，「●」是烧结前， 「□」是烧结后。
例如，硅晶片的厚度为200μm时烧结后的翘曲量X为1.7mm，厚度为130μm时翘曲量X为3.8mm，厚度为60μm时翘曲量X为16mm。
这样的半导体晶片1的翘曲在传送半导体晶片1时，成为半导体晶片1卡在装置的内部而导致传送故障和处理中断的原因。另外，将切断为芯片状的半导体晶片1焊接到基板等时，成为焊接不充分、连接不良的原因。
发明人对此进行锐意研究，结果发现，Ni组成的第2金属层5通过热处理，其膜质等产生变化，对半导体晶片1的翘曲产生影响，从而完成了本发明。
即，本发明的目的是提供可降低由热处理导致的半导体晶片的翘曲量的半导体装置的制造方法。
本发明的半导体装置的制造方法，是具有背面电极的半导体装置的制造方法，其特征在于，包含：准备具备表面和背面的半导体晶片的工序；在该半导体晶片的背面形成第1金属层，通过热处理在该半导体晶片和该第1金属层之间形成欧姆连接的热处理工序；在该热处理工序后，在该半导体基板的背面上形成Ni组成的第2金属层的工序。
如上所述，通过采用本发明的半导体装置的制造方法，可降低半导体晶片的翘曲量，可防止半导体晶片的传送故障等。另外，可进行良好的芯片焊接。
附图说明
图1是本发明实施例1的半导体装置的制造工序的截面图。
图2是本发明实施例2的半导体装置的制造工序的截面图。
图3是本发明实施例3的半导体装置的制造工序的截面图。
图4是传统的半导体装置的顶视图。
图5是传统的半导体装置的制造工序的截面图。
图6表示传统的制造方法制作的半导体装置的晶片厚和翘曲量的关系。
符号说明
1半导体晶片  2半导体元件  3第1金属层  4、7金属阻挡层
5第2金属层   6第3金属层   100半导体装置
具体实施方式
实施例1
图1是全体用100表示的本实施例1的半导体装置的制造工序的截面图。图1是从与图4的IV-IV方向相同的方向观察半导体装置100时的截面图。该制造方法包含以下的工序1～5。
工序1：如图1(a)所示，在硅等的半导体晶片1上，形成绝缘栅双极型晶体管(IGBT)等的半导体元件2。半导体晶片1的膜厚为t1(研磨前)
工序2：如图1(b)所示，为了降低半导体元件2的电阻，从背面研磨半导体晶片1，膜厚为t2(研磨后)。
工序3：如图1(c)所示，在半导体晶片1的背面，形成由例如Al或Al-Si合金组成的第1金属层3。第1金属层3通过例如蒸镀法或溅射法形成。
另外，在半导体晶片1的背面上形成第1金属层3的工序之前，也可从半导体晶片1的背面注入B或As等的离子，通过加热进行注入离子的激活。
工序4：将半导体晶片1放入保持在300℃～470℃左右的炉中进行热处理(烧结)。从而，在半导体晶片1和第1金属层3之间产生相互扩散，可获得良好的欧姆连接。如图1(d)所示，该热处理工序中，半导体晶片1几乎不翘曲。
工序5：如图1(e)所示，用蒸镀法和溅射法依次形成由例如Ti、Mo或V组成的金属阻挡层4、由例如Ni组成的第2金属层5、由例如Au、Ag或Au-Ag合金组成的第3金属层6。这些金属层形成后不进行热处理。
这里，第2金属层5是为了使焊接时的焊接良好而形成的，另外，第3金属层6是为了防止第2金属层5的氧化而形成的。
例如，将直径6英寸、膜厚t2为60μm的硅晶片用作半导体晶片1时，形成膜厚200nm的第1金属层3，热处理后的翘曲量X在1mm以下。
而且，膜厚100nm的金属阻挡层4、膜厚500nm的第2金属层5、膜厚200nm的第3金属层6形成后的翘曲量X在2mm以下。
这样，在由例如Ni组成的第2金属层5形成后不进行热处理(烧结)工序，可降低半导体晶片1的翘曲。即，不对第2金属层5进行例如300℃以上高温的热处理，可降低半导体晶片1的翘曲。
其结果，采用本实施例1的制造方法，通过热处理可获得良好的欧姆连接并可降低半导体晶片的翘曲。
另外，工序5中，最好形成第2金属层5、第3金属层6时的半导体晶片1的基板温度设为80℃以下。通过在80℃以下的低温形成第2金属层5、第3金属层6，可进一步降低半导体晶片1的翘曲量X到1mm以下。
实施例2
图2是全体用200表示的本实施例2的半导体装置的制造工序的截面图。图2是从与图4的IV-IV方向相同的方向观察半导体装置200时的截面图，图2中，与图1相同的符号表示相同或相应部位。该制造方法包含以下的工序1～5。
工序1、2：图2(a)及(b)所示的工序1、2与上述的实施例1的工序1、2同样。
工序3：如图2(c)所示，在半导体晶片1的背面，形成由例如Al或Al-Si合金组成的第1金属层3、由例如Ti、Mo或V组成的金属阻挡层。第1金属层3、金属阻挡层4通过例如蒸镀法或溅射法形成。
另外，在半导体晶片1的背面上形成第1金属层3的工序之前，也可从半导体晶片1的背面注入B或As等的离子，通过加热进行注入离子的激活。
工序4：将半导体晶片1放入保持在300℃～470℃左右的炉中进行热处理(烧结)。从而，在半导体晶片1和第1金属层3之间产生相互扩散，可获得良好的欧姆连接。如图2(d)所示，在该热处理工序中，半导体晶片1几乎不翘曲。
工序5：如图2(e)所示，用蒸镀法或溅射法依次形成由例如Ni组成的第2金属层5、由例如Au、Ag或Au-Ag合金组成的第3金属层6。这些金属层形成后不进行热处理。
例如，将直径6英寸、膜厚t2为60μm的硅晶片用作半导体晶片1时，形成膜厚200nm的第1金属层3及膜厚100nm的金属阻挡层4，热处理后的翘曲量X在1mm以下。
而且，膜厚500nm的第2金属层5和膜厚200nm的第3金属层6形成后的翘曲量X在2mm以下。
这样，在例如由Ni组成的第2金属层5形成后不进行热处理(烧结)工序，可降低半导体晶片1的翘曲。从而，采用本实施例2的制造方法，通过热处理可获得良好的欧姆连接并可降低半导体晶片的翘曲。
特别地，采用本实施例2的方法时，可提高第1金属层3和金属阻挡层4的密合性。
另外，工序5中，在第2金属层5、第3金属层6形成时的半导体晶片1的温度最好在80℃以下。通过在80℃以下的低温形成第2金属层5、第3金属层6，可进一步降低半导体晶片1的翘曲量X到1mm以下。
实施例3
图3是全体用300表示的本实施例3的半导体装置的制造工序的截面图。图3是从与图4的IV-IV方向相同的方向观察半导体装置300时的截面图，图3中，与图1相同的符号表示相同或相应部位。该制造方法包含以下的工序1～5。
工序1～4：图3(a)～(d)所示工序1～4与上述实施例2的工序1～4相同。
工序5：如图3(e)所示，还形成由例如Ti、Mo或V组成与金属阻挡层4相同材料的金属阻挡层7。烧结后，通过形成与金属阻挡层4相同材料的金属阻挡层7，可提高与金属阻挡膜7和其上形成的第2金属层5的密合性。然后，用蒸镀法或溅射法依次形成由例如Ni组成的第2金属层5、由例如Au、Ag或Au-Ag合金组成的第3金属层6。这些金属阻挡层7或金属层5、6形成后不进行热处理。
例如，将直径6英寸、膜厚t2为60μm的硅晶片用作半导体晶片1时，形成膜厚200nm的第1金属层3及膜厚100nm的金属阻挡层4，热处理后的翘曲量X在1mm以下。
而且，金属阻挡层7、膜厚500nm的第2金属层5、膜厚200nm的第3金属层6形成后的翘曲量X在2mm以下。
这样，在由例如Ni组成的第2金属层5形成后不进行热处理(烧结)工序，可降低半导体晶片1的翘曲。从而，采用本实施例3的制造方法，通过热处理可获得良好的欧姆连接并可降低半导体晶片的翘曲。
另外，工序5中，在金属阻挡层7、第2金属层5、第3金属层6形成时的半导体晶片1的温度最好在80℃以下。通过在80℃以下的低温形成金属阻挡层7、第2金属层5、第3金属层6，可进一步降低半导体晶片1的翘曲量X到1mm以下。

Claims (7)

1.一种半导体装置的制造方法，是具有背面电极的半导体装置的制造方法，其特征在于，包含：
准备具备表面和背面的半导体晶片的工序；
在该半导体晶片的背面形成第1金属层，通过热处理在该半导体晶片和该第1金属层之间形成欧姆连接的热处理工序；
在该热处理工序后，在该半导体基板的背面上形成Ni组成的第2金属层的工序。
2.权利要求1所述的制造方法，其特征在于，
上述热处理工序后，形成金属阻挡层，并在其上形成上述第2金属层。
3.权利要求1所述的制造方法，其特征在于，
在上述第1金属层上形成金属阻挡层，进行热处理工序后，在该金属阻挡层上形成上述第2金属层。
4.权利要求1所述的制造方法，其特征在于，
在上述第1金属层上形成金属阻挡层，进行热处理工序后，在该金属阻挡层上再追加形成该金属阻挡层，并在其上形成上述第2金属层。
5.权利要求1～4的任一项所述的制造方法，其特征在于，
上述第1金属层由从Al及Al-Si合金组成的组中选择的材料组成。
6.权利要求1～4的任一项所述的制造方法，其特征在于，
上述热处理工序后的工序，将上述半导体晶片的温度维持在比该热处理工序低的温度下进行。
7.权利要求6所述的制造方法，其特征在于，
上述半导体晶片的温度在80℃以下。
CNB200610063646XA 2006-01-23 2006-12-29 半导体装置的制造方法 Active CN100524632C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006013349A JP2007194514A (ja) 2006-01-23 2006-01-23 半導体装置の製造方法
JP2006013349 2006-01-23

Publications (2)

Publication Number Publication Date
CN101009221A true CN101009221A (zh) 2007-08-01
CN100524632C CN100524632C (zh) 2009-08-05

Family

ID=38282344

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200610063646XA Active CN100524632C (zh) 2006-01-23 2006-12-29 半导体装置的制造方法

Country Status (7)

Country Link
US (1) US8183144B2 (zh)
JP (1) JP2007194514A (zh)
KR (1) KR100823648B1 (zh)
CN (1) CN100524632C (zh)
AT (1) AT503190B1 (zh)
DE (1) DE102006062029B4 (zh)
TW (1) TW200737382A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222623A (zh) * 2010-04-14 2011-10-19 富士电机株式会社 半导体装置的制造方法
CN108352298A (zh) * 2015-11-09 2018-07-31 应用材料公司 底部处理

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4221012B2 (ja) * 2006-06-12 2009-02-12 トヨタ自動車株式会社 半導体装置とその製造方法
WO2009141740A2 (en) * 2008-05-23 2009-11-26 Florian Bieck Semiconductor wafer and method for producing the same
JP2010021171A (ja) * 2008-07-08 2010-01-28 Renesas Technology Corp 半導体装置の製造方法およびそれに用いる半導体製造装置
WO2010109572A1 (ja) * 2009-03-23 2010-09-30 トヨタ自動車株式会社 半導体装置
JP2012248572A (ja) * 2011-05-25 2012-12-13 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
CN103748689B (zh) * 2011-09-08 2017-02-15 富士电机株式会社 半导体装置以及半导体装置的制造方法
JP6289104B2 (ja) * 2014-01-08 2018-03-07 日東電工株式会社 フィルム状接着剤、フィルム状接着剤付きダイシングテープ、半導体装置の製造方法、及び半導体装置
JP2023073724A (ja) * 2021-11-16 2023-05-26 株式会社フルヤ金属 半導体デバイス及びそれに用いる酸化防止用金属材料並びに該金属材料のスパッタリングターゲット及び蒸着源

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1149606A (en) 1967-02-27 1969-04-23 Motorola Inc Mounting for a semiconductor wafer which is resistant to fatigue caused by thermal stresses
JPS5950090B2 (ja) * 1977-07-07 1984-12-06 三菱電機株式会社 半導体装置の製造方法
JPS55111140A (en) * 1979-02-20 1980-08-27 Nec Corp Metalizing method for back surface of silicon wafer
JPS58106825A (ja) * 1981-12-18 1983-06-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
DE3301666A1 (de) 1983-01-20 1984-07-26 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung einer mehrschichtigen kontaktmetallisierung
DD277602A3 (de) 1987-12-21 1990-04-11 Akad Wissenschaften Ddr Verfahren zur Herstellung eines weichlötfähigen Mehrschichtkontaktsystems für Halbleiterbauelemente
DE3823347A1 (de) 1988-07-09 1990-01-11 Semikron Elektronik Gmbh Leistungs-halbleiterelement
US5342793A (en) * 1990-02-20 1994-08-30 Sgs-Thomson Microelectronics, S.R.L. Process for obtaining multi-layer metallization of the back of a semiconductor substrate
JPH0472764A (ja) 1990-07-13 1992-03-06 Sharp Corp 半導体装置の裏面電極
DE69223868T2 (de) 1991-07-17 1998-09-03 Denso Corp Verfahren zur Herstellung von Elektroden eines Halbleiterbauelements
JP3127494B2 (ja) * 1991-07-17 2001-01-22 株式会社デンソー 半導体装置の電極形成方法
KR930017092A (ko) * 1992-01-15 1993-08-30 김광호 반도체장치 및 그 제조방법
JPH0637301A (ja) * 1992-07-20 1994-02-10 Toyota Motor Corp 半導体装置及びその製造方法
US5924002A (en) * 1994-12-22 1999-07-13 Sony Corporation Method of manufacturing a semiconductor device having ohmic electrode
DE19527209A1 (de) * 1995-07-27 1997-01-30 Philips Patentverwaltung Halbleitervorrichtung
US6140703A (en) * 1996-08-05 2000-10-31 Motorola, Inc. Semiconductor metallization structure
DE19734434C1 (de) 1997-08-08 1998-12-10 Siemens Ag Halbleiterkörper mit Rückseitenmetallisierung und Verfahren zu deren Herstellung
KR100365436B1 (ko) * 1998-12-15 2003-04-10 주식회사 하이닉스반도체 반도체장치의배리어층형성방법
JP3960739B2 (ja) 2000-07-11 2007-08-15 シャープ株式会社 半導体装置とその製造方法
KR100724143B1 (ko) * 2001-01-17 2007-06-04 매그나칩 반도체 유한회사 반도체장치의 배리어층 형성방법
JP2003059860A (ja) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp 半導体装置
JP2003282845A (ja) * 2002-03-20 2003-10-03 Mitsubishi Electric Corp 炭化ケイ素基板の製造方法およびその製造方法により製造された炭化ケイ素基板、ならびに、ショットキーバリアダイオードおよび炭化ケイ素薄膜の製造方法
JP2003338620A (ja) * 2002-05-22 2003-11-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN100454492C (zh) 2002-06-13 2009-01-21 衡阳科晶微电子有限公司 共晶焊背面金属化工艺
JP2004153081A (ja) * 2002-10-31 2004-05-27 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハ及びｓｏｉウエーハの製造方法
KR100477396B1 (ko) * 2002-09-04 2005-03-28 한국전기연구원 금속 게이트 전극을 갖는 탄화규소 모스펫 소자 및 그제조방법
JP4693411B2 (ja) * 2002-10-30 2011-06-01 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI247576B (en) * 2003-03-28 2006-01-11 Hon Hai Prec Ind Co Ltd Method of manufacturing electromagnetic interference shield
JP4049035B2 (ja) * 2003-06-27 2008-02-20 株式会社デンソー 半導体装置の製造方法
JP3767585B2 (ja) 2003-07-11 2006-04-19 株式会社デンソー 半導体装置
US7214620B2 (en) * 2003-10-28 2007-05-08 Samsung Electronics Co., Ltd. Methods of forming silicide films with metal films in semiconductor devices and contacts including the same
JP4792694B2 (ja) * 2003-11-13 2011-10-12 セイコーエプソン株式会社 電気光学装置用基板の製造方法、電気光学装置用基板、電気光学装置、電子機器
US20050268963A1 (en) * 2004-02-24 2005-12-08 David Jordan Process for manufacturing photovoltaic cells
JP4788390B2 (ja) * 2005-06-07 2011-10-05 株式会社デンソー 半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222623A (zh) * 2010-04-14 2011-10-19 富士电机株式会社 半导体装置的制造方法
CN102222623B (zh) * 2010-04-14 2015-12-02 富士电机株式会社 半导体装置的制造方法
CN108352298A (zh) * 2015-11-09 2018-07-31 应用材料公司 底部处理
TWI729498B (zh) * 2015-11-09 2021-06-01 美商應用材料股份有限公司 基板處理方法
CN108352298B (zh) * 2015-11-09 2023-04-18 应用材料公司 底部处理

Also Published As

Publication number Publication date
AT503190B1 (de) 2010-03-15
TW200737382A (en) 2007-10-01
CN100524632C (zh) 2009-08-05
KR20070077450A (ko) 2007-07-26
US8183144B2 (en) 2012-05-22
AT503190A2 (de) 2007-08-15
AT503190A3 (de) 2008-05-15
JP2007194514A (ja) 2007-08-02
DE102006062029B4 (de) 2010-04-08
US20070173045A1 (en) 2007-07-26
KR100823648B1 (ko) 2008-04-21
DE102006062029A1 (de) 2007-08-09

Similar Documents

Publication Publication Date Title
CN100524632C (zh) 半导体装置的制造方法
CN107017152B (zh) 复合晶片及其制造方法
WO2008053627A1 (en) OHMIC ELECTRODE FOR SiC SEMICONDUCTOR, METHOD FOR MANUFACTURE OF OHMIC ELECTRODE FOR SiC SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURE OF SEMICONDUCTOR DEVICE
CN105518829B (zh) 半导体装置的制造方法
CN104303269A (zh) 碳化硅半导体装置的制造方法
CN105518830A (zh) 半导体装置的制造方法
TW202205368A (zh) 氮化鎵/鑽石晶圓
JP2019125802A (ja) ガリウム窒化物電界効果トランジスタ
CN100524860C (zh) 半导体元件及其制造方法
CN101589466B (zh) 电子元件
JP7283053B2 (ja) 炭化珪素半導体装置、炭化珪素半導体組立体および炭化珪素半導体装置の製造方法
CN217239466U (zh) 垂直传导半导体器件
CN102254936A (zh) 化合物半导体装置以及制造该化合物半导体装置的方法
JP2009272449A (ja) 半導体装置の製造方法
CN115552634A (zh) 半导体装置以及其制造方法
JP5375497B2 (ja) 半導体装置、及び、半導体装置の製造方法
JP2005026612A (ja) 半導体装置
KR19990057898A (ko) 반도체 소자의 장벽금속막 형성 방법
JPH07297380A (ja) 配線の接続構造及びその製造方法
JP2006156910A (ja) 半導体装置
JPS586172A (ja) 半導体装置
JP5303008B2 (ja) 半導体素子及び半導体素子の製造方法
JPS6360526A (ja) 半導体装置の製造方法
KR20050039166A (ko) 반도체 소자의 게이트 전극 및 그 형성방법
JPH0119251B2 (zh)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant