CN108352298B - 底部处理 - Google Patents

底部处理 Download PDF

Info

Publication number
CN108352298B
CN108352298B CN201680064396.3A CN201680064396A CN108352298B CN 108352298 B CN108352298 B CN 108352298B CN 201680064396 A CN201680064396 A CN 201680064396A CN 108352298 B CN108352298 B CN 108352298B
Authority
CN
China
Prior art keywords
substrate
backside
film
strain
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680064396.3A
Other languages
English (en)
Other versions
CN108352298A (zh
Inventor
约瑟夫·M·拉内什
阿伦·缪尔·亨特
斯瓦米纳坦·T·斯里尼瓦桑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to CN202310350135.XA priority Critical patent/CN116435172A/zh
Priority to CN202211543021.9A priority patent/CN116435167A/zh
Publication of CN108352298A publication Critical patent/CN108352298A/zh
Application granted granted Critical
Publication of CN108352298B publication Critical patent/CN108352298B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32899—Multiple chambers, e.g. cluster tools
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02354—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light using a coherent radiation, e.g. a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68792—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

本文所公开的实施方式一般地涉及用于处理基板的底表面以抵消基板上的热应力的方法及装置。可将校正应变施加至基板的底表面，校正应变可补偿基板的顶表面上的非期望的应变及变形。可通过任意结合沉积、注入、热处理及蚀刻在基板的背侧上形成经特别设计的膜，以产生能补偿基板的非所欲变形的应变。通过局部改变氮化硅膜或碳膜的氢含量可导致局部应变。可由印刷、光刻术或自组装技术形成结构。可由期望的应力图来确定对膜的数个层的处理，且所述处理可包括退火、注入、熔融或其它热处理。

Description

底部处理
技术领域
本公开内容的实施方式一般地涉及用于半导体处理的方法及装置。更具体而言，本文所述的实施方式涉及用于处理基板的底侧的方法及装置。
背景技术
在芯片制造过程中，基板经历了不均匀的局部变形(distortion)，若没有被修正的话，局部变形会导致层与层之间产生光刻图案(lithography pattern)的未对准(misalignment)。既然可在光刻印刷期间使图案光学对位，对某些型态的变形而言，可校正定位(registration)。然而，对其它类型的变形而言，校正是不可能的且会导致产量损失的结果。此外，随着特征尺寸继续缩减，对变形的容限(tolerance)会降低，并且不可校正的变形的数量会增加。
先前已经通过将受控量的离子局部注入到硬掩模中以产生局部应变(localstrain)，来校正变形。局部应变可补偿原本存在的应变。然而，可能导致含有所选择的离子的下层的污染。
校正变形的其它尝试涉及硬掩模的可变局部表面退火，以产生局部应变来补偿原本存在的局部应变。然而，另一方面，当在随后的处理期间去除硬掩模的表面时，会发生局部松弛(relaxation)。
因此，在本技术领域中需要用于处理基板的背侧的方法与系统。
发明内容
在一个实施方式中，公开了一种用于处理基板的背侧的方法。所述方法可包括下列步骤：于基板的背侧上沉积膜；退火基板；及于基板的背侧上进行注入。所述方法进一步包括热处理基板的背侧。
在另一个实施方式中，公开了一种用于处理基板的背侧的方法。所述方法可包括下列步骤：退火基板；注入基板的背侧；及热处理基板的背侧。所述方法可进一步包括下列步骤：蚀刻基板的背侧；及对准基板以进行图案化。
在又一个实施方式中，公开了一种用于处理基板的工具。所述工具可包括：处理腔室，用以在基板的背侧上沉积多个膜层。所述处理腔室可包括：传送腔室、沉积工具、退火工具及蚀刻工具。退火工具可将基板的背侧上的多个膜层退火，且退火工具可包括基板边缘支撑件。蚀刻工具可蚀刻基板的背侧，并可包括基板边缘支撑件。
附图说明
以上简要概述的本公开内容的上述详述特征能够被具体理解的方式、以及本公开内容的更特定描述，可以通过参照实施方式获得，实施方式中的一些绘示于附图中。然而，应当注意，附图仅绘示本公开内容的典型实施方式，因而不应被视为是对本发明的范围的限制，因为本公开内容可以允许其他等同有效的实施方式。
图1示意性图解根据一个实施方式的用于处理基板的背侧的方法的操作。
图2示意性图解根据一个实施方式的用于处理基板的背侧的方法的操作。
图3图示根据一个实施方式的沉积腔室的示意图。
图4图示根据一个实施方式的用于热处理基板的装置的概要等角视图。
图5图示根据一个实施方式的用于热处理基板的快速热处理腔室的示意性等距图。
图6图示根据一个实施方式的用于热处理基板的装置的示意图。
图7图示根据一个实施方式的蚀刻反应器的示意图。
图8图示根据一个实施方式的具有多个基板处理腔室的群集工具传送腔室的顶部示意图。
为了便于理解，尽可能地，已经使用相同的附图标号来标示附图中共通的相同元件。考虑到，在一个实施方式中公开的元件在没有特定描述下可以有益地用于其它实施方式。
具体实施方式
一般来说，本文所公开的实施方式涉及用于处理基板的底表面以抵消基板上的热应力的方法及装置。可将校正应变施加至基板的底表面，校正应变可补偿基板的顶表面上的非期望的应变及变形。可藉由任意结合沉积、注入、热处理及蚀刻等方法在基板的背侧上形成经特别设计的膜，以产生能补偿基板的非所欲变形之应变。通过局部改变氮化硅膜或碳膜的氢含量可导致局部应变。可由印刷、光刻术或自组装技术可形成结构。可由期望的应力图(stress map)来确定对膜的数个层的处理，且所述处理可包括退火、注入、熔融或其它热处理。
如本文所应用，基板可以是任何合适的基板，如单晶硅基板；绝缘体上硅(SOI)；硅锗或其合金；如用于制造薄膜晶体管(TFT)的玻璃或石英基板，其上具有硅层，或类似物。基板可以具有在基板的器件侧上形成的器件和结构。
图1图解方法100的操作，方法100可用于处理基板的背侧，以补偿基板的前侧上的应变。
在操作110，在基板的背侧上沉积膜。可利用任何
Figure BDA0001649274680000031
系列腔室来完成沉积，
Figure BDA0001649274680000032
系列腔室可购自加州圣塔克拉拉市的应用材料公司。在某些实施方式中，所述膜可为沉积在基板的背侧上的覆盖膜(blanket film)。所述膜可以是，或可以包括，非晶碳膜、氧化硅膜或氮化硅膜。
将一区块的膜沉积到基板的对应区块。可将膜沉积到基板的背侧上。在某些实施方式中，所述膜的区块可对应到基板的前侧上的裸片。可将膜沉积达介于约40纳米与约120纳米之间的厚度。在某些实施方式中，可将膜沉积至基板的边缘。
可使用本技术领域中已知的标准图案化技术，在基板的背侧上形成具有不同厚度或具有变化厚度的层。因此，可在退火所述膜层时产生不同的应力。举例而言，在某些实施方式中，可在基板的背侧上沉积覆盖膜层，且可使用掩模将附加的膜选择性地沉积在期望的位置内。可通过调整处理条件来选择及施加覆盖膜及附加膜中的应力。
举例而言，可在基板的背侧上沉积非晶碳层。可在非晶碳层上沉积氧化硅层。可图案化氧化硅层以形成掩模，且接着在基板上方沉积第二非晶碳层。可在所述背侧上平坦化基板，以暴露氧化硅掩模，接着可移除氧化硅掩模而留下具有选择性变化的厚度的非晶碳层。
于操作120，可将基板的背侧退火。退火可改变背侧膜的结构，并根据任何期望的图案调整膜内的应变。举例而言，退火可松弛所沉积的膜内的应变。可对膜选择性地局部退火，以在基板的背侧上产生校正应变(correcting strain)，校正应变可补偿基板的前侧上的非期望应变。在某些实施方式中，也可在一个步骤中对膜进行全面性退火(blanketanneal)，以调整在沉积期间被选择性地加入膜内的应变。在一个实施方式中，可通过将设计过的膜层施加到基板的背侧来产生校正应变。在另一个实施方式中，可经由利用来自先前处理之已存在膜层来产生校正应变。
在某些实施方式中，退火可为点退火(spot annealing)。点退火可发生在基板的背侧的选择位置上。退火操作可利用各种类型的能量。在某些实施方式中，退火可为纳秒退火工艺。在其它实施方式中，退火可为毫秒退火工艺。
退火可导致基板的背侧上的期望层的改变，其可用于减轻所沉积的层中的应力和/或应变。选择性地减轻应力和/或应变可在基板中产生应力的图案，以补偿由热处理产生的结构不均匀性。可在退火工艺期间改变整体基板的应力状态，因此可设计退火工艺来产生基板的中间应力/应变状态，而由后续处理可进一步改变基板的中间应力/应变状态。
在某些实施方式中，可在基板的背侧上界定多个区块，并可使用不同的工艺条件对各区块进行退火。举例而言，可经由纳秒退火工艺来退火第一区块，并经由毫秒退火工艺来退火第二区块。在另一个实施方式中，可在基板的背侧上选择性地沉积材料层。举例而言，可在第一层上沉积非晶碳，而对其它层涂布二氧化硅。
于操作130，可对基板的背侧进行注入。可利用任何
Figure BDA0001649274680000041
腔室来完成注入，
Figure BDA0001649274680000042
腔室可购自位于加州圣塔克拉拉市的应用材料公司。注入是调整背侧膜中应力的另一种方式，其通过加入掺杂剂来调整应力。可在本公开内容中应用的一类膜包括高级图案化膜(Advanced Patterning Film；
Figure BDA0001649274680000043
)，其包括非晶碳材料。由此，可沉积经掺杂的非晶碳，可沉积未掺杂的非晶碳，或可沉积未掺杂的非晶碳再进行后续掺杂。膜也可包含氮化物、金属硅化物或经历相变的任何其它材料中的一者。在某些实施方式中，膜可以是自吸收的(self-absorbing)，这是因为膜可以溶解和/或扩散进入基板。
可选择注入的掺杂剂来调整所沉积的层中的应力。可以根据图案注入掺杂剂，以修改膜的特定区块中的应力。应力可以是拉伸应力和/或压缩应力。掺杂剂可以是金属或非金属。掺杂剂可包括：He、Ne、Ar、F、Cl、Br、O、N、P、As、Si、Ge、Sn、B、Al、Ga、In、Zn、Cu、Ag、Au、Ni、Ti及前述掺杂剂的组合或合金。
可由离子束或等离子体来进行注入。在某些实施方式中，注入可为直接注入。在其它实施方式中，注入可为沉积后接着扩散。在某些实例中，可在扩散注入工艺期间使用盖层(capping layer)。
在不同的实施方式中，可蚀刻基板的背侧。如下文所描述的蚀刻腔室可蚀刻基板的背侧。可使用掩模或其它图案特征，根据期望图案来进行蚀刻工艺，以通过将图案化应力差施加到基板的背侧来影响遍及基板的应力。蚀刻工艺亦可以是将材料从基板的背侧全面性去除(blanket removal)，以将全面性应力差(blanket stress differential)施加至基板的背侧。全面性应力差可以有效地改变基板的一部分中的整个局部应力，而多于基板的另一部分中的整个局部应力，这对于某些实施方式而言是有用的。
在不同的实施方式中，可在基板的背侧上形成应力的图案，以补偿基板的前侧上的应变。在某些实施方式中，可在基板的背侧上沉积膜层，其中所述膜层，例如非晶碳，可保持一定的沉积时应力(压缩应力或拉伸应力)。可在选择的位置内对所沉积的膜层进行退火，以减轻应力。
在另一个实施方式中，可在基板的背侧上沉积非晶碳，并选择性地注入非晶碳。随后，可将基板退火，以形成图案，所述图案可产生相异应力矩阵(stress matrix)，因而在基板的背侧上产生应力的图案。
在另一个实施方式中，可在基板的背侧上沉积具有不同厚度的膜层。后续可根据图案将基板退火，因而在基板的背侧上产生应力的图案。
在另一个实施方式中，可蚀刻基板的背侧以选择性移除膜层，因而在基板的背侧上产生相异厚度并产生应力的图案。
方法100可进一步包括对准基板以进行图案化、定位基板中的变形，以及通过平坦化基板来补偿变形。
图2图解方法200的操作，方法200可用于处理基板的背侧，以补偿基板的前侧上的应变。
于操作210，可对基板的背侧进行退火。退火可改变背侧膜的结构，并根据任何期望的图案调整膜内的应变。举例而言，退火可松弛(relax)所沉积的膜内的应变。可对膜选择性地局部退火，以在基板的背侧上产生校正应变(correcting strain)，校正应变可补偿基板的前侧上的非期望应变。在某些实施方式中，也可在一个步骤中对膜进行全面性退火(blanket anneal)，以调整在沉积期间被选择性地加入膜内的应变。在一个实施方式中，可藉由将设计过的膜层施加到基板的背侧来产生校正应变。在另一个实施方式中，可经由利用来自先前处理的已存在膜层来产生校正应变。
在某些实施方式中，退火可为点退火(spot annealing)。点退火可发生在基板的背侧的选择位置上。退火操作可利用各种类型的能量。在某些实施方式中，退火可为纳秒退火工艺。在其它实施方式中，退火可为毫秒退火工艺。
退火可导致基板的背侧上的期望层的改变，其可用于减轻所沉积的层中的应力和/或应变、施加期望的应力差至基板的背侧，和/或改变基板的应力分布(stressprofile)。选择性地减轻应力和/或应变可在基板中产生应力的图案，以补偿由热处理产生的结构不均匀性。可在退火工艺期间改变整体基板的应力状态，因此可设计退火工艺来产生基板的中间应力/应变状态，而由后续处理可进一步改变基板的中间应力/应变状态。
在某些实施方式中，可在基板的背侧上界定多个区块，并可使用不同的制程条件对各区块进行退火。举例而言，可透过纳秒退火制程来退火第一区块，并透过毫秒退火制程来退火第二区块。在另一个实施方式中，可在基板的背侧上选择性地沉积材料层。举例而言，可在第一层上沉积非晶碳，而对其它层涂布二氧化硅。
于操作220，可对基板的背侧进行注入。可利用任何
Figure BDA0001649274680000061
腔室来完成注入，
Figure BDA0001649274680000062
腔室可购自位于加州圣塔克拉拉市的应用材料公司。注入是通过加入掺杂剂来调整背侧膜中应力的另一种方式。可在本公开内容中应用的一类膜包括高级图案化膜(Advanced Patterning Film；
Figure BDA0001649274680000063
)，其包括非晶碳材料。由此，可沉积经掺杂的非晶碳、可沉积未掺杂的非晶碳，或可沉积未掺杂的非晶碳再进行后续掺杂。膜也可包含氮化物、金属硅化物或经历相变的任何其它材料中的一者。在某些实施方式中，膜可以是自吸收的(self-absorbing)。
可选择注入的掺杂剂来调整所沉积的层中的应力。可以根据图案注入掺杂剂，以修改膜的特定区块中的应力。应力可以是拉伸应力和/或压缩应力。掺杂剂可以是金属或非金属。掺杂剂可包括：He、Ne、Ar、F、Cl、Br、O、N、P、As、Si、Ge、Sn、B、Al、Ga、In、Zn、Cu、Ag、Au、Ni、Ti及前述掺杂剂的组合或合金。
可由离子束或等离子体来进行注入。在某些实施方式中，注入可为直接注入。在其它实施方式中，注入可为沉积后接着扩散。在某些实例中，可在扩散注入工艺期间使用盖层(capping layer)。
于操作230，可蚀刻基板的背侧。如下文所描述的蚀刻腔室可蚀刻基板的背侧。于操作240，可对准基板以进行图案化。
在某些实施方式中，方法200可进一步包括将膜沉积在基板的背侧上。一类的膜可被用来增进光刻术的图案化。因此，膜可包含氮化物、非晶碳、金属硅化物或可进行相变的任何其它材料中的一者。在某些实施方式中，膜可以是自吸收的(self-absorbing)。可将膜的某区块沉积到基板的对应区块。在某些实施方式中，膜的区块可对应到基板的前侧上的裸片。可将膜沉积达介于约40纳米与约120纳米之间的标准深度。
在其它实施方式中，方法200进一步包括：定位基板中的变形，以及通过平坦化基板来补偿所述变形。
图3图示用于处理基板的装置。图3的装置可以是如上所述，用于在基板的背侧上沉积膜的等离子体沉积腔室。
图3示出腔室300的示意性截面图，腔室300界定两个处理区域318、320。腔室主体302包括侧壁312、内壁314和底壁316，所述侧壁312、内壁314和底壁316界定两个处理区域318、320。各处理区域318、320中的底壁316界定至少两个通道322、324，其中基座加热器328的主干326和基板升降销组件的轴杆330经设置而分别穿过通道322、324。
侧壁312和内壁314界定两个圆柱状环型处理区域318、320。周边泵送通道325形成于界定所述圆柱状处理区域318、320的腔室壁中，用以自处理区域318、320排出气体，并控制各区域318、320内的压力。可在各处理区域318、320中设置由陶瓷材料或类似材料制成的腔室衬里或嵌入件327，以界定各处理区域的侧向边界，并保护腔室壁312、314不受到腐蚀性处理环境影响并在电极之间维持电气隔离的等离子体环境。衬里327被支撑于腔室中的凸缘329上，凸缘329形成在各处理区域318、320的壁312、314中。衬里可包括多个排放端口331或周向槽(circumferential slots)，所述排放端口331或周向槽穿过衬里而设置，并与形成在腔室壁中的泵送通道325连通。在一个实施方式中，有约二十四个端口331设置成穿过各衬里327，所述端口331间隔约15度且围绕处理区域318、320的外围定位。尽管上面描述了二十四个端口，但是可以采用任何数量，以实现期望的泵送速率和均匀性。除了端口的数量之外，端口相对于气体分配系统的面板的高度可受到控制，以在处理期间在基板上方提供最佳的气流模式。
在某些实施方式中，腔室300包括基板边缘支撑件380。基板边缘支撑件380可为连续或不连续的壁或为多个柱体，以将基板的边缘部分支撑在基座加热器328的上方。在某些实施方式中，基板边缘支撑件380可避免基板的器件侧与基座加热器328之间的直接接触，以允许将层沉积在基板的背侧上。
如前文所述，在某些实施方式中，可利用边缘支撑件380将基板的边缘部分支撑在基座加热器的上方。然而，在某些实施方式中，可由多个销(pin)来支撑基板。多个销可在基板上的任何位置处接触基板，包括在接近基板的边缘的位置处。销支撑件可允许对基板的底部应力膜侧的快速加热(flash heating)。进而，在某些实施方式中，当基板安置和/或被支撑在基板的边缘上时，可对基板的背侧进行激光退火或加热。
图4是用于热处理基板的系统400的平面图。可利用系统400对基板施加脉冲式激光辐射，如前文所述。具体而言，可在纳秒退火工艺中利用系统400。进一步地，如前文所述，可利用系统400对基板的背侧进行退火。
系统400包括能量模块402、脉冲控制模块404、脉冲成形模块406、均质器408、孔构件416和对准模块418，能量模块402具有可产生多个脉冲式激光脉冲的多个脉冲式激光源；脉冲控制模块404可结合独立的多个脉冲式激光脉冲成为结合脉冲式激光脉冲，并控制结合脉冲式激光脉冲的强度、频率特性和极性特性；脉冲成形模块406可调整经结合的脉冲式激光脉冲的脉冲的时域分布(temporal profile)；均质器408可调整脉冲的空间能量分布，使结合脉冲式激光脉冲重叠成单一均匀能量场；孔构件416可自所述能量场移除残存的边缘不均匀性；且对准模块418使激光能量场与设置在基板支撑件410上的基板的精确对准。控制器412可耦接能量模块402，以控制激光脉冲的产生；控制器412可耦接脉冲控制模块404，以控制脉冲特性；且控制器412可耦接基板支撑件410，以控制基板相对于能量场的移动。通常，外壳414包围系统400的操作性部件。在某些实施方式中，系统400可进一步包括遮蔽环490，用以遮蔽基板的边缘，使基板的边缘不受高热应力。
为了类似的目的，基板支撑件410的特征可以是与上面结合图3所述的边缘支撑件380基本相似的边缘支撑件。当载台被移动以定位基板来处理特定的目标区域时，可通过在基板边缘和遮蔽环490之间采用适当小的间距，以使基板在边缘支撑件上的非所欲移动最小化。举例而言，若基板为300mm的基板，则遮蔽环490可具有150.2mm或更小的内半径。
如前文所述，在某些实施方式中，可利用边缘支撑件来支撑基板的边缘部分。然而，在某些实施方式中，可由多个销来支撑基板。多个销可在基板上的任何位置处接触基板，包括在接近基板的边缘的位置处。销支撑件可允许对基板的底部应力膜侧的脉冲式激光处理。进而，在某些实施方式中，当基板安置和/或被支撑在基板的边缘上时，可对基板的背侧进行激光处理或加热。
激光器可以是能够形成短脉冲(例如持续时间为短于约100nsec)的高功率激光辐射的任何类型激光器。一般而言，使用高模态(modality)激光器，该高模态激光器具有超过500个空间模式(mode)，且M2大于约30。经常使用固态激光器，诸如Nd：YAG、Nd：玻璃、钛-蓝宝石、或其他掺杂有稀土的晶体激光器，但可使用气态激光器，诸如准分子激光器，例如XeCl2、ArF、或KrF激光器。可开关(switch)这些激光器，诸如通过Q开关(被动或主动)、增益开关(gain switching)、或锁模(mode locking)来开关。也可在激光器输出端附近使用普克尔盒(Pockels cell)，以通过中断激光器所发射的射束来形成脉冲。大体而言，可用于脉冲式激光处理的激光能够产生具下述特征的激光辐射的脉冲：能量含量介于约100mJ与约10J之间，且持续时间介于约1nsec与约100μsec之间，一般而言是在约8nsec内约1J。所述激光可具有介于约200nm与约2,000nm之间的波长，诸如介于约400nm与约1,000nm之间，例如约532nm。在一个实施方式中，所述激光器是Q开关、频率加倍的Nd：YAG激光器。所述激光器可全部在相同波长操作，或这些激光中的一或多个激光器可在与能量模块402中的其它激光器不同的波长下操作。所述激光器可放大(amplify)以发展期望的功率级(powerlevel)。多数情况中，放大的媒介会是与激光媒介相同或类似的组成。每一单独的激光脉冲通常由自身放大，但在某些实施方式中，所有激光脉冲可在组合后放大。
传送到基板的典型激光脉冲是多重激光脉冲的组合。多重脉冲在受控时间和彼此受控的关系中产生，使得当组合时，产生激光辐射的单一脉冲，所述激光辐射的单一脉冲具有受控的时间和空间能量分布，具有受控的能量升高、持续时间和衰减，以及能量非均匀性的受控空间分布。控制器412可具有脉冲产生器(例如，耦接到电压源的电子定时器)，所述脉冲产生器可耦接到各激光器(例如，各激光器的各开关)，以控制来自各激光器的脉冲的产生。
多个激光器可经排列，使得各激光产生射入脉冲控制模块404的脉冲，脉冲控制模块404可具有一或多个脉冲控制器405。一或多个脉冲离开脉冲控制模块404并进入脉冲成形模块406，脉冲成形模块406具有一或多个脉冲成形器407。
在某些实施方式中，可从基板支撑件410下方导引激光辐射朝向基板，所述基板以器件侧朝上(device-side-up)的方式安置在边缘支撑件上。可提供基板支撑件410中的窗或开口，以允许激光辐射从基板支撑件410下方朝向基板的背侧。
图5为用于热处理基板的系统500的示意图。如上所述，可利用系统500来退火(经由灯退火)和/或化学快速退火基板。进而，如上所述，可利用系统500来退火基板的背侧。
图5是快速热处理(rapid thermal processing；RTP)腔室500的一个实施方式的简化等矩图。可经调适而受益于本公开内容的快速热处理腔室的实例为
Figure BDA0001649274680000101
腔室，
Figure BDA0001649274680000102
腔室可购自位在加州圣塔克拉拉市的应用材料公司。处理腔室500可包括无接触或磁悬浮的基板支撑件504及腔室主体502，腔室主体502具有壁508、底部510及顶部512界定内部容积520。壁508通常可包括至少一个基板进出口548，以有助于基板540(图5中显示部分基板540)的进入和离开。进出口可耦接至传送腔室(未示出)或装载锁定腔室(未示出)，且可以利用阀选择性密封进出口，所述阀，例如狭缝阀(未示出)。在一个实施方式中，基板支撑件504为环状，且腔室500可包括辐射热源506，辐射热源506可设置在基板支撑件504的内径中。
基板支撑件504适于在内部容积520中磁悬浮和旋转。在处理期间，基板支撑件504能在垂直地升高和降低的同时旋转，且也可在处理之前、期间或之后被升高或降低而不旋转。因为缺乏或减少通常用来升高/降低和/或旋转基板支撑件的移动部件之故，此磁悬浮和/或磁旋转可防止或最小化颗粒产生。
腔室500也可包括窗514，窗514可由对热及多种波长的光透明的材料制成，所述光可包括红外线(IR)光谱中的光，来自辐射热源506的光子透过窗514可加热基板540。窗514可包括耦接至窗514的上表面的多个升降销544，升降销544适于选择性地接触并支撑基板540，以有助于基板转移进入或离开腔室500。
在一个实施方式中，辐射热源506可包括由壳体形成的灯组件，壳体可包括位在冷却剂组件(未示出)中的多个蜂巢管560，而冷却剂组件耦接至冷却剂源583。冷却剂源583可为水、乙二醇、氮气(N2)及氦(He)中的一者或其组合。壳体可以由铜材料或其它合适的材料制成，其中形成有供来自冷却剂源583的冷却剂流动的适当冷却剂通道。每个管560可以含有形成蜂窝状管布置的反射器和高强度灯组件或IR发射器。可由一或多个温度传感器517(更详细描述于下文)对基板540的加热进行动态控制，所述一或多个温度传感器517适于测量基板540各处的温度。
定子组件518可环绕腔室主体502的壁508，并耦接至一或多个致动器组件522，致动器组件522可控制定子组件518沿着腔室主体502的外部升高。
气氛控制系统564也可耦接至腔室主体502的内部容积520。气氛控制系统564通常包括节流阀及真空泵，用于控制腔室压力。气氛控制系统564可额外包括气体源，用于将处理气体或其它气体供应至内部容积520。气氛控制系统564也可适于传递处理气体供热沉积工艺所用。
腔室500也可包括控制器524，控制器524通常包括中央处理单元(CPU)530、支持电路528和存储器526。CPU 530可为任何形式的计算机处理器中的一种，其可以用于工业设定，以控制各种动作和子处理器。存储器526，或电脑可读介质，可以是易于获得的存储器中的一或多种，诸如随机存取存储器(RAM)、唯读存储器(ROM)、软盘、硬盘或任何其它形式的数字存储装置，本地或远程，并且通常耦接至CPU 530。支持电路528可耦接至CPU 530，用于以常规方式支持控制器524。这些电路可包括快取、电源、时脉电路、输入/输出电路、子系统等。
腔室500也可包括一或多个传感器516，传感器516通常适于检测腔室主体502的内部容积520中的基板支撑件504(或基板540)的升高。传感器516可耦接至腔室主体502和/或处理腔室500的其它部分，并适于提供输出，该输出能指示基板支撑件504与腔室主体502的顶部512和/或底部510之间的距离，且传感器516还可检测基板支撑件504和/或基板540之间的未对准。一或多个传感器516可耦接至控制器524，控制器524可接收来自传感器516的输出度量，并提供一或多个信号至一或多个致动器组件522，以升高或降低基板支撑件504的至少一部分。一或多个传感器516可为超声波、激光、电感式、电容式或适于检测腔室主体502内的基板支撑件504的接近度(proximity)的其它类型传感器。
腔室500也可包括一或多个温度传感器517，其可适于在处理之前、期间或之后感测基板540的温度。在图5所描绘的实施方式中，温度传感器517穿过顶部512而设置，但也可采用腔室主体502内部或周围的其它位置。
图6示意性地图示用于热处理基板的装置600。具体而言，可在毫秒退火工艺中利用装置600。进而，如上所述，系统600可被用来退火基板的背侧。
装置600可包括连续波电磁辐射模块601、载台616及平移机构618，其中载台616经构造以接收载台上的基板614。连续波电磁辐射模块601可包括连续波电磁辐射源602和聚焦光学元件620，聚焦光学元件620设置在连续波电磁辐射源602与载台616之间。
连续波电磁辐射源602能发射诸如光的电磁辐射的“连续波(continuous waves)”或射线。“连续波(continuous waves)”是指辐射源被构造为连续地发射辐射，即不是辐射的爆发(burst)、脉冲或闪光。这与激光退火中使用的激光非常不同，激光退火通常使用爆发或闪光。
进而，由于连续波电磁辐射在基板的表面处或附近被吸收，所述辐射具有的波长是在基板可吸收辐射的范围内。在硅基板的案例中，连续波电磁辐射具有介于190nm与950nm之间的波长，诸如大约810nm。
或者，可以使用在UV中或附近操作的高功率连续波电磁辐射激光源。由这种连续波电磁辐射激光源产生的波长被大多数其它反射材料高度吸收。
在一个实施方式中，连续波电磁辐射源602能够连续发射辐射达至少15秒。在另一个实施方式中，连续波电磁辐射源602可包括多个激光二极管，每个激光二极管可产生相同波长的均匀且空间相干的光。激光二极管的功率可在0.5kW至50kW的范围内，例如，接近5kW。合适的激光二极管是由加州圣塔克拉拉市的Coherent公司、加州的Spectra-Physics所制造；或由密苏里州圣查尔斯市的Cutting Edge Optronics公司所制造。激光二极管的一个实例是由Cutting Edge Optronics公司所制造，而另一个合适的激光二极管是Spectra Physics的
Figure BDA0001649274680000131
多杆模块(multi-bar module；MBM)，此提供每个激光二极管模块40至480瓦的连续波功率。
聚焦光学元件620可包括一或多个准直器606，以使来自连续波电磁辐射源602的辐射604准直成为实质上平行的射束608。此经准直的辐射608接着被至少一个透镜610聚焦成为基板614的上表面624处的线形辐射622。
透镜610是能将辐射聚焦成为线形的任何合适的透镜或一系列的透镜。在一个实施方式中，透镜610是柱状透镜。或者，透镜610可为一或多个凹透镜、凸透镜、平面镜、凹面镜、凸面镜、折射透镜、衍射透镜、菲涅尔透镜、梯度折射率透镜(gradient index lens)或类似物。
载台616可包括用于平移基板的平台，如下文所解释的。载台616可包括类似于图3的边缘支撑件390的边缘支撑件，以用于基板的背侧处理。
如前文所述，在某些实施方式中，可利用边缘支撑件来支撑基板的边缘部分。然而，在某些实施方式中，可由多个销来支撑基板。多个销可在基板上的任何位置处接触基板，包括在接近基板的边缘的位置处。销支撑件可允许对基板的底部应力膜侧的热处理。进而，在某些实施方式中，当基板安置和/或被支撑在基板的边缘上时，可对基板的背侧进行热处理。
装置600也可包括平移机构618，平移机构618经构造以使载台616和线状辐射622相对于彼此平移。在一个实施方式中，平移机构618可耦接至载台616，以相对于连续波电磁辐射源602和/或聚焦光学元件620移动载台616。在另一个实施方式中，平移机构可耦接至连续波电磁辐射源602及聚焦光学元件620两者，以相对于载台616移动连续波电磁辐射源602和/或聚焦光学元件620。在又一个实施方式中，平移机构618移动连续波电磁辐射源602、聚焦光学元件620及载台616。可使用任何合适的平移机构，诸如输送系统、齿条和齿轮系统，或者类似物。
在某些实施方式中，装置600可包括遮蔽环690，以屏蔽基板614的边缘不受高温应力。如上所注解，可设定遮蔽环690的尺寸，以防止载台616上的基板的非所欲移动。
图7图示蚀刻反应器700的示意图。可利用蚀刻反应器700来蚀刻基板的背侧，如上所述。
在某些实施方式中，蚀刻反应器700可包括离子自由基屏蔽件770。可适于与本文所披露的教示一起使用的合适反应器包括，例如，Decoupled Plasma Source
Figure BDA0001649274680000141
I型反应器，或Tetra I型及Tetra II型光掩模蚀刻系统，以上全部可从加州圣塔克拉拉市的应用材料公司获得。
Figure BDA0001649274680000142
II型反应器也可被用作
Figure BDA0001649274680000143
整合式半导体晶片处理系统(一样可自应用材料公司获得)的处理模块。本文所示的反应器700的特定实施方式是出于说明的目的而提供，而不应当用于限制本公开内容的范围。
反应器700一般可包括处理腔室702及控制器746，处理腔室702具有基板基座724位在导电主体(壁)704内。腔室702具有实质上平坦的介电质顶板708。腔室702的其它修饰例可具有其它类型的顶板，例如圆顶状的顶板。天线710可设置在顶板708上方。天线710可包括一或多个感应线圈元件，一或多个感应线圈元件可被选择性控制(图7中显示两个同轴元件710a和710b)。天线710可通过第一匹配网络714耦接至等离子体功率源712。等离子体功率源712通常能在自约50kHz至约13.56MHz的范围中的可调节频率下，产生高达约3000W。
基板基座(阴极)724可透过第二匹配网络742耦接至偏压电源740。偏压电源740通常是在大约13.56MHz的频率下高达约500W的源，其能够产生连续或脉冲式功率。或者，源740可以是DC或脉冲式DC源。
在一个实施方式中，基板支撑基座724可提供基板边缘支撑件。在一个实施方式中，基板支撑基座724可包括静电卡盘(electrostatic chuck)760。静电卡盘760可包括至少一个夹持电极732，并且由卡盘电源766控制。在替代实施方式中，基板基座724可包括基板保持机构，例如底座夹持环(susceptor clamp ring)、机械式卡盘(mechanical chuck)和类似物。
可使用光罩接合器(reticle adapter)782将基板(光罩)722固定在基板支撑基座724上。光罩接合器782一般包括下部784及上部786，下部784可经磨制以覆盖基座724(例如，静电卡盘760)的上表面，而上部786具有开口788，开口788的尺寸和形状可经订制以托持基板722。开口788通常相对于基座724而实质置中。接合器782通常由诸如聚酰亚胺陶瓷或石英的抗蚀刻、耐高温材料的单一部件所形成。边缘环726可覆盖接合器782和/或将接合器782固定至基座724。
升降机构738可用于降低或升高接合器782，且因而降低基板722至基板支撑基座724上，或升高基板722离开基板支撑基座724。一般而言，举升机构762可包括多个升降销730(仅示出一个升降销)，升降销730可穿过各自的导向孔736行进。
在操作中，可通过稳定基板基座724的温度来控制基板722的温度。在一个实施方式中，基板支撑基座724可包括阻抗式加热器744和散热器728。阻抗式加热器744通常包括至少一个加热元件734，并受到加热器电源768的调控。来自气体源756的背侧气体(例如，氦(He))可经由气体导管758提供至通道，所述通道形成在基板722下方的基座表面中。背侧气体可用来协助基座724与基板722之间的热传递。在处理期间，可由内嵌的阻抗式加热器744将基座724加热至稳态(steady-state)温度，此方式可与氦背侧气体结合而有助于基板722的均匀加热。使用这样的热控制方式，可将基板722维持在介于约0摄氏度与350摄氏度之间的温度。
离子-自由基屏蔽件770设置在基座724上方的腔室702中。离子-自由基屏蔽件770可与腔室壁704及基座724电性隔离，且通常包括实质上平坦的板772和多个支脚776。可由支脚776将板772支撑在基座上方的腔室702中。板772可界定一或多个开口(通孔)774，所述开口在板772的表面中界定了期望的开口区块。离子-自由基屏蔽件770的开口区块可控制从等离子体递送至下处理容积780的离子的量，其中等离子体形成于处理腔室702的上处理容积778中，而下处理容积780位在离子-自由基屏蔽件770与基板722之间。开口面积越大，则越多离子可通过离子-自由基屏蔽件770。由此，通孔774的尺寸可控制容积780中的离子密度。所以，屏蔽件770为离子过滤器。
图8图示群集工具810的顶部示意图，群集工具810具有多个基板处理腔室812，多个基板处理腔室812安装于群集工具810上。与图8所示的群集工具类似的群集工具可购自加州圣塔克拉拉市的应用材料公司。群集工具810可用作为传送腔室，以在本文所述的多个工具与腔室之间转移基板。
工具可包括装载锁定腔室820及传送腔室818，传送腔室818具有基板传送模块816，用以在系统内将基板从一个位置移动至另一个位置，特别是在多重基板处理腔室812之间移动基板。示出此特定工具为容纳多达四个基板处理腔室812，四个基板处理腔室812径向地围绕传送腔室而定位，然而，可以预期的是，可以在此工具上容纳任何数量的基板处理腔室812。
本公开内容的益处包括：基板底部的处理较为不会在热力学上影响基板的顶部结构(例如，经由表面加热技术、高表面辐照度激光或闪光灯的使用)或在组成分上影响基板的顶部结构。此外，来自基板的底部的应变更一致，因为它们与基板顶部上的任何处理隔离。进而，可以在基板的底部上进行额外的调整，以补偿在后续处理中产生的应变。一旦被加热，在基板的背侧上的注入可抵消在基板的前侧上的其它热应力。
虽然前述针对本公开内容的实施方式，但在不偏离本公开内容的基本范围的情况下可设计其它和进一步的实施方式，并且本公开内容的范围可由随附的权利要求书来确定。

Claims (7)

1.一种用于处理基板的方法，所述基板具有在前侧上形成的器件，所述方法包含下列步骤：
将所述基板的背侧激光退火，以调整所述基板的所述背侧中的应变；接着注入所述基板的所述背侧，以调整所述基板的所述背侧中的应变；接着蚀刻所述基板的所述背侧；和接着
对准所述基板以进行图案化。
2.如权利要求1所述的方法，进一步包含下列步骤：在所述基板的所述背侧上沉积膜至介于50nm与100nm之间的厚度。
3.如权利要求2所述的方法，其中所述膜的一区块对应到所述基板的所述前侧上的裸片。
4.如权利要求2所述的方法，其中所述膜溶解或扩散进入所述基板。
5.如权利要求1所述的方法，其中所述激光退火是点退火，且其中所述点退火发生在所述基板的所述背侧的选择位置上以产生应力的图案。
6.如权利要求1所述的方法，其中所述激光退火是纳秒退火工艺或毫秒退火工艺。
7.如权利要求1所述的方法，所述方法进一步包含下列步骤：
定位所述基板中的变形；和
通过平坦化所述基板来补偿所述变形。
CN201680064396.3A 2015-11-09 2016-10-10 底部处理 Active CN108352298B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202310350135.XA CN116435172A (zh) 2015-11-09 2016-10-10 底部处理
CN202211543021.9A CN116435167A (zh) 2015-11-09 2016-10-10 底部处理

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562252901P 2015-11-09 2015-11-09
US62/252,901 2015-11-09
US201662306150P 2016-03-10 2016-03-10
US62/306,150 2016-03-10
PCT/US2016/056220 WO2017083037A1 (en) 2015-11-09 2016-10-10 Bottom processing

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN202310350135.XA Division CN116435172A (zh) 2015-11-09 2016-10-10 底部处理
CN202211543021.9A Division CN116435167A (zh) 2015-11-09 2016-10-10 底部处理

Publications (2)

Publication Number Publication Date
CN108352298A CN108352298A (zh) 2018-07-31
CN108352298B true CN108352298B (zh) 2023-04-18

Family

ID=58663719

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201680064396.3A Active CN108352298B (zh) 2015-11-09 2016-10-10 底部处理
CN202310350135.XA Pending CN116435172A (zh) 2015-11-09 2016-10-10 底部处理
CN202211543021.9A Pending CN116435167A (zh) 2015-11-09 2016-10-10 底部处理

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN202310350135.XA Pending CN116435172A (zh) 2015-11-09 2016-10-10 底部处理
CN202211543021.9A Pending CN116435167A (zh) 2015-11-09 2016-10-10 底部处理

Country Status (7)

Country Link
US (1) US10128197B2 (zh)
JP (1) JP6971229B2 (zh)
KR (2) KR20230152092A (zh)
CN (3) CN108352298B (zh)
DE (1) DE112016005136T5 (zh)
TW (2) TWI729498B (zh)
WO (1) WO2017083037A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10418264B2 (en) * 2016-06-08 2019-09-17 Hermes-Epitek Corporation Assembling device used for semiconductor equipment
US10510575B2 (en) * 2017-09-20 2019-12-17 Applied Materials, Inc. Substrate support with multiple embedded electrodes
US10916416B2 (en) * 2017-11-14 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer with modified surface and fabrication method thereof
KR102612989B1 (ko) * 2017-12-01 2023-12-11 어플라이드 머티어리얼스, 인코포레이티드 고 에칭 선택성 비정질 탄소 막
JP2020047617A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 基板処理装置、半導体装置の製造方法、および被加工基板
DE102019211447B4 (de) * 2019-07-31 2023-06-01 Robert Bosch Gmbh Verfahren zum Laserrichten von Führungsschienen
CN115803882A (zh) 2021-06-30 2023-03-14 长江存储科技有限责任公司 三维存储器装置及其形成方法
WO2023028729A1 (en) * 2021-08-30 2023-03-09 Yangtze Memory Technologies Co., Ltd. Wafer stress control and semiconductor structure
US20240105641A1 (en) * 2022-09-28 2024-03-28 Applied Materials, Inc. Correction of global curvature during stress management
CN115642112A (zh) * 2022-11-24 2023-01-24 西安奕斯伟材料科技有限公司 一种用于硅片的背封装置及背封方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223425A (ja) * 1999-02-02 2000-08-11 Nec Corp 基板処理装置、ガス供給方法、及び、レーザ光供給方法
JP2001274048A (ja) * 2000-03-24 2001-10-05 Hitachi Ltd 半導体装置の製造方法及び加工装置
CN101009221A (zh) * 2006-01-23 2007-08-01 三菱电机株式会社 半导体装置的制造方法
CN102420176A (zh) * 2011-06-15 2012-04-18 上海华力微电子有限公司 一种改善半导体晶片翘曲的方法
CN103094098A (zh) * 2013-01-14 2013-05-08 陆伟 一种解决晶圆破片的方法
US20150294917A1 (en) * 2014-04-09 2015-10-15 Tokyo Electron Limited Method for Correcting Wafer Bow from Overlay

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296385A (en) 1991-12-31 1994-03-22 Texas Instruments Incorporated Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing
JPH05315371A (ja) * 1992-05-12 1993-11-26 Fujitsu Ltd 化合物半導体装置の製造方法
AU8675798A (en) 1997-07-29 1999-02-22 Silicon Genesis Corporation Cluster tool method and apparatus using plasma immersion ion implantation
JP3505678B2 (ja) * 1999-08-25 2004-03-08 住友重機械工業株式会社 ウエハの歪修正装置
KR20020034492A (ko) 2000-11-02 2002-05-09 박종섭 반도체 소자의 제조방법
JP4653374B2 (ja) * 2001-08-23 2011-03-16 セイコーエプソン株式会社 電気光学装置の製造方法
US7208380B2 (en) 2004-03-22 2007-04-24 Texas Instruments Incorporated Interface improvement by stress application during oxide growth through use of backside films
US7244311B2 (en) * 2004-10-13 2007-07-17 Lam Research Corporation Heat transfer system for improved semiconductor processing uniformity
US7432177B2 (en) 2005-06-15 2008-10-07 Applied Materials, Inc. Post-ion implant cleaning for silicon on insulator substrate preparation
US20080128019A1 (en) * 2006-12-01 2008-06-05 Applied Materials, Inc. Method of metallizing a solar cell substrate
US8846532B2 (en) 2007-02-28 2014-09-30 Alpha And Omega Semiconductor Incorporated Method and apparatus for ultra thin wafer backside processing
US7776746B2 (en) 2007-02-28 2010-08-17 Alpha And Omega Semiconductor Incorporated Method and apparatus for ultra thin wafer backside processing
CN102017101B (zh) 2008-05-02 2014-06-04 应用材料公司 用于旋转基板的非径向温度控制系统
US20090278287A1 (en) * 2008-05-12 2009-11-12 Yun Wang Substrate processing with reduced warpage and/or controlled strain
US20100109060A1 (en) 2008-11-06 2010-05-06 Omnivision Technologies Inc. Image sensor with backside photodiode implant
JP2010225830A (ja) 2009-03-24 2010-10-07 Mitsumi Electric Co Ltd 半導体装置の製造方法
KR101758852B1 (ko) * 2009-07-15 2017-07-17 퀄컴 인코포레이티드 후면 방열 기능을 갖는 반도체-온-절연체
TWI396771B (zh) * 2009-08-25 2013-05-21 羅門哈斯電子材料有限公司 形成矽化鎳之強化方法
JP2011119472A (ja) * 2009-12-03 2011-06-16 Panasonic Corp 半導体製造装置
JP5615207B2 (ja) * 2011-03-03 2014-10-29 株式会社東芝 半導体装置の製造方法
US8466530B2 (en) 2011-06-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Co-implant for backside illumination sensor
WO2013130191A1 (en) * 2012-02-29 2013-09-06 Applied Materials, Inc. Abatement and strip process chamber in a load lock configuration
US9318367B2 (en) * 2013-02-27 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structure with different fin heights and method for forming the same
JP2015012241A (ja) * 2013-07-01 2015-01-19 ソニー株式会社 撮像素子およびその製造方法、ならびに電子機器
KR102133490B1 (ko) * 2013-11-11 2020-07-13 에스케이하이닉스 주식회사 트랜지스터, 트랜지스터의 제조 방법 및 트랜지스터를 포함하는 전자장치
US9159621B1 (en) * 2014-04-29 2015-10-13 Applied Materials, Inc. Dicing tape protection for wafer dicing using laser scribe process
JP6510310B2 (ja) * 2014-05-12 2019-05-08 ローム株式会社 半導体装置
WO2015195272A1 (en) * 2014-06-20 2015-12-23 Applied Materials, Inc. Methods for reducing semiconductor substrate strain variation
US9613870B2 (en) * 2015-06-30 2017-04-04 International Business Machines Corporation Gate stack formed with interrupted deposition processes and laser annealing

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223425A (ja) * 1999-02-02 2000-08-11 Nec Corp 基板処理装置、ガス供給方法、及び、レーザ光供給方法
JP2001274048A (ja) * 2000-03-24 2001-10-05 Hitachi Ltd 半導体装置の製造方法及び加工装置
CN101009221A (zh) * 2006-01-23 2007-08-01 三菱电机株式会社 半导体装置的制造方法
CN102420176A (zh) * 2011-06-15 2012-04-18 上海华力微电子有限公司 一种改善半导体晶片翘曲的方法
CN103094098A (zh) * 2013-01-14 2013-05-08 陆伟 一种解决晶圆破片的方法
US20150294917A1 (en) * 2014-04-09 2015-10-15 Tokyo Electron Limited Method for Correcting Wafer Bow from Overlay

Also Published As

Publication number Publication date
KR102584138B1 (ko) 2023-10-04
KR20230152092A (ko) 2023-11-02
US10128197B2 (en) 2018-11-13
DE112016005136T5 (de) 2018-07-26
TWI729498B (zh) 2021-06-01
CN116435167A (zh) 2023-07-14
TW202015095A (zh) 2020-04-16
KR20180069920A (ko) 2018-06-25
TW201727696A (zh) 2017-08-01
CN116435172A (zh) 2023-07-14
US20170133328A1 (en) 2017-05-11
WO2017083037A1 (en) 2017-05-18
JP6971229B2 (ja) 2021-11-24
TWI675393B (zh) 2019-10-21
CN108352298A (zh) 2018-07-31
JP2018536990A (ja) 2018-12-13

Similar Documents

Publication Publication Date Title
CN108352298B (zh) 底部处理
US10020204B2 (en) Bottom processing
TWI692047B (zh) 用於epi製程之晶圓加熱的二極體雷射
US7109087B2 (en) Absorber layer for DSA processing
US8999798B2 (en) Methods for forming NMOS EPI layers
EP3329510B1 (en) Rotating substrate laser anneal
US9263265B2 (en) Crystallization of amorphous films and grain growth using combination of laser and rapid thermal annealing
US7838431B2 (en) Method for surface treatment of semiconductor substrates
KR102126119B1 (ko) 열처리 방법
US20070243721A1 (en) Absorber layer for dsa processing
US7643736B2 (en) Apparatus and method for manufacturing semiconductor devices
WO2011066548A1 (en) Laser doping
TWI768238B (zh) 半導體形成裝置與半導體裝置的形成方法
KR20050084592A (ko) 매립된 종을 선형으로 포커싱하는 레이저-어닐링
US6762136B1 (en) Method for rapid thermal processing of substrates
TW202029384A (zh) 用於epi製程之晶圓加熱的二極體雷射
KR20040032631A (ko) 레이저 어닐링 장비 및 이를 이용한 박막트랜지스터의제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant