JPS55111140A - Metalizing method for back surface of silicon wafer - Google Patents

Metalizing method for back surface of silicon wafer

Info

Publication number
JPS55111140A
JPS55111140A JP1883179A JP1883179A JPS55111140A JP S55111140 A JPS55111140 A JP S55111140A JP 1883179 A JP1883179 A JP 1883179A JP 1883179 A JP1883179 A JP 1883179A JP S55111140 A JPS55111140 A JP S55111140A
Authority
JP
Japan
Prior art keywords
approximately
thickness
layer
silicon wafer
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1883179A
Other languages
Japanese (ja)
Inventor
Hiromi Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1883179A priority Critical patent/JPS55111140A/en
Publication of JPS55111140A publication Critical patent/JPS55111140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To eliminate contamination on the surface of an element due to the conventional wet Ni plating process by a method wherein the application of Ni and next of Au by evaporation is performed sequentially and moreover the metalization for mounting is formed by heat treatment at temperature below the eutetic temperature of Au-Si.
CONSTITUTION: After polishing the back surface of silicon wafer 1 to get the disired thickness, etching the polished surface several μm by chemical process and the surface is kept clean by fluoric acid treatment. Next Ni film of approximately 1,500W 5,000Å thickness is applied by vacuum evaporation and continuously Au film of approximately 1,500W2,000Å thickness is applied by vacuum evaporation, and thus Ni layer 2 and Au layer 4 is formed. Next by performing heat treatment about 30min in N2 atmosphere at approximately 350°C which is lower than Au-Si eutectic temperature the sintered Ni layer 3 is formed. By this method elimination of surface contamination of the element due to the conventional Ni wet plating method is achievable and in addition to this, reduction of metalizing process is achievable too.
COPYRIGHT: (C)1980,JPO&Japio
JP1883179A 1979-02-20 1979-02-20 Metalizing method for back surface of silicon wafer Pending JPS55111140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1883179A JPS55111140A (en) 1979-02-20 1979-02-20 Metalizing method for back surface of silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1883179A JPS55111140A (en) 1979-02-20 1979-02-20 Metalizing method for back surface of silicon wafer

Publications (1)

Publication Number Publication Date
JPS55111140A true JPS55111140A (en) 1980-08-27

Family

ID=11982500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1883179A Pending JPS55111140A (en) 1979-02-20 1979-02-20 Metalizing method for back surface of silicon wafer

Country Status (1)

Country Link
JP (1) JPS55111140A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070173045A1 (en) * 2006-01-23 2007-07-26 Mitsubishi Electric Corporation Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070173045A1 (en) * 2006-01-23 2007-07-26 Mitsubishi Electric Corporation Method of manufacturing semiconductor device
US8183144B2 (en) * 2006-01-23 2012-05-22 Mitsubishi Electric Corporation Method of manufacturing semiconductor device

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