JPS56103432A - Production of semiconductor - Google Patents
Production of semiconductorInfo
- Publication number
- JPS56103432A JPS56103432A JP671680A JP671680A JPS56103432A JP S56103432 A JPS56103432 A JP S56103432A JP 671680 A JP671680 A JP 671680A JP 671680 A JP671680 A JP 671680A JP S56103432 A JPS56103432 A JP S56103432A
- Authority
- JP
- Japan
- Prior art keywords
- 20min
- thin film
- substrate
- vacuum
- back electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE:To provide a back electrode with a stable Ai-Si eutectic layer at a low cost without use of any heat treatment furnace or the like. CONSTITUTION:A given element region is formed on an N expitaxial layer on an N type si substrate. First the substrate is treated in a fluoric acid liquid and washed with pure water. Then, an Au thin film 2 is vacuum evaporated on the back thereof and treated under vacuum at 380 deg.C for about 20min by infrared rays to form an Au-Si eutectic layer 3. After cooled for about 20min, the Au thin film 2 undergoes a vacuum evaporation again to complete a back electrode. With such an arrangement, evaporation and backing are consistently performed thereby minimizing damage to a wafer. Less use of Au can reduce the raw cost.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP671680A JPS56103432A (en) | 1980-01-22 | 1980-01-22 | Production of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP671680A JPS56103432A (en) | 1980-01-22 | 1980-01-22 | Production of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56103432A true JPS56103432A (en) | 1981-08-18 |
Family
ID=11645981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP671680A Pending JPS56103432A (en) | 1980-01-22 | 1980-01-22 | Production of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56103432A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4702941A (en) * | 1984-03-27 | 1987-10-27 | Motorola Inc. | Gold metallization process |
EP2693465A1 (en) * | 2012-07-31 | 2014-02-05 | Nxp B.V. | Electronic device and method of manufacturing such device |
-
1980
- 1980-01-22 JP JP671680A patent/JPS56103432A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4702941A (en) * | 1984-03-27 | 1987-10-27 | Motorola Inc. | Gold metallization process |
EP2693465A1 (en) * | 2012-07-31 | 2014-02-05 | Nxp B.V. | Electronic device and method of manufacturing such device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS56103432A (en) | Production of semiconductor | |
JPS5269589A (en) | Semiconductor capacity element | |
JPS5688317A (en) | Manufacture of semiconductor device | |
JPS551109A (en) | Manufacture of semiconductor device | |
JPS5420671A (en) | Production of semiconductor devices | |
JPS5694736A (en) | Manufacturing method of semiconductor device | |
JPS54159186A (en) | Semiconductor device | |
JPS5642367A (en) | Manufacture of bipolar integrated circuit | |
JPS5475273A (en) | Manufacture of semiconductor device | |
JPS54157496A (en) | Manufacture of tunnel junction | |
JPS6443922A (en) | Formation of superconductive thin film | |
JPS5232671A (en) | Manufacturing process of semiconductor device | |
JPS5633844A (en) | Semiconductor device and manufacture therefor | |
JPS5516425A (en) | Semiconductor device | |
JPS6450472A (en) | Amorphous semiconductor solar cell | |
JPS55162240A (en) | Semiconductor device and its manufacture | |
JPS524170A (en) | Manufacturing process of semiconductor element | |
JPS5688374A (en) | Evaporated thin film diode | |
JPS54137276A (en) | Semiconductor device | |
JPS5498570A (en) | Manufacture for semiconductor device | |
JPS5313369A (en) | Manufacture of semiconductor | |
JPS5650528A (en) | Semiconductor integrated circuit and manufacture thereof | |
JPS5728353A (en) | Manufacture of semiconductor device | |
JPS5336180A (en) | Production of semiconductor device | |
JPS5271980A (en) | Formation of metal wiring |