JPS54157496A - Manufacture of tunnel junction - Google Patents

Manufacture of tunnel junction

Info

Publication number
JPS54157496A
JPS54157496A JP6584178A JP6584178A JPS54157496A JP S54157496 A JPS54157496 A JP S54157496A JP 6584178 A JP6584178 A JP 6584178A JP 6584178 A JP6584178 A JP 6584178A JP S54157496 A JPS54157496 A JP S54157496A
Authority
JP
Japan
Prior art keywords
electrode
layer
junction
mask
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6584178A
Other languages
Japanese (ja)
Other versions
JPS5733713B2 (en
Inventor
Kenichi Kuroda
Akira Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6584178A priority Critical patent/JPS54157496A/en
Publication of JPS54157496A publication Critical patent/JPS54157496A/en
Publication of JPS5733713B2 publication Critical patent/JPS5733713B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To avoid the contamination as well as to increase both the yield and the reliability by carrying out continuously in the vacuum state the processes of the electrode formation from the lower junction to the upper junction with no photo etching process. CONSTITUTION:First wiring layer 2 of the lead is provided to Si substrate 1, and only the junction scheduled region is exposed via resist mask 3-1. Then lower junction electrode 6 of the superconductor (lead), tunnel layer 4 and upper junction electrode 7 are laminated each through evaporation. The tunnel layer is the surface oxide film of electrode 6 or the evaporation film of other insulator and semiconductor. Mask 3-1 is then removed and insulator 8 is coated with an aperture drilled to layer 4. Then lead second wiring layer 5 is evaporated on part of layer 8 as well as on electrode 7 via mask 3-2, and then mask 3-2 is removed to complete the manufacture. In this method, the surfaces of the upper and lower junction electrodes are never contaminated with no evil effect given to formation of the tunnel layer. This effect is more enhanced is the oxide film of the lower junction electrode is used to the tunnel layer.
JP6584178A 1978-06-02 1978-06-02 Manufacture of tunnel junction Granted JPS54157496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6584178A JPS54157496A (en) 1978-06-02 1978-06-02 Manufacture of tunnel junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6584178A JPS54157496A (en) 1978-06-02 1978-06-02 Manufacture of tunnel junction

Publications (2)

Publication Number Publication Date
JPS54157496A true JPS54157496A (en) 1979-12-12
JPS5733713B2 JPS5733713B2 (en) 1982-07-19

Family

ID=13298634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6584178A Granted JPS54157496A (en) 1978-06-02 1978-06-02 Manufacture of tunnel junction

Country Status (1)

Country Link
JP (1) JPS54157496A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054485A (en) * 1983-09-05 1985-03-28 Agency Of Ind Science & Technol Manufacture of josephson junction
WO2001047042A1 (en) * 1999-12-22 2001-06-28 Nanoway Oy Method for stabilizing a tunnel junction component and a stabilized tunnel junction component
CN111279497A (en) * 2017-11-07 2020-06-12 国际商业机器公司 Shadow mask area correction for tunnel junctions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282090A (en) * 1975-12-27 1977-07-08 Fujitsu Ltd Apparatus and manufacture for superconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282090A (en) * 1975-12-27 1977-07-08 Fujitsu Ltd Apparatus and manufacture for superconductor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054485A (en) * 1983-09-05 1985-03-28 Agency Of Ind Science & Technol Manufacture of josephson junction
WO2001047042A1 (en) * 1999-12-22 2001-06-28 Nanoway Oy Method for stabilizing a tunnel junction component and a stabilized tunnel junction component
US6780684B2 (en) 1999-12-22 2004-08-24 Nanoway Oy Stabilized tunnel junction component
CN111279497A (en) * 2017-11-07 2020-06-12 国际商业机器公司 Shadow mask area correction for tunnel junctions
JP2021503171A (en) * 2017-11-07 2021-02-04 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ A method for correcting the overlapping area between two films produced by sequential shadow mask deposition and a method for forming a bond.
CN111279497B (en) * 2017-11-07 2023-12-26 国际商业机器公司 Shadow mask area correction for tunnel junctions

Also Published As

Publication number Publication date
JPS5733713B2 (en) 1982-07-19

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