BR0207798A - Circuitos integrados analógicos e digitais mistos - Google Patents
Circuitos integrados analógicos e digitais mistosInfo
- Publication number
- BR0207798A BR0207798A BR0207798-1A BR0207798A BR0207798A BR 0207798 A BR0207798 A BR 0207798A BR 0207798 A BR0207798 A BR 0207798A BR 0207798 A BR0207798 A BR 0207798A
- Authority
- BR
- Brazil
- Prior art keywords
- inserts
- analog
- digital
- insert
- integrated circuits
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
"CIRCUITOS INTEGRADOS ANALóGICOS E DIGITAIS MISTOS". Trata-se de técnicas para fabricar circuitos analógicos e digitais em pastilhas separadas e empilhar e integrar as pastilhas dentro de um único pacote, de modo a formar um IC de sinais misturados que apresenta muitas vantagens. Sob um aspecto, os circuitos analógicos e digitais são implementados em duas pastilhas separadas por meio de processos de IC possivelmente diferentes adequados para estes tipos diferentes de circuitos. As pastilhas analógica e digital são em seguida integradas (empilhadas) e encapsuladas dentro do pacote único. São apresentados blocos de ligação para interligar as pastilhas e para ligar as pastilhas a pinos externos. Os blocos de ligação podem ser localizados e dispostos de maneira a proporcionarem a necessária conectividade enquanto minimizam a quantidade de área de pastilha requerida para implementar os blocos. Sob outro aspecto, a conectividade de pastilha com pastilha pode ser testada em conjunto com uma interface de barramento serial.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/798,198 US6472747B2 (en) | 2001-03-02 | 2001-03-02 | Mixed analog and digital integrated circuits |
PCT/US2002/005405 WO2002071486A2 (en) | 2001-03-02 | 2002-02-22 | Mixed analog and digital integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
BR0207798A true BR0207798A (pt) | 2004-07-06 |
Family
ID=25172776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR0207798-1A BR0207798A (pt) | 2001-03-02 | 2002-02-22 | Circuitos integrados analógicos e digitais mistos |
Country Status (11)
Country | Link |
---|---|
US (1) | US6472747B2 (pt) |
EP (1) | EP1407491A2 (pt) |
JP (5) | JP2004523912A (pt) |
KR (4) | KR20080050637A (pt) |
CN (1) | CN100355071C (pt) |
AU (1) | AU2002238123A1 (pt) |
BR (1) | BR0207798A (pt) |
HK (1) | HK1062958A1 (pt) |
MY (1) | MY122792A (pt) |
TW (1) | TWI246737B (pt) |
WO (1) | WO2002071486A2 (pt) |
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- 2002-02-22 WO PCT/US2002/005405 patent/WO2002071486A2/en active Application Filing
- 2002-02-22 BR BR0207798-1A patent/BR0207798A/pt not_active Application Discontinuation
- 2002-02-25 TW TW091103280A patent/TWI246737B/zh not_active IP Right Cessation
- 2002-02-27 MY MYPI20020686A patent/MY122792A/en unknown
-
2004
- 2004-08-05 HK HK04105812A patent/HK1062958A1/xx not_active IP Right Cessation
-
2009
- 2009-01-05 JP JP2009000324A patent/JP2009152616A/ja active Pending
-
2013
- 2013-08-19 JP JP2013169931A patent/JP5931814B2/ja not_active Expired - Lifetime
-
2014
- 2014-07-18 JP JP2014148230A patent/JP6537789B2/ja not_active Expired - Lifetime
-
2017
- 2017-09-14 JP JP2017176737A patent/JP2018022903A/ja not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
HK1062958A1 (en) | 2004-12-03 |
EP1407491A2 (en) | 2004-04-14 |
JP5931814B2 (ja) | 2016-06-08 |
WO2002071486A3 (en) | 2003-12-24 |
JP2018022903A (ja) | 2018-02-08 |
KR100862405B1 (ko) | 2008-10-08 |
CN100355071C (zh) | 2007-12-12 |
JP6537789B2 (ja) | 2019-07-03 |
WO2002071486A2 (en) | 2002-09-12 |
JP2014241422A (ja) | 2014-12-25 |
TWI246737B (en) | 2006-01-01 |
KR20080050637A (ko) | 2008-06-09 |
AU2002238123A1 (en) | 2002-09-19 |
JP2009152616A (ja) | 2009-07-09 |
CN1498423A (zh) | 2004-05-19 |
KR20090077026A (ko) | 2009-07-13 |
MY122792A (en) | 2006-05-31 |
US6472747B2 (en) | 2002-10-29 |
KR20080050638A (ko) | 2008-06-09 |
KR100940404B1 (ko) | 2010-02-02 |
JP2014013918A (ja) | 2014-01-23 |
KR20040030519A (ko) | 2004-04-09 |
US20020121679A1 (en) | 2002-09-05 |
JP2004523912A (ja) | 2004-08-05 |
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