ATE417357T1 - Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sind - Google Patents
Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sindInfo
- Publication number
- ATE417357T1 ATE417357T1 AT04707086T AT04707086T ATE417357T1 AT E417357 T1 ATE417357 T1 AT E417357T1 AT 04707086 T AT04707086 T AT 04707086T AT 04707086 T AT04707086 T AT 04707086T AT E417357 T1 ATE417357 T1 AT E417357T1
- Authority
- AT
- Austria
- Prior art keywords
- balls
- solder balls
- dummy
- package
- area
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/121—Arrangements for protection of devices protecting against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44381703P | 2003-01-30 | 2003-01-30 | |
| US10/393,666 US6762495B1 (en) | 2003-01-30 | 2003-03-20 | Area array package with non-electrically connected solder balls |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE417357T1 true ATE417357T1 (de) | 2008-12-15 |
Family
ID=32684776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04707086T ATE417357T1 (de) | 2003-01-30 | 2004-01-30 | Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sind |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6762495B1 (de) |
| EP (1) | EP1588407B1 (de) |
| AT (1) | ATE417357T1 (de) |
| DE (1) | DE602004018268D1 (de) |
| WO (1) | WO2004068560A2 (de) |
Families Citing this family (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7310458B2 (en) | 2001-10-26 | 2007-12-18 | Staktek Group L.P. | Stacked module systems and methods |
| US6914324B2 (en) | 2001-10-26 | 2005-07-05 | Staktek Group L.P. | Memory expansion and chip scale stacking system and method |
| US6940729B2 (en) | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
| US7371609B2 (en) | 2001-10-26 | 2008-05-13 | Staktek Group L.P. | Stacked module systems and methods |
| US20030234443A1 (en) | 2001-10-26 | 2003-12-25 | Staktek Group, L.P. | Low profile stacking system and method |
| US20060255446A1 (en) | 2001-10-26 | 2006-11-16 | Staktek Group, L.P. | Stacked modules and method |
| US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
| US6956284B2 (en) | 2001-10-26 | 2005-10-18 | Staktek Group L.P. | Integrated circuit stacking system and method |
| US7485951B2 (en) | 2001-10-26 | 2009-02-03 | Entorian Technologies, Lp | Modularized die stacking system and method |
| US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
| US20040227233A1 (en) * | 2003-05-16 | 2004-11-18 | Nokia Corporation | Interconnection pattern design |
| US7542304B2 (en) | 2003-09-15 | 2009-06-02 | Entorian Technologies, Lp | Memory expansion and integrated circuit stacking system and method |
| JP3844079B2 (ja) * | 2003-10-27 | 2006-11-08 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| US7476040B2 (en) * | 2004-02-02 | 2009-01-13 | Jds Uniphase Corporation | Compact optical sub-assembly with ceramic package |
| US7357293B2 (en) * | 2004-03-24 | 2008-04-15 | Intel Corporation | Soldering an electronics package to a motherboard |
| US7095107B2 (en) * | 2004-12-07 | 2006-08-22 | Lsi Logic Corporation | Ball assignment schemes for integrated circuit packages |
| JP2006222374A (ja) * | 2005-02-14 | 2006-08-24 | Fuji Film Microdevices Co Ltd | 半導体チップ |
| US7391122B1 (en) * | 2005-03-04 | 2008-06-24 | Altera Corporation | Techniques for flip chip package migration |
| US7215026B2 (en) * | 2005-04-14 | 2007-05-08 | Samsung Electonics Co., Ltd | Semiconductor module and method of forming a semiconductor module |
| US7033861B1 (en) * | 2005-05-18 | 2006-04-25 | Staktek Group L.P. | Stacked module systems and method |
| JP2006344824A (ja) * | 2005-06-09 | 2006-12-21 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
| US20070252252A1 (en) * | 2006-04-28 | 2007-11-01 | Powertech Technology Inc. | Structure of electronic package and printed circuit board thereof |
| US7417310B2 (en) * | 2006-11-02 | 2008-08-26 | Entorian Technologies, Lp | Circuit module having force resistant construction |
| US7573115B2 (en) * | 2006-11-13 | 2009-08-11 | International Business Machines Corporation | Structure and method for enhancing resistance to fracture of bonding pads |
| US20090078745A1 (en) * | 2007-09-26 | 2009-03-26 | Ee Hua Wong | Method for forming interconnects |
| US7646105B2 (en) * | 2007-11-16 | 2010-01-12 | Stats Chippac Ltd. | Integrated circuit package system with package substrate having corner contacts |
| US20090152659A1 (en) * | 2007-12-18 | 2009-06-18 | Jari Hiltunen | Reflowable camera module with improved reliability of solder connections |
| US20090160475A1 (en) * | 2007-12-20 | 2009-06-25 | Anwar Ali | Test pin reduction using package center ball grid array |
| US8525333B2 (en) * | 2008-03-17 | 2013-09-03 | Renesas Electronics Corporation | Electronic device and manufacturing method therefor |
| US8212350B2 (en) * | 2009-04-06 | 2012-07-03 | Intel Corporation | Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates |
| JP5340047B2 (ja) * | 2009-06-12 | 2013-11-13 | パナソニック株式会社 | 半導体集積回路装置 |
| JP5870303B2 (ja) | 2010-08-06 | 2016-02-24 | パナソニックIpマネジメント株式会社 | 回路基板及びその製造方法 |
| US20120032327A1 (en) * | 2010-08-09 | 2012-02-09 | Fujitsu Limited | Systems and methods for reinforcing chip packages |
| FR2967328B1 (fr) * | 2010-11-10 | 2012-12-21 | Sierra Wireless Inc | Circuit electronique comprenant une face de report sur laquelle sont agences des plots de contact |
| JP5878823B2 (ja) * | 2012-05-15 | 2016-03-08 | 太陽誘電株式会社 | 複合電子部品 |
| US8987884B2 (en) | 2012-08-08 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package assembly and methods for forming the same |
| US8927417B2 (en) | 2012-12-18 | 2015-01-06 | Freescale Semiconductor, Inc. | Semiconductor package signal routing using conductive vias |
| JP6344919B2 (ja) * | 2014-01-21 | 2018-06-20 | キヤノン株式会社 | プリント回路板及び積層型半導体装置 |
| US9245940B2 (en) * | 2014-02-12 | 2016-01-26 | Qualcomm Incorporated | Inductor design on floating UBM balls for wafer level package (WLP) |
| JP6371583B2 (ja) | 2014-05-20 | 2018-08-08 | ローム株式会社 | 半導体パッケージ、pcb基板および半導体装置 |
| US10104772B2 (en) | 2014-08-19 | 2018-10-16 | International Business Machines Incorporated | Metallized particle interconnect with solder components |
| US9922920B1 (en) | 2016-09-19 | 2018-03-20 | Nanya Technology Corporation | Semiconductor package and method for fabricating the same |
| JP6726309B2 (ja) * | 2017-01-05 | 2020-07-22 | 華為技術有限公司Huawei Technologies Co.,Ltd. | 高信頼性電子パッケージ構造、回路基板及びデバイス |
| KR102351428B1 (ko) * | 2017-09-29 | 2022-01-17 | 가부시키가이샤 아이신 | 회로 기판, 회로 기판의 설계 방법, 및 반도체 장치 |
| JP7524632B2 (ja) * | 2020-06-29 | 2024-07-30 | 日本電気株式会社 | 量子デバイス |
| KR102822948B1 (ko) | 2020-08-12 | 2025-06-20 | 삼성전자주식회사 | 배선 구조물 및 이를 포함하는 반도체 칩 |
| KR102952764B1 (ko) * | 2021-10-14 | 2026-04-17 | 삼성전자주식회사 | 반도체 패키지 |
| KR20230060092A (ko) * | 2021-10-27 | 2023-05-04 | 삼성전자주식회사 | 패키지 기판 및 이를 포함하는 반도체 패키지 |
| JP2023171042A (ja) * | 2022-05-20 | 2023-12-01 | ローム株式会社 | 半導体装置 |
Family Cites Families (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
| US5960319A (en) * | 1995-10-04 | 1999-09-28 | Sharp Kabushiki Kaisha | Fabrication method for a semiconductor device |
| JPH1070153A (ja) * | 1996-08-26 | 1998-03-10 | Hitachi Ltd | 電子部品の接続方法 |
| JP4311774B2 (ja) * | 1998-03-11 | 2009-08-12 | 富士通株式会社 | 電子部品パッケージおよびプリント配線板 |
| JPH11297872A (ja) * | 1998-04-13 | 1999-10-29 | Mitsubishi Electric Corp | 半導体装置 |
| US6323559B1 (en) * | 1998-06-23 | 2001-11-27 | Lsi Logic Corporation | Hexagonal arrangements of bump pads in flip-chip integrated circuits |
| US6118182A (en) * | 1998-06-25 | 2000-09-12 | Intel Corporation | Integrated circuit package with rectangular contact pads |
| JP3201353B2 (ja) * | 1998-08-04 | 2001-08-20 | 日本電気株式会社 | 半導体装置とその製造方法 |
| US6229218B1 (en) * | 1998-11-06 | 2001-05-08 | Mcms, Inc. | Interconnect device and method for mating dissimilar electronic package footprints |
| JP3179420B2 (ja) * | 1998-11-10 | 2001-06-25 | 日本電気株式会社 | 半導体装置 |
| US6552425B1 (en) * | 1998-12-18 | 2003-04-22 | Intel Corporation | Integrated circuit package |
| JP3437107B2 (ja) * | 1999-01-27 | 2003-08-18 | シャープ株式会社 | 樹脂封止型半導体装置 |
| US6365978B1 (en) * | 1999-04-02 | 2002-04-02 | Texas Instruments Incorporated | Electrical redundancy for improved mechanical reliability in ball grid array packages |
| US6246121B1 (en) * | 1999-04-12 | 2001-06-12 | Vlsi Technology, Inc. | High performance flip-chip semiconductor device |
| JP3343730B2 (ja) * | 1999-08-27 | 2002-11-11 | 埼玉日本電気株式会社 | 実装基板及び電気部品の実装方法 |
| US6285560B1 (en) * | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
| JP2001217355A (ja) * | 1999-11-25 | 2001-08-10 | Hitachi Ltd | 半導体装置 |
| US6657124B2 (en) * | 1999-12-03 | 2003-12-02 | Tony H. Ho | Advanced electronic package |
| US6242815B1 (en) * | 1999-12-07 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Flexible substrate based ball grid array (BGA) package |
| US6661082B1 (en) * | 2000-07-19 | 2003-12-09 | Fairchild Semiconductor Corporation | Flip chip substrate design |
| US6448639B1 (en) * | 2000-09-18 | 2002-09-10 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
| US6403896B1 (en) * | 2000-09-27 | 2002-06-11 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
| US6492254B2 (en) * | 2001-01-31 | 2002-12-10 | Bae Systems Information And Electronic Systems Integration, Inc. | Ball grid array (BGA) to column grid array (CGA) conversion process |
| TW484172B (en) * | 2001-02-15 | 2002-04-21 | Au Optronics Corp | Metal bump |
| US6696763B2 (en) * | 2001-04-02 | 2004-02-24 | Via Technologies, Inc. | Solder ball allocation on a chip and method of the same |
| JP4746770B2 (ja) * | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2003100801A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置 |
| US6617699B2 (en) * | 2001-11-29 | 2003-09-09 | Sun Microsystems, Inc. | 120 degree bump placement layout for an integrated circuit power grid |
| JP2003258154A (ja) * | 2002-03-05 | 2003-09-12 | Fujitsu Ltd | 半導体素子の実装構造 |
| US6667561B2 (en) * | 2002-03-13 | 2003-12-23 | Globespanvirata, Incorporated | Integrated circuit capable of operating in multiple orientations |
-
2003
- 2003-03-20 US US10/393,666 patent/US6762495B1/en not_active Expired - Lifetime
-
2004
- 2004-01-30 EP EP04707086A patent/EP1588407B1/de not_active Expired - Lifetime
- 2004-01-30 WO PCT/US2004/002716 patent/WO2004068560A2/en not_active Ceased
- 2004-01-30 AT AT04707086T patent/ATE417357T1/de not_active IP Right Cessation
- 2004-01-30 DE DE602004018268T patent/DE602004018268D1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1588407A2 (de) | 2005-10-26 |
| WO2004068560A3 (en) | 2004-10-07 |
| DE602004018268D1 (de) | 2009-01-22 |
| US6762495B1 (en) | 2004-07-13 |
| EP1588407B1 (de) | 2008-12-10 |
| WO2004068560A2 (en) | 2004-08-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |